JPH0559436B2 - - Google Patents

Description

[Detailed description of the invention]

A. Technical Field of the Invention The present invention relates to a parameter setting device for an electronic musical instrument that sets parameter information for musical tone formation, and more specifically, parameter information set by various operators or parameter information displayed on various display elements. It is related to input/output control. B. Prior Art As is well known, electronic musical instruments have many operators that set various parameter information for controlling various musical sound elements such as pitch, timbre, and volume, and many controllers that display the set parameter information. A display element is provided. These operators and display elements are placed on an operation panel provided near the keyboard section at appropriate positions taking into consideration operability and visibility by the player. However, in the past, the parameter information set by these operators or the parameter information displayed on the display elements was input/output by connecting the input/output line to the main body for each operator or each display element. Therefore, the wiring state on the back surface of the operation panel becomes very complicated, and the length of the wiring becomes enormous, resulting in poor operability and increased cost. C. Purpose of the Invention This invention was made in view of these drawbacks, and its purpose is to simplify the wiring of signal lines for inputting and outputting parameter information between many operators and display elements. An object of the present invention is to provide a parameter setting device for an electronic musical instrument. D. Summary of the Invention To this end, the present invention provides a plurality of operator circuits each including at least one of an operator for setting parameter data for musical tone formation and a display element for displaying the parameter data; If the parameter data is set by the parameter data, the musical tone is formed according to the parameter data, otherwise, the musical tone is formed by a predetermined method, and if the parameter data is to be displayed, the display data of the generated parameter data is In a parameter setting device for an electronic musical instrument consisting of a main device that supplies the circuit,
a plurality of sub-devices that are provided corresponding to each of the manipulator circuits and transmit M-bit (M: positive integer) data in parallel to and from the manipulator circuit; A data signal line that connects the devices in series and a data signal line that is commonly provided to the plurality of sub devices,
A control signal line is provided to connect the main device and the plurality of sub-devices, and the main device communicates N bits (N bits) between the main device and the plurality of sub-devices via the data signal line. : positive integer) data bit by bit. In addition, the control signal line can be shared by a plurality of sub-devices. In general, parameter information (parameter data) used for musical tone formation in electronic musical instruments includes direct parameter information that directly controls musical tone elements such as pitch and timbre of musical tones, and direct parameter information that is stored in advance in memory, etc. Although there is indirect parameter information that specifies the parameter information, the parameter setting device according to the present invention can be applied to setting either the above-mentioned direct or indirect parameter information. E. Description of Embodiments (A) Configuration Description FIG. 1 is a block diagram showing an embodiment of a parameter setting device according to the present invention. In this embodiment, the parameter information includes effect selection information for selecting an effect such as a vibrato effect, timbre selection information for selecting the basic timbre of musical tones such as piano and harpsichord, and multiple types of information stored in advance in the preset memory. Preset selection information for selecting a specific set of preset information from a plurality of sets of preset information each including parameter information is set. These parameter information, for example, in the case of timbre selection information, is set by turning on a non-locking pushbutton switch provided corresponding to the desired timbre. Further, in this embodiment, not only the above parameter information is set, but also the setting state of this parameter information is displayed by lighting the light emitting diode. In FIG. 1, reference numeral 1 denotes a group of operator circuits for setting parameter information and displaying the setting status, which includes a large number of non-locking pushbutton switches 101 to 116 and light emitting diodes 117 to 116.
132 are divided into eight sets of operator circuits 10-1 to 10-8. 2 are switches 101 to 11 of operator circuit group 1
6, and outputs setting state information of the parameter information to the light emitting diodes 117 to 132 of the operator circuit group 1 and controls the output. processing device 20,
Program memory 21, working memory 2
2, a preset memory 23 and an interface circuit 24. 3 is the operation mode control signal C ₀ from the main device 2;
A sub-device group that receives C ₁ and mediates information transmission between the control circuit group 1 and the main device 2, and here the control circuit 10- in the control circuit group 1.
Eight sets of sub-devices 30-1 corresponding to 1 to 10-8
~30-8 are provided, and each sub-device 30-1 to 30-3 is provided.
0-8 is the corresponding set of operator circuits 10-
1 to 10-8 using 8-bit parallel signals for each controller circuit. Furthermore, between the sub-devices of each group, the serial signal output terminal _S0 of the sub-device 30-1 of the first group is connected to the serial signal input terminal Si of the sub-device 30-2 of the second group, and The serial signal output terminal S ₀ of the second set of sub-devices 30-2 is connected to the serial signal input terminal Si of the third set of sub-devices 30-3.
The serial signal input/output lines are connected in series, and then the first set of sub-devices 3
Connect the serial signal input terminal Si of 0-1 to the serial signal output terminal S ₀ of the main device 2, and connect the serial signal output terminal S ₀ of the eighth sub device 30-8 to the serial signal input terminal of the main device 2. They are coupled by a ring-shaped serial signal transmission loop formed by connecting to Si. The information transmission between the sub-device group 3 and the main device 2 is performed by an 8-bit serial signal for each set of sub-devices using the serial signal transmission loop. Sub-devices 30-1 to 30-1 constituting this sub-device group 3
30-8 includes a decoder 300 that decodes the operation mode control signals C ₀ and C ₁ from the main device 2, a serial input/output function, and a parallel A register circuit 301 with an 8-bit signal storage location and an input/output function, a latch circuit 302 with an 8-bit signal storage location, an inverter 303, and a gate circuit 304 with an 8-bit signal input/output gate. It is composed of. And each of these sub-devices 30-1 to 30
-8 is a mode in which parameter information set in the corresponding set of operator circuits 10-1 to 10-8 is read into the register circuit 301 by the operation mode control signals C ₀ and C ₁ given from the main device 2. and a shift mode in which serial signals input from the main device 2 to the register circuit 301 via the serial signal transmission loop are sequentially shifted.
After the shift mode ends, there is a hold mode in which the serial signals stored in each storage location of the register circuit 301 are held, and a serial signal stored in each storage location in the register circuit 301 is sent to the latch circuit 302 as an 8-bit parallel signal. It is controlled into four operation modes including a load mode in which the data is stored and sent to the operator circuits 10-1 to 10-8 via the gate circuit 304. By the way, in each of the operator circuits 10-1 to 10-8 constituting the operator circuit group 1, the following parameter information is set, and the setting status information is displayed. That is, the operator circuit 10
-1, preset select information is set to select any one of eight sets of preset information, one set of which is a plurality of types of parameter information stored in advance in the preset memory 23 of the main device 2. . This preset selection information is set by turning on any one of the pushbutton switches 101-108. For example, when selecting the first set of preset information, by turning on the switch 101, preset selection information for selecting this preset information is set. Next, in the operator circuit 10-2, the setting state of the preset selection information by the switches 101 to 108 is determined by the issuing diodes 117 to 1.
24 is lit. The setting state of the preset selection information is the control circuit 10-1.
The preset select setting status information corresponding to the preset select information set in the sub device 3
It is displayed by being given from 0-2. For example, when preset select information that selects the first set of preset information is set, preset select setting state information with an 8-bit signal configuration of "10000000" is given, and the light emitting diode 117 is turned on. The setting status will be displayed. Next, in the operator circuit 10-3, tone selection information for selecting a basic tone of a musical tone such as a piano is set by turning on the switches 109 to 112, and the setting state is indicated by the lighting of the sending diodes 125 to 128. Displayed by. For example, when the switch 109 is turned on, tone selection information for selecting a piano tone is set. The setting state is displayed by lighting the light emitting diode 125 when tone color selection state display information "01000000" corresponding to the piano tone color selection information is provided from the sub device 30-3. Next, in the operator circuit 10-8, effect selection information for selecting an effect such as vibrato is set by turning on the switches 113 to 115, and the setting state is changed to the light emitting diode 1.
It is displayed by lighting 29 to 131. Further, in this operator circuit 10-8, write command information for storing parameter information such as timbre selection information in the preset memory 23 of the main device 2 is input by turning on the switch 116, and the input state is light emitting diode 13
It is displayed by lighting 2. In this operator circuit 10-8, when the switch 113 is turned on, for example, effect selection information of "10000000" for selecting a vibrato effect is set. This setting state is "01000000" which corresponds to the effect selection information of the vibrato effect.
By receiving the effect selection state display information from the sub device 30-8, the light emitting diode 129
It is displayed by lighting up. Note that other parameter information is set in the operator circuits 10-4 to 10-7. On the other hand, the central processing unit 2 in the main device 2
0 is the sub-device 30-1 to 30- according to the control program stored in the program memory 21 in advance.
Information is transferred to and from the control circuit group 1 by appropriately controlling the operation modes of 8 to the above-mentioned four modes. For such information transfer, the working memory 22 is provided with a memory area as shown in the memory map of FIG. 2a. That is, the working memory 22 has a first buffer memory area that stores parameter information most recently read from the control circuit group 1.
DBUF1 and a second buffer memory area DBUF2 for storing previously read parameter information are provided. Further, there are provided a third buffer memory area DBUF3 for storing parameter information to be transferred to a musical tone forming section (not shown), and a fourth buffer memory area DBUF4 for temporarily storing information necessary for various processes. . In this case, the third buffer memory area
DBUF3 is provided for the following reasons. That is, when transferring parameter information to the musical tone forming section, a configuration is generally considered in which the parameter information set in the operator circuit group 1 is transferred as is. However, in some cases, musically undesirable setting operations may be performed, such as a combination of piano tone selection information and vibrato effect selection information, so the set parameter information may be transferred as is. Sometimes it's not good to do that. Therefore,
In this embodiment, in order to eliminate such a problem, when parameter information in a musically inconsistent relationship is set, one of the parameter information is given priority and the other parameter information is changed to the parameter information in a consistent relationship. The configuration is such that the data is changed and transferred to the tone forming section. Furthermore, in this embodiment, the preset selection information is not directly transferred to the tone forming section, but the preset information corresponding to the preset selection information is read out from the preset memory 23 and sent to the tone forming section. I'm trying to transfer it. Therefore, in order to perform such processing, a separate memory area other than the first buffer memory area DBUF1 described above is required. The third buffer memory area DBUF3 is provided for this reason. On the other hand, the preset memory 23 is configured to be able to store a maximum of "M+N" sets of parameter information necessary for forming one specific musical tone as one set of preset information. Here, as shown in the memory map of Fig. 2b, there are M memory areas.
a random access memory section 23A having PMEM(1) to PMEM(M), in which the performer can freely store desired M sets of preset information;
N memory areas PMEM (M+1) ~ PMEN
(N) and a read-on memory section 23B in which N sets of preset information that are used as standard are stored in advance at the factory stage. Note that the preset information also includes display information corresponding to various parameter information such as effect selection information that constitutes the information.
That is, if the effect selection information constituting a certain set of preset information is, for example, information for selecting a vibrato effect, the light emitting diode 129 of the operator circuit 10-8 indicates that the vibrato effect is selected. Display information for this purpose is also included in this preset information. (b) Description of Operation Next, the operation of the parameter setting device configured as described above will be explained based on the flowchart shown in FIG. First, when the device is powered on, the main device 2
The central processing unit 20 of the program memory 2
According to the control program stored in step 1, the automatic parameter initialization process of step 210 is first executed, and the most standard preset information is read out of the preset information stored in the read-on memory section 23B of the preset memory 23. It is stored in the third buffer memory area DBUF3 of the working memory 22. That is, in order to be able to immediately create musical tones with standard tones after turning on the power without having to perform parameter setting operations each time, the central processing unit 22 selects the most preset information stored in the preset memory 23. Normally, tone preset information is read out and stored in the third buffer memory area DBUF3. Next, the central processing unit 20 performs step 21.
In the display information transfer process 1, a process is executed to transfer display information corresponding to various parameter information included in the preset information stored in the third buffer memory area DBUF3 to the operator circuit group 1. Display information for the operator circuit group 1 is obtained by connecting the serial input/output lines of eight sets of sub-devices 30-1 to 30-8 in series, and
A set of sub-devices 30-1 to 30-8 corresponding to each of the operator circuits 10-1 to 10-8, respectively, using a serial signal transmission loop formed by setting -8 to parameter shift mode.
transferred via. In addition, the display information to the operator circuit group 1 is first transferred to the eighth operator circuit 10-8 located at the end of the serial signal transmission loop, and then to the seventh operator circuit 10-8. Display information for 10-8,...
First, the display information for the first set of operator circuits 10-1 is displayed. The operation modes of the sub devices 30-1 to 30-8 are set to the parameter shift mode all at once each time display information for one set of operator circuits is sent from the main device 2. That is, eight sets of operator circuits 10-1 to 10
The display information for -8 is the sub device 30-1 to 30-3.
Set the operation mode of 0-8 to the parameter shift mode a number of times equal to the number of installations of the device,
The display information for the eighth set of operator circuits 10-8 is sequentially transferred from the main device 2 via the sub devices 30-1 to 30-8. In this case, one set of display information consists of an 8-bit serial signal,
In addition, since each bit is sequentially transferred in synchronization with clock pulses φ _A and φ _B , the parameter shift mode period when transferring this set of display information is set to 8 cycles of clock pulses φ _A and φ _B. . Display information for the eight sets of operator circuits 10-1 to 10-8 is generally transferred through the operations described above. Here, the operation when transferring display information to, for example, the eighth set of operator circuits 10-8 will be described in detail. First, the central processing unit 20 starts with the sub-device 30-
Control information for setting the operation modes 1 to 30-8 to the parameter shift mode is supplied to the interface circuit 24 via the data bus D.BUS. At this time, the central processing unit 20 supplies the read/write control signal R/W of "0" to the interface circuit 24 together with the control information, and stores the control information in the internal register of the interface circuit 24. Thereafter, the central processing unit 20 reads the display information to be transferred to the eighth set of operator circuits 10-1 from the third buffer memory area DBUF3 and supplies it to the interface circuit 24 via the data bus D/BUS. and is stored in a data register inside this circuit 24. Then, on the condition that the interface circuit 24 is given the control information for setting the sub device group 3 to the parameter shift mode and the display information to be displayed on the eighth set of operator circuits 10-8, the interface circuit 24 switches the sub device group 3 to the parameter shift mode. Operation mode control signals C ₀ , C ₁ for setting the operation mode of group 3 to parameter shift mode
is commonly supplied to the sub-devices 30-1 to 30-8. The relationship between the operation modes of the sub-devices 30-1 to 30-8 and their operation mode control signals C ₀ and C ₁ is set as shown in Table 1 below.

[Table] Therefore, at this time, the interface circuit 24 receives the operation mode control signals of C ₀ = “1” and C ₁ = “0”.
Outputs C ₀ and C ₁ . Thereafter, the interface circuit 24 converts the display information stored in the internal data register into an 8-bit serial signal in synchronization with the clock pulses _φA and _φB , and sequentially outputs the data 1 bit at a time from the serial signal output terminal _S0 . Output. The sub-devices 30-1 to 30-8 are operated in this way.
Operation mode control signal with C ₀ = “1” and C ₁ = “0”
When C ₀ and C ₁ are supplied, the decoder 300 decodes the signals C ₀ and C ₁ . Then,
Decoder 300 of each sub-device 30-1 to 30-8
is a mode setting signal for setting the operation mode of its own sub-device to parameter shift mode.
SFT is output, and this mode setting signal SFT is supplied to the register circuit 301 as a shift enable signal. When a shift enable signal is applied to the register circuit 301, while this enable signal is applied, the register circuit 301 generates clock pulses φ _A and φ _B to shift the stored contents of each internal storage location toward the storage location of the output stage. It is configured to sequentially shift the serial signals from the terminal _S0 and to sequentially take in the serial signals input from the serial signal input terminal Si and shift them sequentially in the direction of the storage position of the output stage. Therefore, from the interface circuit 24 C ₀ =
“1”, C ₁ = “0” operation mode control signal C ₀ , C ₁
When is output, the sub-devices 30-1 to 30-8 sequentially take in the serial signals supplied to the serial signal input terminal Si into the internal register circuit 301 and sequentially shift them to the storage position side of the output stage. Set to parameter shift mode. In this case, the interface circuit 24 in the main device 2 receives the operation mode control signal of C ₀ = “1”.
The number of occurrences of clock pulses φ _A and φ _B after starting to send C ₀ and C ₁ is counted, and when this count value reaches a value corresponding to the number of bits of the serial signal, the control signals C ₀ and C ₁ are ₀ = “0”,
C ₁ = “0” and each sub-device 30-1 to 30-8
Cancels parameter shift mode and returns to parameter hold mode. This results in
The parameter shift mode period of the sub devices 30-1 to 30-8 is set over eight periods of clock pulses φ _A and φ _B. In this way, the operation mode of the sub-devices 30-1 to 30-8 is set to the parameter shift mode over eight periods of the clock pulses φ _A and φ _B , and in synchronization with this, the operation mode of the eighth set of operator circuits is set to the parameter shift mode. 10
-8 is sent from the interface circuit 24 using an 8-bit serial signal, this display information is sent to the sub devices 30-1 to 30.
-8 is set to the parameter shift mode, the register circuit 301 of the first set of sub-devices 30-1 sequentially captures and stores the bits one by one. The display information stored in the register circuit 301 of the sub device 30-1 is transmitted to the seventh set of operator circuits 10.
-7 display information is interface circuit 2
By being sent from 4, the second
The data is transferred to and stored in the register circuit 301 of the sub-device 30-2 of the set. Then, when the display information for the first set of operator circuits 10-1 is sent out from the interface circuit 24, it is transferred to and stored in the eighth set of sub-devices 30-8. In this way, eight sets of display information are displayed on the sub device 30.
When the process of transferring from -1 to 30-8 is completed,
The central processing unit 20 has sub-devices 30-1 to 30
Control information for setting the operation mode of -8 to parameter load mode is given to the interface circuit 24, and from this circuit 24 C ₀ = “1”, C ₁ = “1”
The operation mode control signal is sent. Decoder 30 of each sub-device 30-1 to 30-8
When operation mode control signals C ₀ and C 1 with C ₀ = “1” and C ₁ = “1 _” are supplied, these signals C ₀ and C ₁
It outputs a mode setting signal LOD for setting the operating mode of its own sub-device to the parameter load mode, and provides this signal LOD to the clutch circuit 302 as a latch control signal. When the latch circuit 302 is supplied with the latch control signal, the latch circuit 302 clocks each bit signal of the display information stored in the register circuit 301 with a clock pulse φ _A ,
It is configured to capture and store data in parallel based on φ _B. Therefore, the mode setting signal from the decoder 300
When the LOD is output, the display information stored in the register circuit 301 is transferred and stored in the latch circuit 302. Display information stored in latch circuit 302 is provided to gate circuit 304. The gate circuit 304 includes 8-bit signal gates, which are in an open state in other operating modes except the parameter read mode. Therefore, the latch circuit 302
When display information is stored in , this display information is supplied to the parallel signal input/output terminal PI/O via the gate circuit 304, and further to this terminal PI/O.
The respective corresponding sets of operator circuits 10
-1 to 10 to 8 are supplied. Thereby, the display information sent from the main device 2 is displayed by lighting the light emitting diodes in the operator circuits 10-1 to 10-8. For example, if each bit of the display information for the eighth set of operator circuits 10-8 is "01000000", the light emitting diode 129 lights up, indicating that the vibrato effect has been selected according to the preset information. Note that for an operator circuit consisting only of switches, such as the operator circuit 10-1, information in which all bits are "0" is transferred. In this way, the operator circuits 10-1 to 10 −
When the display information transfer process for 8 is completed,
The central processing unit 20 has sub-devices 30-1 to 30
-8 operation mode is returned from parameter load mode to parameter hold mode. Next, the central processing unit 20 performs step 21.
2, the third buffer memory area DBUF3
A process is executed to transfer the preset information stored in the tone forming section (connected to the address bus A.BUS and the data bus D.BUS).
As a result, the musical tone forming section becomes able to form a musical tone with a timbre corresponding to the preset information transferred at this time. After this, the central processing unit 20 performs step 2.
At step 13, the parameter information set in the operator circuit group 1 is read and stored in the first buffer memory area DBUF1 of the working memory 22. That is, the central processing unit 20 is
Control information for setting the operation mode of 0-1 to 30-8 to parameter reading mode is supplied to the interface circuit 24 through the data bus D.BUS, and from this circuit 24 C ₀ = “0”, C ₁ =
The operation mode control signals C ₀ and C ₁ of “1” are sent out. Then, the decoder 300 of each sub-device 30-1 to 30-8 decodes the operation mode control signal of C ₀ = “0” and C ₁ = “1”, and changes the operation mode of its own sub-device to the parameter reading mode. Outputs a mode setting signal GET for setting, gives this signal GET to the register circuit 301, and
The signal is inverted by an inverter 303 and provided as a gate control signal to a gate circuit 304. The register 301 is configured to take in and store in parallel the 8-bit signal applied to the parallel input/output terminal P/IO as a set of parameter information when the mode setting signal GET is applied. On the other hand, the gate circuit 304 equipped with an 8-bit signal gate becomes closed when the decode signal GET of "1" is applied.
The signal feedback loop from the latch circuit 302 to the parallel input terminal of the register circuit 301 is cut off,
The resistor circuit 301 is configured to apply the output signal of the corresponding set of operator circuits to the parallel input terminal of the register circuit 301 via the parallel input/output terminal PI/O. Therefore, when the mode setting signal GET of "1" is output from the decoder 30, the register circuit 3
01 has a corresponding set of operator circuits 10-
Output signals 1 to 10-8 are respectively read and stored in parallel. That is, each sub-device 3
The register circuits 301 of 0-1 to 30-8 have corresponding sets of operator circuits 10-1 to 10-.
The parameter information set in step 8 is respectively read and stored. For example, when the switch 101 is turned on in the operator circuit 10-1, the sub device 3
Parameter information of "01111111" is stored in the register circuit 301 at 0-1.
Note that in the parameter information stored in each register circuit 301 of the sub-devices 30-1 to 30-8, the signal at the bit position to which the light emitting diode is connected is always "1". In this way, the operator circuits 10-1 to 10-
The parameter information set in step 8 is taken into the sub-devices 30-1 to 30-8. After this, the central processing unit 20
In order to read the parameter information stored in 0-1 to 30-8 into the main device 2, the sub device 30-
Set the operation modes 1 to 30-8 to parameter shift mode. That is, the central processing unit 20 causes the interface circuit 24 to send out operation mode control signals C ₀ and C ₁ with C ₀ =“1” and C ₁ =“0”. As a result, each sub-device 30-1 to 30-8 is set to the parameter shift mode, and the parameter information stored in the internal register circuit 301 as a parallel 8-bit signal is transferred every time the clock pulses φ _A and φ _B occur. Serial signal output terminal S ₀
By sequentially shifting one bit in the direction of , the signal is converted into an 8-bit serial signal and sequentially sent out. In this case, the period of the parameter shift mode is set to eight periods of the clock pulses φ _A and φ _B as described above. Therefore, by the generation of the first operation mode control signals C ₀ and C ₁ with _{C 0 =} “1” and C 1 = “0”, the first
The parameter information stored in the sub-device 30-1 of the group is transferred to the sub-device 30-2 of the second group, and similarly the parameter information stored in the sub-device 30-2 of the second group is transferred to the sub-device 30-2 of the second group. Third set of sub-device 3
Transferred to 0-3. On the other hand, the parameter information stored in the sub-device 30-8 located at the end of the serial signal transmission loop is transmitted to the interface circuit 2 through the serial signal input terminal Si of the main device 2.
4, and sequentially stored one bit at a time in the internal data register of this circuit 24. In this way, first, the 8th set of operator circuits 1
When the reading of the parameter information set in 0-8 is completed for all bits, the central processing unit 20 transfers the parameter information read at this time from the internal data register of the interface circuit 24 to the first buffer memory area DBUF1. and memorize it. Thereafter, the central processing unit 20 executes such operations a number of times equal to the number of installed sub-devices 30-1 to 30-8. As a result, all the operator circuits 10-1 to 10
The parameter information set in -8 is read through the interface area circuit 24 and stored in the first buffer memory area DBUF1. In addition, all bits of parameter information read from a control circuit composed only of light emitting diodes, such as the control circuit 10-2, are always "1". When the parameter reading process in step 213 is completed, the central processing unit 20 compares the newly read parameter information this time with the parameter information read in the previous parameter reading process in the next step 214, and detects changes in the parameter information. Detect. That is, the parameter information stored in both the first buffer memory area DBUF1 and the second buffer memory area DBUF2 is compared, and the control circuits 10-1 to 10-8
Detect whether there is a change in the parameter setting state. As a result of this comparison process, if there is no change in the parameter setting state, the central processing unit 20 returns to the process of step 212 and executes the process of transferring the parameter information stored in the third buffer memory area DBUF3 to the tone forming section. After that, the processes of steps 213 and 214 are repeated. However, if there is a change in the parameter setting state, the central processing unit 20 moves to step 215 and detects whether or not there is a change in the setting state of the preset selection information. As a result, if there is a change in the setting state of the preset select information, it is further determined in the preset process of step 217 whether or not write command information is given by the switch 116, and if the switch 116 is off and the write command information is not given. If not (if the signal is "1"), preset information corresponding to the new preset select information is read from the preset memory 23 and transferred to the third buffer memory area DBUF3. but,
When the switch 116 is turned on, the parameter information stored in the third buffer memory area DBUF3 is stored in one of the memory areas PUEM(1) to PMEM(M) corresponding to the preset selection information. After this, the central processing unit 20 performs step 2.
Return to step 11. On the other hand, the central processing unit 20 performs step 21.
When a change in the parameter information other than the preset selection information is detected in step 5, the next step 216 compares the parameter information other than the preset selection information to check whether there is a musical matching relationship. As a result, if there is a combination of parameter information that is not in a musically consistent relationship, one of the parameter information is changed to parameter information that is in a consistent relationship and is stored in the third buffer memory area DBUF3. but,
If there is a musically consistent relationship, it is stored in the first buffer memory area DBLF3. However, if there is musical consistency, the parameter information newly stored in the first buffer memory area DBUF1 is transferred to the third buffer memory area DBUF3. When this is finished, the process returns to step 211 and the same process is repeated. As described above, the main device 2 and the operator circuit 10
-1 to 10-8, various parameter information is transferred. In addition, in the processing of step 214, when a change is detected, processing is also performed to transfer the contents of the first buffer memory area DBUF1 to the second buffer memory area DBUF2. Further, in the process of step 216, processes such as priority selection of parameter information and toggle operation of a switch are also performed as necessary. F. Configuration of Interface Circuit 24 FIG. 4 is a circuit diagram showing an example of a specific configuration of the interface circuit 24 in the main device 2. This interface circuit 24 has a 16-bit address bus A/BUS and an 8-bit data bus D/BUS.
It is coupled to the central processing unit 20 by a BUS and a read/write control signal line RWL. From the central processing unit 20 to the sub-devices 30-1 to 30-3
Display information for 0-8 and sub-devices 30-1~
Control information for setting the operating mode of 30-8 is transmitted to latch 240 via data bus D.BUS.
is memorized. The memory contents of this latch 240 are:
Interface internal output data bus OPD/BUS
The signal is supplied to a data register (D.REG) 241 having an 8-bit signal storage location and a latch 242 having a 2-bit signal storage location. The data register 241 is the sub-device 30-1 to 30-30.
The 8-bit configuration display information stored here is supplied to the parallel-to-serial converter (PSC) 243 and synchronized with the clock pulses φ _A and φ _B. After being sequentially converted into an 8-bit serial signal, it is sequentially output one bit at a time from the serial signal output terminal _S0 . On the other hand, the latch 242 stores the control information of the operation mode, and the 2-bit configuration control information stored here is used for the inverters 2440 and 244.
1, after being code-converted in the encoder 244 with AND gates 2442 to 2444 and OR gate 2445, the operating mode control signal C ₀ ,
It is sent out from the control signal output terminals TC ₀ and TC ₁ as C ₁ . On the other hand, parameter information input from the sub-devices 30-1 to 30-8 in the form of an 8-bit serial signal is supplied to the shift register (S/R) 245 via the serial signal input terminal Si, and clock pulse φ _A , φ _B are stored one bit at a time. The parameter information stored in shift register 245 is transferred to latch 246. In this case, the shift register 245 has only 7 bits of signal storage positions, and the 8th
Of the serial signals that are input in time series starting from the 8th bit, the 8th bit to the 2nd bit are stored in the shift register 245, and the 1st bit signal that is input last is determined by the input timing of the signal. The latch 246 is configured to be stored directly at the latch 246. As a result, a set of parameter information input as an 8-bit serial signal is converted into an 8-bit parallel signal and stored in the latch 246. The indirect parameter information thus stored in latch 246 is sent to data bus D.BUS of central processing unit 20 via 3-state buffer gates (3ST.BUF) 247 and 248. The input/output control of the information described above is performed based on the read/write control signal R/W and the interface control information IFCD supplied to the address bus A/BUS together with the device number information DND of the interface circuit 24 concerned. (Operation when transferring display information) First, the operation when transferring display information to the sub devices 30-1 to 30-8 will be described with reference to the flowchart shown in FIG. 5 and the time chart shown in FIG. I will explain. The central processing unit 20 has sub-devices 30-1 to 30
-8, as shown in step 3110 in FIG.
8 to set parameter shift mode.
Control information for B ₂ =1 and B ₁ =1 is provided to the input of latch 240 . In addition, this control information is
In order to store the data as 0, a read/write control signal R/W of "0" is sent. Further, the device number information DND of the interface circuit 24 is supplied to the decoder 249 via the upper bit signal line of the address bus A.
Interface control information IFCD is provided to latch 250 via the lower bit signal line of BUS. The decoder 249 receives input device number information.
It decodes whether or not DED matches a predetermined set value. If it matches the set value, it outputs an enable signal EN of "1". This enable signal EN is provided as a latch control signal for latch 250 and is also provided to one gate input of AND gate 251. On the other hand, the read/write control signal R/W of "0" is inverted by the inverter 252 and supplied to the other input of the AND gate 251, and the latch 240 is inverted on the condition that the enable signal EN of "1" is generated. latch control signal. Therefore, when the enable signal EN of "1" is generated from the decoder 249, the address bus A/BUS
The interface control information IFCD input via the lower bit signal line of the latch 250 is stored in the latch 250. Further, control information on the operating mode input via the data bus D.BUS is stored in latch 240. The interface control information IFCD stored in the latch 250 is a read/write control signal R/
The signal DL/R/W, which is obtained by delaying W by a predetermined time by the delay circuit 254, is read into the decoder 253. Decoder 253 is interface control information
It decodes the IFCD and outputs various control signals for the data register 241 and the like. In this embodiment, (a) display information transfer command information for the sub-devices 30-1 to 30-8, and (b) sub-devices 30-1 to 30-8.
30-8 read command information, (c) write command information for storing operation mode control information in latch 242, (d) sub-device 30-
Four types of interface control information IFCD are supplied from the central processing unit 20: reply command information for feeding back to the central processing unit 20 the information transfer status information between the central processing unit 1 to 30-8. When the decoder 253 is supplied with such interface control information IFCD, it sends a transfer command signal 3W for the information in (a) above, and a read command signal 3R for the information in (b) above. , a write command signal 2W is output for the information in (c) above, and a reply command signal IR is output for the information in (d) above. When setting the sub devices 30-1 to 30-8 to the parameter shift mode, the above write command information (c) is supplied to the decoder 253 as the interface control information IFCD. This causes the mode control information write command signal to be sent from the decoder 253.
2W is output (see Figure 6c). This write command signal 2W is supplied to latch 242 as a latch control signal. At this time, the input of the latch 242 is the signal line of the lower 2 bits of the interface internal output data bus OPD/BUS.
Control information for setting the sub-devices 30-1 to 30-8 to the parameter shift mode is supplied via D ₁ and D ₂ . As a result, latch 242 stores control information for setting sub-devices 30-1 to 30-8 to the parameter shift mode. The control information for setting the operation mode of the sub-devices 30-1 to 30-8 consists of 2-bit signals _B2 and _B1 ,
The relationship between the signals B ₂ and B ₁ and the operation mode is determined as shown in Table 2 below.
When setting 1 to 30-8 to parameter shift mode, B ₂ = “1” as shown in Figure 6 d and e.
Control information of B ₁ =“1” is stored.

[Table] The control information consisting of the 2-bit signals B ₂ and B ₁ is supplied to the encoder 244, where it is subjected to timing control by a transfer control circuit 255 and a timing control circuit 256, which will be described later, so that C ₀ =
After being converted into operation mode control signals C ₀ and C ₁ with C ₁ = “0” and C 1 = “1”, they are sent to the sub devices 30-1 to 30-8 over eight cycles of clock signals φ _A and φ _B. Ru. After the central processing unit 20 supplies the operation mode control information to the interface circuit 24 as described above, as shown in step 2111 in FIG. set,
In the next step 2112, display information is read from the address position of the third buffer memory DBUF3 corresponding to the contents of the address pointer ADRP and set in the accumulator ACC. After this, the display information set in the accumulator ACC is latched to the latch 240 via the data bus D/BUS.
supply to. At the same time, along with the device number information DED of the interface circuit 24, display information transfer command information is supplied to the latch 250 as interface control information IFCD. These display information and transfer command information are stored in latches 240 and 250 in the same manner as the operation mode control information writing operation described above. Further, the transfer command information stored in latch 250 is similarly read into decoder 253. As a result, the display information transfer command signal 3W is output from the decoder 253 (see FIG. 6f). This transfer command signal 3W is sent to the data register 241
is supplied as a data write control signal to NOR gate 2550 and AND gate 255.
1, OR gate 2552, delay flip-flops 2553 and 2554, AND gate 255
5. The signal is supplied to a transfer control circuit 255 composed of a differentiation circuit 2556. As a result, the display information stored in the latch 240 is transferred to the interface internal output data bus OPD.
The data is transferred to the data register 241 via the BUS and stored. Figure 6g shows data register 241.
It shows how the memory contents of . On the other hand, a count start signal ST for timing control 256 is output from transfer control circuit 255 . That is, the transfer command signal 3W (“1” signal) output from the decoder 253 is supplied to the delay flip-flop 2553 via the OR gate 2552 in the transfer control circuit 255. The delay flip-flop 2553 is connected to the central processing unit 2.
A clock signal φ ₁ , which is synchronized with the clock signal 0 and has a much higher frequency than the clock signals φ _A and φ _B.
Based on _φ2 , the input signal is read at the rising timing of the clock signal _φ1 , and then outputted at the rising timing of the clock signal _φ2 . Therefore, when the transfer command signal 3W is input to the delay flip-flop 2553 via the OR gate 2552, the command signal 3W is delayed by a time corresponding to one period of the clock signal _{φ1 and} output. This delayed command signal 3W' is then passed through an AND gate 2551 to an OR gate 255.
Feedback is provided to the second input. This results in
The transfer command signal 3W is an AND gate 2551, an OR gate 2552, and a delay flip-flop 2553.
The signal is held in a signal holding loop consisting of: In this case, the output signal of the NOR gate 2550 is supplied to one gate input of the AND gate 2551. Timing control circuit 256
The configuration is such that the signal becomes "0" only when the transfer period end signal CT7 is generated, and the signal holding loop from the AND gate 2551 to the OR gate 2552 is released. Therefore, at the beginning of the transfer command signal 3W, the Noah gate 255
The output signal of 0 is "1". The transfer command signal 3W held by the circuit section consisting of AND gate 2551, OR gate 2552 and delay flip-flop 2553 is supplied to delay flip-flop 2554 at the next stage. The delay flip-flop 2554 reads an input signal at the rising timing of the clock signal φ _A and then outputs it at the rising timing of the clock signal φ _B.
When the output signal of the delay flip-flop 2553 in the previous stage is supplied, this signal is delayed by a time equivalent to one period of the clock pulse φ _A (or φ _B ) and output. This delay flip-flop 2554
The output signal of is shown in FIG. 6h as signal name Q1. Note that the delay operation by the delay flip-flop 2554 has no meaning in the delay itself; rather, the signal (3W) read into the flip-flop 2553 in the previous stage in synchronization with the clock signal of the central processing unit 20 is sent to the sub-device group 3. It is meaningful that it is read in synchronization with the clock signals φ _A and φ _B used. The output signal Q1 of this delay flip-flop 2554 is supplied to a differentiating circuit 2556. The differentiation circuit 2556 is based on the clock signals φ _A and φ _B , and outputs a differentiated signal that is synchronized with the rising edge (“0” → “1”) timing of the input signal and has a time width equal to one period of the clock signal φ _B. When the output signal Q1 of the delay flip-flop 2554 changes from "0" to "1", a differential signal ST synchronized with this change timing is output as shown in FIG. 6i. This differential signal ST is an OR gate 2560,
It is supplied as a count start signal to a timing control circuit 256 composed of a delay flip-flop 2561, a 3-bit binary counter 2562, an inverter 2563, a decoder 2564, an inverter 2565 and an AND gate 2566. Furthermore, the PSC 243 is used as a gate timing signal for the gate inputs of AND gates 2442 and 2444 in the encoder 244.
are respectively supplied as data write control signals. When the timing control circuit 256 receives the count start signal ST, the timing control circuit 256 starts the binary counter 25.
The "1" signal applied to the trigger input T of 62 starts counting sequentially in synchronization with the clock signals φ _A and φ _B , and when the count value reaches from "0" to "7", the count value consisting of 8 bits is counted. A transfer period end signal CT7 for one set of transfer information is output. That is, the count start signal ST is input to the delay flip-flop 2561 via the OR gate 2560, and is delayed by a time corresponding to the first anniversary of the clock signal φ _B in the flip-flop 2561. The data is maintained by being fed back to the input side. The count start signal ST held in this manner is inverted by an inverter 2563 and supplied to the reset R of the binary counter 2562. As a result, the binary counter 2562 is released from the reset state and starts sequentially counting the "1" signal applied to the trigger input T based on the clock pulses φ _A and φ _B. The 3-bit output signals Q ₁ , Q ₂ , Q ₃ of this binary counter 2562 are sequentially decoded by a decoder 2564.
When the count value N of the binary counter 2562 reaches "7" as shown in FIG. 6P, it is output as the decode signal CT7 (see FIG. 6Q).
That is, as shown in FIG. 6o, when eight cycles of the clock pulse φ _B have elapsed since the output signal Q2 of the delay flip-flop 2561 became "1",
The decoder 2564 outputs a decoded signal with a count value of "7". This decode signal CT7 is 8
It is sent as a transfer period end signal for a set of transfer information consisting of bits. The transfer period end signal CT7 is sent to the transfer control circuit 255.
The signal is supplied as a reset signal to AND gate 2555, and is also inverted by inverter 2565 and supplied to AND gate 2566. As a result, the AND gate 2566 and the OR gate 25 in the timing control circuit 256
The signal holding loop of delay flip-flop 2561 formed by 60 is released. As a result, the output signal Q2 of the delay flip-flop 2561 changes to a "1" signal as shown in _FIG .
signal, and along with this, the binary counter 25
62 also returns to the reset state. On the other hand, during the period when the output signal Q2 of the delay flip-flop 2561 is a "1" signal,
The PSC 243 converts a set of display information consisting of 8 bits into a serial signal and outputs it one bit at a time, and the encoder 244 converts the operation mode control information (B ₂ = “1”,
B ₁ = “1”) is converted and output. That is, the differential signal ST output from the transfer control circuit 255 is applied to the PSC 243 as a data write control signal. As a result, the PSC 243 captures and stores each bit signal of a set of display information stored in the data register (D/REG) 241 in parallel, and then converts it into a serial signal based on the clock signals φ _A and φ _B. Then, it sequentially outputs one bit at a time starting from the most significant bit (B8). The serial signal output in this manner is shown in FIG. 6j with the signal name SD. Furthermore, in the encoder 244, the differential signal ST output from the transfer control circuit 255 is applied to AND gates 2442 and 2444 as a gate timing signal, and the delay flip-flop 2561 in the timing control circuit 256
The output signal Q2 of is applied as the gate timing signal of the AND gate 2443. The AND gate 2442 has three gate inputs, and each gate input receives the 2-bit output signals B ₂ and B ₁ output from the latch 242 to the inverter 24.
Signals inverted by 40 and 2441 respectively
B ₂ , ₁ and signal ST are input, and signals B ₁ and
“1” synchronized with signal ST when both B ₂ are “0”
configured to output a signal. Also, the AND gate 2443 has two gate inputs,
The output signal _B2 of the latch 242 and the output signal Q2 of the delay flip-flop 2561 are input to each gate input, and the output signal _B2 of the latch 242 is "1".
It is configured to output a "1" signal synchronized with the output signal Q2 of the delay flip-flop 2561 at the time of the delay flip-flop 2561. Furthermore, and gate 2444
has two gate inputs, and each gate input connects the output signal _B1 of latch 242 to inverter 2440.
The signal ₁ inverted by the transfer control circuit 25
The latch 242 is configured to receive a signal ST outputted from the latch 242 and output a "1" signal synchronized with the signal ST when the output signal _B1 of the latch 242 is "0". Output signals of AND gates 2442 and 2443 among AND gates 2442 to 2444 are outputted as operation mode control signal C ₀ of sub-device group 3 via OR gate 2445.
The output signals of are configured to be sent out as operation mode control signals _C1 , respectively. Therefore, when transferring display information to the sub devices 30-1 to 30-8, the output signal B ₂ of the latch 242,
Since both _B1 are "1", the theoretical condition of AND gate 2443 only holds true while output signal Q2 of delay flip-flop 2561 is "1". As a result, while the output signal Q2 of the delay flip-flop 2561 is "1", the AND gate 2443 outputs C ₀ =
An operation mode control signal C ₀ of “1” is sent out. That is, after the output signal Q2 of the delay flip-flop 2561 becomes "1", the clock signal _φB becomes
Until the cycle period elapses, the echoer 244 outputs an operation mode control signal of C ₀ = “1” and C ₁ = “0”.
C ₀ and C ₁ are sent. FIG. 6k shows the output signal of the AND gate 2442 with the signal name ECA, FIG. 6l shows the output signal of the AND gate 2443 with the signal name ECB, and FIG.
and n indicate operation mode control signals C ₀ and C ₁ , respectively. By sending out the operation mode control signals C ₀ and C 1 with C ₀ = “1” and C ₁ = “ ₀ ” in this way,
The sub-devices 30-1 to 30-8 receive clock pulses φ _B
The parameter shift mode is set for a period of . During this parameter shift mode period, the serial signals SD sequentially sent out from the PSC 243 are first stored in the register circuit 301 of the sub-device 30-1. Output signal Q2 of delay flip-flop 2561
When eight cycles of the clock signal φ _B have elapsed since the clock signal φ B became "1", the timing control circuit 256 outputs the transfer period end signal CT7 as described above. This signal CT7 is supplied to the NOR gate 2550 via the AND gate 2555 of the transfer control circuit 255. By this, AND gate 2551
The signal holding loop of delay flip-flop 2553 formed by OR gate 2552 is released. As a result, delay flip-flop 2553
The output signals of 2554 and 2554 both become "0" signals, and the interface circuit 24 returns to its initial state. The display information for the eight sets of sub-devices 30-1 to 30-8 is stored in the register circuit 301 of each sub-device 30-1 to 30-8 by performing the above operations a total of eight times. In this case, the central processing unit 20 uses the decoder 2
After generating a transfer command signal 3W from 53, an operation to detect whether the transfer operation of one set of transfer information (display information) has been completed is executed at a predetermined cycle, and on the condition that the transfer operation is completed, the next The transfer operation of the set of transfer information is performed. For this purpose, the transfer control circuit 255
Delay flip-flops 2553 and 25
The output signal of 54 is output to the OR gate 257 and the 3-state buffer gate 25 by the return command signal 1R (“1” signal) being output from the decoder 253.
Interface internal input data bus via 8
After being sent to the most significant bit line _D8 of the IPD/BUS, a read/write control signal R/W of "1" is output from the central processing unit 20, thereby causing the 3-state buffer gate 248 and the data bus D - It is read into the central processing unit 20 via the BUS, and is configured to be able to detect whether or not the transfer operation of all bits of one set of display information has been completed. That is, the output signals of the delay flip-flops 2553 and 2554 are "1" signals after the transfer command signal 3W is output from the decoder 253 until the transfer of all bits of one set of display information is completed. Therefore, by knowing whether the OR signal obtained from the OR gate 257 is "1" or "0", it is possible to determine whether or not the transfer operation of one set of display information in the interface circuit 24 has been completed. The state can be detected. Therefore, the central processing unit 20 generates the transfer command signal 3W in step 2113 of FIG. r) is read into the accumulator ACC as transfer status information,
In the next step 2115, it is determined whether this transfer status information (STD) is "0" or "1", and if it is "1", the read operation of the information (STD) is executed again and it becomes "0". The processing of the subsequent steps is executed on the condition that this is the case. That is, the central processing unit 20 stores a set of display information in the data register 241, and then stores the transfer status information (STD) of the interface circuit 24.
A reply command signal from the decoder 253 for reading the
1R and sends out a read/write control signal R/W of "1". This reply command signal 1R
is provided as a gate enable signal for three-state buffer gate 258. As a result, the output signal STD of the OR gate 257 is sent via the buffer gate 258 to the most significant bit line _D8 of the interface internal input data bus IPD/BUS. On the other hand, the read/write control signal R/W of “1” is supplied to the AND gate 259. The other input of this AND gate 259 is supplied with an enable signal of "1" from the decoder 249. Therefore, the read/write control signal R/W of "1" passes through the AND gate 259 and is supplied to the delay circuit 260, where it is delayed by a predetermined time and then supplied as a gate enable signal to the 3-state buffer gate 248. be done. As a result, the transfer status information (STD) being sent to the top pit line D ₈ of the interface internal input data bus IPD/BUS is read into the central processing unit 20 via the 3-stage buffer gate 248. . As a result, the central processing unit 20 determines that if the transfer status information (STD) read at this time is "1", the interface circuit 24 is in the process of transferring display information; It is possible to detect that the operation is completed and the state is in the initial state. As a result of such detection processing, if the transfer status information (STD) is "1",
Repeat the same process. Therefore, the decoder 253 repeatedly outputs the reply command signal 1R as shown in FIG. 6s. However, if the transfer status information (STD) is "0", the central processing unit 20 transfers all the sub-devices 30-1 to 30- in step 2116 of FIG.
It is determined whether the information transfer to 8 has been completed, and if it has not been completed, the content of the address pointer ADRP is updated by "+1" in step 2117, and then the transfer processing operations from step 2112 onward are performed as described above. . And eight sets of sub-devices 30-
When the information transfer to 1 to 30-8 is completed, the display information stored in the register circuit 301 in each sub-device is stored in the latch 302.
As shown in step 2118 of the figure, the sub-device 30-
After transferring the control information (B ₂ = "0", B ₁ = "0") for setting parameters 1 to 30-8 to the parameter load mode to the latch 242 and storing it, a transfer command is issued in the next step 2119. Interface control information IFCD for generating the signal 3W is stored in latch 250. This causes the transfer command signal to be sent from the decoder 253.
3W occurs. Then, the differential signal ST is sent from the transfer control circuit 255.
occurs, and the timing control circuit 256 starts counting, and the logic conditions of the AND gates 2442 and 2444 in the encoder 244 are satisfied, and the operation mode control signal C of C ₀ = “1” and C ₁ = “1” is generated. ₀ and _C1 are sent. In this case, AND gates 2442 and 244
Logic condition 4 is satisfied only while the differential signal ST is "1". Therefore, the operation mode control signals C ₀ and C ₁ output from the encoder 244 are as shown in FIG.
As shown in , it has the same time width as the differential signal ST. When the operation mode control signals C ₀ and C 1 with C ₀ = “1” and C ₁ = “ ₁ ” are output in this way, the sub device 3
0-1 to 30-8 are set to parameter load mode. As a result, each sub-device 30-1 to 30-30
After the display information stored in the register circuit 301 of -8 is transferred to the latch circuit 302 and stored,
The signals are transferred via the gate circuit 304 to the respective corresponding sets of operator circuits 10-1 to 10-8. The transfer control circuit 255 and the timing control circuit 256 are returned to their initial states by the transfer period end signal CT7 generated when the count value of the binary counter 2562 reaches "7". The above is an explanation of the operation when transferring display information. (Operation when reading parameter information) Next, FIG. This will be explained with reference to the flowchart shown in FIG. 8 and the time chart shown in FIG. The central processing unit 20 includes operator circuits 10-1 to 10-1.
When reading the parameter information set in step 10-8, as shown in step 2130 in FIG. 7, first read the control information (B ₂ = “1”,
B ₁ =“0”) is stored in the latch 242 of the interface circuit 24. Thereafter, by generating a reply command signal 1R from the decoder 253, the transfer status information (STD) of the interface circuit 24 is read into the accumulator ACC as shown in step 2131 in FIG.
In 2, this information (STD) is “1” or “0”
It is determined whether or not information can be transferred between the sub-devices 30-1 to 30-8. As a result, if the state is such that information transfer cannot be performed (that is, if STD is "1"), steps 2131 and 21 are performed until the state becomes possible (that is, until STD becomes "0").
32 is repeatedly executed. When the information transfer becomes possible, the latch 250 stores the interface control information IFCD for generating the transfer command signal 3W in the next step 2133. As a result, a transfer command signal 3W is generated from the decoder 253 (see FIG. 8f). As a result, the differential signal ST is generated from the transfer control circuit 255 at the timing shown in FIG.
AND gate 2444 in encoder 244
The logical conditions are satisfied, and the operation mode control signals C _{0 and C 1 of C 0} = “0” and C ₁ = “1” are activated only while the signal S is “1” as shown in FIG. ₈ j and _k . Sent out. Then, in the sub devices 30-1 to 30-8, a mode setting signal GET is generated from the decoder 300, and the operation mode is set to the parameter reading mode. As a result, each operator circuit 10-1~
The parameter information set in step 10-8 is stored in the register circuits 301 of the corresponding sets of sub-devices 30-1 to 30-8. After this, when the differential signal ST becomes "0", the output signal of the AND gate 2444 also becomes "0", and the parameter load mode of the sub devices 30-1 to 30-8 is canceled. However, at the same time that the differential signal ST becomes "0", the output signal Q2 of the delay flip-flop 2561 in the timing control circuit 256 becomes "1" (see FIG. 8l), the binary counter 2562 starts counting, and the encoder 244 The logic condition of the AND gate 2443 is satisfied, and the operation mode control signals C ₀ and C 1 with C ₀ =“1” and C ₁ =“ ₀ ” are transmitted.
That is, operation mode control signals C ₀ and C ₁ for setting the sub-devices 30-1 to 30-8 to the parameter shift mode are sent out. As a result, the sub devices 30-1 to 30-8 are set to the parameter shift mode. On the other hand, the count value N of the binary counter 2562 is determined by the clock pulse φ _A , as shown in FIG.
It is updated sequentially every time φ _B occurs, and when this count value N reaches "7", the transfer period end signal CT7 is generated from the decoder 2564 (see FIG. 8n).
The output signal Q2 of the delay flip-flop 2561 becomes a "0" signal, and the timing control circuit 256 returns to its initial state. At the same time, the transfer control circuit 25
5 also returns to its initial state. When the timing control circuit 256 returns to the initial state, AND gate 2 in the encoder 244
The logical condition of 443 is not satisfied. As a result, C ₀ = “1”, which was output from the encoder 244,
Operation mode control signal C ₀ when C ₁ = “0”, C ₁ is C ₀ =
“0”, C ₁ = “0”, and the sub devices 30-1 to 30
-8 parameter shift mode is canceled. That is, by generating the transfer command signal 3W from the decoder 253 through the process of step 2133 in FIG _. After being set to the parameter read mode for one cycle period of _φB , the parameter shift mode is set for eight cycles of the clock signal φB. As a result, the parameter information stored in the register circuits 301 of the sub devices 30-1 to 30-8 is
During the parameter shift mode, the bits are sequentially shifted toward the serial signal output terminal _S0 and sent out one bit at a time. The parameter information sequentially sent from the sub-device 30-8 located at the end of the serial transmission loop is sent to the interface circuit 24.
After being sequentially read into the shift register 245, the latch 246 is activated by the transfer period end signal CT7.
is memorized. In this way, first, the operator circuit 1 of the 8th set
The parameter information set in 0-8 is latched 24
6 is stored. On the other hand, while the interface circuit 24 is performing the above-described transfer operation, the central processing unit 20 sends the reply command signal 1R to the decoder 25.
3 (see FIG. 8q), and reads the transfer status information (STD) of the interface circuit 24 as shown in steps 2134 and 2135 in FIG. ”, and performs a detection process to determine whether reading the next set of parameter information is possible. As a result of this detection process, the transfer status information (STD)
When becomes “0”, the central processing unit 20 starts reading the next set of parameter information.
As shown in step 2136 of the figure, first B ₂ =
The control information of “1” and B ₁ =“1” is transferred to the latch 242 and stored. After this, the next step 213
After the start address information of the first buffer memory area DBUF1 is set in the address pointer ADRP in step 7, the read command signal 3R is generated from the decoder 253 in the next step 2138 (see FIG. 8f). Furthermore, a read/write control signal R/W of "1" is sent out. When the read command signal 3R is generated from the decoder 253, the set of parameter information stored in the latch 246 is inputted to the 3-state buffer gate 248 via the 3-state buffer gate 247, and further the read/write control of "1" is performed. Signal R/W
is read into the central processing unit 20 via the three-state buffer gate 248. On the other hand, in response to the generation of the read command signal 3R, the transfer control circuit 255 outputs the differential signal ST.
Therefore, the output signal Q2 of the delay flip-flop 2561 in the timing control circuit 256 becomes "1", and the counting operation of the binary counter 2562 is started. Furthermore, since the output signal Q2 of the delay flip-flop 2561 becomes "1", the logic condition of the AND gate 2443 in the encoder 244 is satisfied, and C ₀ = "1", C ₁ =
Operation mode control signals C ₀ and C ₁ of “0” are now sent. The operation mode control signals C ₀ and C 1 with C ₀ = “1” and C ₁ = “0” generate a transfer period end signal CT7 from the decoder 2564, and the output signal Q2 of the delay flip-flop 2561 becomes “0” _. will be output continuously until As a result, the operation mode of the sub-devices 30-1 to 30-8 is set to the parameter shift mode for eight cycles of the clock signal _φB , and this time the operation mode is set by the seventh set of operator circuits 10-7. The parameter information is transmitted to the latch 24 via the shift register 245.
6 is stored. Parameter information input to the shift register 245 in the form of an 8-bit serial signal is indicated by the signal name RD in FIG. While the parameter information from the sub-device 30-7 is being sequentially input, the central processing unit 20
reads the transfer status information (STD) of the interface circuit 24 as shown in steps 2139 and 2140 in FIG. There is. As a result, if the transfer status information (STD) becomes "0" and it becomes possible to read the next set of parameter information, then in step 2141, on the condition that the read operation of all sets has been completed, In step 2142, the address pointer
After updating the contents of ADRP by "+1", the processing from step 2138 onwards is performed in the same manner. As a result, eight sets of operator circuits 10-1 to 10
The reading operation of the parameter information set in -8 is all completed. Note that when reading the parameter information set in the operator circuits 10-1 to 10-8, when the differential signal ST is generated from the transfer control circuit 255,
After reading the stored contents of the data register 241, the PSC 243 sequentially converts them into serial signals and sends them out from the serial signal output terminal _S0 . information that is unrelated to the regular display information is stored in the , but this information is not included in the mode setting signal.
Since LOD is not generated, it is not transferred to latch circuit 302. Therefore, the regular display information stored in the latch circuit 302 is held without being affected in any way. G. Specific configuration of sub-devices FIG. 9 is a circuit diagram showing an example of a specific configuration of the sub-devices 30-1 to 30-8. Here, a register circuit 301, a latch circuit 302, a gate circuit 30
Among the circuit portions 30B ₁ to 30B ₈ corresponding to the first bit B ₁ to the eighth bit B ₈ in 4, only the circuit portion corresponding to the first bit B ₁ is shown as a representative. In FIG. 9, the circuit portion corresponding to the first bit _B1 in register circuit 301 is composed of AND gates 301-3012, OR gate 3013, and delay flip-flop 3014. Further, the circuit portion corresponding to the first bit _B1 in the latch circuit 302 is connected to the inverter 30.
20, AND gates 3021 and 3022, OR gate 3023 and delay flip-flop 3
024, and further includes a gate circuit 304.
The circuit portion corresponding to the first bit _B1 in is constituted by a gate 3040. In such a configuration, an 8-bit serial signal constituting display information from the serial signal input terminal Si is supplied to the AND gate 3010. This AND gate 3010 has a mode setting signal output from the decoder 300 to the other gate input.
SFT is supplied, and its output signal is passed through an off-gate 3013 to a delayed flip-flop 301.
4. Further, the delay flip-flop 3014 delays the input signal by a time equivalent to one period of the clock signal φ _B and supplies it to the AND gate 3010 of the second bit circuit section, and also supplies it to the AND gate 3012, so that the mode setting signal HLD is It is configured to hold the input signal by feeding it back to its own input side via the AND gate 3012 and the OR gate 3013 on the condition that the signal is generated. As mentioned above, the mode setting signal SFT becomes "1" for 8 periods of the clock signal φ _B in response to a set of serial signals having an 8-bit configuration, and the mode setting signal SFT becomes "1" for 8 periods of the clock signal φB, and the sub-devices 30-1 to 30-8 are controlled by the clock signal. This is a signal that sets the parameter shift mode for eight periods of φ _B. Therefore, when an 8-bit serial signal is transferred from the interface circuit 24 in synchronization with such a mode setting signal SFT, each bit signal of this serial signal is first passed through the AND gate in the circuit section of the first bit. 3010 and delay flip-flop 3014 via OR gate 3013.
The signals are sequentially inputted to the gates, and then sequentially transferred to the AND gate 3010 of the second bit circuit portion via the delay flip-flop 3014. Such an operation is similarly performed in the circuit portions of the second bit to the eighth bit. As a result, when a time period equivalent to 8 cycles of the clock signal φ _B has elapsed after the first bit signal of the serial signal is input, each bit signal of the serial signal is read into the delay flip-flop 3014 of the corresponding circuit section, and is input to the signal SFT. Signal instead
HLD is generated from decoder 300 and is held by a signal holding loop of AND gate 3012, OR gate 3013, and delay flip prop 3014. 8 transferred from the interface circuit 24
The bit-structured serial signal is held in the register circuit 301 as described above. The display information stored in the register circuit 301 is
The mode setting signal LOD is generated from the decoder 300 and stored in the latch circuit 302.
That is, the delay flip-flop 3014 of the circuit portion of the first bit in the register circuit 301
The output signal is supplied to the AND gate 3021 of the first bit circuit portion of the latch circuit 302. The AND gate 3021 has a mode setting signal LOD input to the other gate input for setting the sub-device to parameter load mode.
The output signal is configured to be supplied to a delay flip-flop 3024 via an OR gate 3023. Also, delay flip-flop 302
4 delays the input signal from the OR gate 3023 by a time equivalent to one period of the clock signal φ _B and supplies it to the gate 3040;
22 and an OR gate 3023 to hold the input signal by feeding it back to its own input side. In this case, the other input of the AND gate 3022 is supplied with a signal obtained by inverting the mode setting signal LOD by the inverter 3020, and the signal holding loop of the delay flip-flop 3024 is connected to the mode setting signal LOD.
It is formed only when the LOD is "0", that is, when the parameter load mode is released. Therefore, the mode setting signal from the decoder 300
When the LOD occurs, the output signal of the delay flip-flop in the register circuit 301 is read into the delay flip-flop 3024 via the AND gate 3021 and the OR gate 3023, and then the AND gate formed by the signal LOD becoming "0" is read. 3022 and orgate 3023
is held in delay flip-flop 3024 by a signal holding loop. The display information stored in the latch circuit 302 in this way is transmitted by the mode setting signal from the decoder 300.
Gate 3040 and parallel signal output terminal PI/O on the condition that GET is not generated.
The signal is sent to the control circuit 10-x via the control circuit 10-x. On the other hand, the parameter information set in the operator circuit 10-x is transmitted through the mode setting signal from the decoder 300.
When GET occurs, the register circuit 301
is read and stored. That is, when the mode setting signal GET of "1" is generated from the decoder 300, the gate 3040 is closed, and the parallel signal input/output terminal PI/O
The operator output signal (i.e., parameter information) of the operator circuit 10-x is applied to. This operator output signal is supplied to an AND gate 3011 in the register circuit 301, and is read into a delay flip-flop 3014 via this AND gate 3011 and an OR gate 3013 on the condition that a mode setting signal GET of "1" is generated. It can be done. After this, the signal is replaced with the mode setting signal GET.
The signal is held by a signal holding loop of AND gate 3012, OR gate 3013, and delay flip-flop 3014 formed by generation of HLD, and further transferred to main device 2 by generation of mode setting signal SFT. H. Other embodiments of the sub-device FIG. 10 is a block diagram showing another embodiment of the sub-device. The sub-device 30-10 of this embodiment is as disclosed in Japanese Patent Application Laid-Open No. 57-95604,
It controls the operator device 10-10, which can control the operator's position not only manually but also by an electric mechanism, and reads setting information. Therefore, when using such a sub-device 30-10 and an operator device 10-10, position control information for controlling the operator position by an electric mechanism is sent from the main device 2; The operator position information read by the operator's position sensor is transferred to the device 2. The position control information and the operator position information are composed of, for example, 8-bit signals, and the latter operator position information is used as parameter information for controlling, for example, the volume of musical tones. The former position control information is determined in correspondence with parameter information for controlling musical tone volume, etc., and is stored in the preset memory 23 of the main device 2 in advance. In FIG. 10, the sub-device 30 shown in FIG.
-1 to 30-8 is that the controller device 1 is used as a parallel signal input to the register circuit 301.
The output information of the operator position sensor 151 at 0-10, that is, the operator position information, is applied, and a comparison circuit 305 and a motor control circuit 306 are provided in place of the gate circuit 304. The electric mechanism 152 is driven and the position of the operator 150 can be controlled from the main control device. In such a configuration, when a mode setting signal GET is generated from the decoder 300 to set the sub-device 10-10 to the parameter reading mode,
Position information of the operator 150 output from the position sensor 151 is read into the register circuit 301. Then, instead of the signal GET, a mode setting signal HLD is generated from the decoder 300 and stored in the register circuit 301. Thereafter, when the mode setting signal SFT for setting the sub-device 10-10 to the parameter shift mode is generated from the decoder 300, the position information of the operator 150 stored in the register circuit 301 is synchronized with the clock signals φ _A and φ _B. The signal is converted into a time-series serial signal, and sent out bit by bit from the serial signal output terminal _S0 . On the other hand, the mode setting signal SFT is "1" from the decoder 300 for eight periods of the clock signal _φB .
is output, and in synchronization with this, the position control information of the operator 150 is sent from the main device 2 in the form of an 8-bit serial signal, and this serial signal is read into the register circuit 301 one bit at a time and stored. After that, the mode setting signal is sent from the decoder 300.
When the LOD occurs, the signal is transferred to the latch circuit 302 and stored. The position control information stored in the latch circuit 302 is supplied to the comparison input A of the comparison circuit 305 as target position information A at which the current position of the operator 150 should be changed. The comparison circuit 305 compares the position control information A supplied to the comparison input A with the position information B representing the current position of the operator 150 given from the position sensor 151 to the comparison input B, and A>B. If so, the comparison result signal AGB is output, if A=B, the comparison result signal AEQB is output, and if A<B, the comparison result signal BGA is output. These comparison result signals AGB, AEQB,
BGA is supplied to motor control circuit 306. The motor control circuit 306 outputs a forward rotation signal UP and a reverse rotation signal DWN to the electric mechanism 152 of the operator device 10-10 based on the comparison result signals AGB, AEQB, and BGA output from the comparison circuit 305. Signal AGB from circuit 305
When this occurs, the forward rotation signal UP is output and the signal BGA
When this occurs, a reverse rotation signal DWN is output. These forward rotation signal UP and reverse rotation signal DWN are
The output continues until the comparison circuit 305 generates the comparison result signal AEQB. Therefore, when the position control information A of the operator 150 is supplied to the comparison circuit 305, this position control information A
is compared with controller position information B, and the comparison result signals AGB, AEQB,
Either BGA is output from this comparison circuit 305, and further, a forward rotation signal UP or a reverse rotation signal DWN is output from the motor control circuit 306 in accordance with this comparison result signal. As a result, the position of the operator 150 is changed to the position of the main device 2.
The position is changed and set according to the position control information transferred from. FIG. 11 shows the sub-device 30-10 shown in FIG.
3 is a circuit diagram showing a detailed configuration of the decoder 3.
00, the register circuit 301, and the latch circuit 302 have the same configuration as in FIG. 9, and are represented by the same symbols. Therefore, the configuration and operation of the comparison circuit 305 and motor control circuit 306 added in place of the gate circuit 304 in FIG. 9 will be described here. The comparison circuit 305 outputs information comparison inputs A ₁ to _{A 8} and B ₁ to _{B 8} of 8-bit configuration, and a comparison result signal AGB representing the relationship of information A>information B, information A=information B, and information B>information A. , AEQB, and BGA, respectively. The motor control circuit 306 also has an OR gate 3060.
and 3061, delay flip-flop 3062
and 3063, and gate 3064 and 3
065, inverters 3066 to 3068, and a delay circuit 3069. In such a configuration, when information A and B in the relationship A>B are input to the information comparison inputs A ₁ to _{A 8} and B ₁ to B ₈ of the comparator 3050, the comparator 305
A comparison result signal AGB is output from 0. This comparison result signal AGB is input to delay flip-flop 3062 via OR gate 3060 in motor control circuit 306. After being delayed by a time corresponding to one cycle of clock signal φ _B in delay flip-flop 3062 , it is supplied to AND gate 3064 . In this case, the gate input of the AND gate 3064 includes a signal obtained by inverting the comparison result signal BGA by the inverter 3066, and a comparison result signal BGA.
A signal delayed by a delay circuit 3069 after inverting AEQB by an inverter 3068
DL・ is input, but since the relationship is information A > information B, these signals and
Both DL and DL are "1" signals.
Therefore, the output signal of delay flip-flop 3062 supplied to AND gate 3064 is
is fed back to its own input side via
As a result, the comparison result signal AGB becomes OR gate 3
060, is held by a signal holding loop of delay flip-flop 3062 and AND gate 3064. The signal AGB held in this way is transferred from the output of the delay flip-flop 3062 to the motorized mechanism 15.
2, it is sent as a forward rotation signal UP. By outputting the forward rotation signal UP, the electric mechanism 152 rotates forward, and the current position of the operator 150 is sequentially changed toward the target position. After a certain period of time, when the position of the operator 150 reaches the target position indicated by information A, the comparator 3050 outputs a comparison result signal AEQB. Therefore, among the input signals of the AND gate 3064, the signal DL・
becomes a "0" signal, and as a result of the comparison, the AGB signal holding loop is released and the forward rotation signal UP becomes a "0" signal. As a result, the operation of changing the position of the operator 150 by the electric mechanism 152 is stopped, and the operation of changing the position of the operator 150 by the electric mechanism 152 is stopped.
The position of 0 is set to the position corresponding to information A. Such an operation is similarly performed in the circuit portion consisting of OR gate 3061, delay flip-flop 3063, AND gate 3065, and inverter 3067 when comparison result signal BGA is generated. Thereby, the operator 150 can be set at a position corresponding to the position control information A. In this case, the inverted signal of comparison result signal AEQB
AEQB and gates 3064 and 3065
The signal is not directly supplied to the target position, but is delayed for a certain period of time by the delay circuit 3069, and is supplied because the moving operation of the operator position is stopped near the center of the target position section. That is, as shown in FIG. 12, the position sensor 151 is connected to a substrate 1510 on which a code pattern representing the absolute position information of the operator 150 is formed, and is linked to the movement of the operator 150 and detects the code pattern surface of the substrate 1510. The position of the operator 150 is represented by the number of a section having a constant width. Therefore, brush 15
11, immediately after obtaining the target position information, set the forward rotation signal UP or reverse rotation signal DWN to “0”.
If a signal is used, the movement of the operator 150 will stop at the end of the target section n, and the contact state between the code pattern and the brush 1511 will become unstable, making it easy to malfunction. Therefore, here, the comparison result signal is delayed for a certain period of time, and the position movement operation of the operator 150 is stopped near the center of the target position section n. This allows the code pattern and brush 1
The contact state with 511 will also be stable, and malfunctions will no longer occur. It goes without saying that the position control information for the operator device 10-10 or the position information for the main device 2 can have any pit configuration depending on the weight of one scale of the operator 150. Further, the output information of the latch circuit 302 is, for example, 7
It is also possible to provide a configuration in which the parameter information is supplied to a segment decoder of a segment numeric display or a bar graph display, and the output signal of this segment decoder drives the numeric display or bar graph display to display parameter information. Further, when such a control device 10-10 is used, it goes without saying that one type of parameter information is set in one control device. Furthermore, in FIG. 1, the pushbutton switch and the light emitting diode are each independently assigned a 1-bit signal line, but only when the ON information from the pushbutton switch and the lighting information from the light emitting diode match, the 13th Common bit signal lines can be assigned as shown in the figure. However, if an independent 1-bit signal line is assigned to each of the pushbutton switch and the light emitting diode, an internal register of the central processing unit 20 is used to create a flag register that repeats the inverted state each time the pushbutton switch is pressed. By providing the output information of this register as a driving signal for the light emitting diode, the pushbutton switch can be used in a manner similar to a toggle switch. Such a function can be used, for example, when starting and stopping rhythm tone production. FIG. 14 is a diagram showing an example of an operation panel 400 of an electronic musical instrument in which the sub-devices described above are arranged, in which switches for setting various parameter information or displays for displaying information are grouped in units of eight. 1 set of operator circuits 10-20 to 10-27
It consists of And each operator circuit 10-2
On the back side of 0 to 10-27, sub-devices 30-20 to 30-27 having the above-mentioned configuration are arranged close to each other as shown by broken lines, and each sub-device is connected by a serial signal transmission line SDL. It is connected. As is clear from FIG. 14, the back side of the operation panel 400 has sub-devices 30-20 to 30-27.
Since only the serial signal transmission loop SDL and the serial signal transmission loop SDL are provided, the wiring condition on the back of the operation panel can be extremely simple, and accordingly, wiring work can be made more efficient and costs can be reduced. In addition, in the embodiment described above, the operator circuit 10-
Parameter information settings in steps 1 to 10-8 are performed using an on/off switch, but a changeover switch with multiple switching positions or a variable resistor (however, in this case, the output voltage of the variable resistor is set using an analog / digital conversion is required), etc. may be used to set the parameter state. In addition, in the embodiment shown in FIG. 1, the address bus A/BUS and the data bus D/
A keyboard circuit may be connected to the BUS via an interface circuit, and the central processing unit 20 may also perform key press detection processing. I Effects of the Invention As explained above, the present invention provides a plurality of operator circuits each including at least one of an operator for setting parameter data for musical tone formation and a display element for displaying the parameter data; If parameter data is set by the operator, musical tones are formed in accordance with the parameter data, otherwise musical tones are formed in a predetermined manner, and if parameter data is to be displayed, the display data of the generated parameter data is A parameter setting device for an electronic musical instrument comprising a main device that supplies information to the operator circuits, wherein a parameter setting device is provided corresponding to each of the operator circuits;
a plurality of sub-devices that transmit M-bit (M: positive integer) data in parallel to and from the control circuit;
A data signal line that connects the main device and the plurality of sub-devices in series, and a control signal line that is provided in common to the plurality of sub-devices and connects between the main device and the plurality of sub-devices. and the main device connects the control signal line to sequentially transmit N-bit (N: positive integer) data bit by bit between the main device and the plurality of sub-devices via the data signal line. The apparatus further includes a control means for controlling the plurality of sub-devices using the following. As a result, data signal lines can be shared by multiple sub-devices, and control signal lines can also be shared by multiple sub-devices, which simplifies the wiring state, improves the efficiency of wiring work, and reduces costs. It is possible to reduce the

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the parameter setting device according to the present invention, FIG. 2 is a memory map showing various buffer memory areas provided in the working memory and preset memory, and FIG. 3 is the same as shown in FIG. 1. A flowchart showing the operation contents of the embodiment, FIG. 4 is a circuit diagram showing a specific example of the interface circuit in the embodiment of FIG. 1, and FIGS. 5 and 7 are diagrams of the interface circuit shown in FIG. 6 and 8 are flowcharts for explaining the operation of the interface circuit, FIG. 9 is a circuit diagram showing one embodiment of the sub-device, and FIG. 10 is the sub-device. A block diagram showing another embodiment of the device, FIG. 11 is a circuit diagram showing the detailed configuration of the sub-device shown in FIG. 10, FIG. 12 is a diagram showing the configuration of the position sensor in FIG. 10, and FIG. 13 is a circuit diagram showing another embodiment of the operator circuit,
FIG. 14 is a diagram showing an example of an operation panel of an electronic musical instrument to which the present invention is applied. 1... Operator circuit group, 2... Main device, 3... Sub device group, 10-1 to 10-8, 10-10, 10
-x...Controller circuit, 20...Central processing unit, 23...Preset memory, 24...Interface circuit, 30-1 to 30-8, 30-10
...Sub device, 300...Decoder, 301...Register circuit, 302...Latch circuit, 304...
Gate circuit, 305... Comparison circuit, 306... Motor control circuit, 400... Operation panel.

Claims (1)

[Scope of Claims] 1. A plurality of operator circuits each including at least one of an operator for setting parameter data for musical tone formation and a display element for displaying the parameter data; If data is set, a musical tone is formed according to the parameter data, otherwise, a musical tone is formed in a predetermined method, and if parameter data is to be displayed, display data of the generated parameter data is supplied to the control circuit. A parameter setting device for an electronic musical instrument comprising a main device, which is provided corresponding to each of the control circuits, and transmits M-bit (M: positive integer) data in parallel to and from the control circuits. a data signal line connecting the main device and the plurality of sub-devices in series; a data signal line provided in common to the plurality of sub-devices and connecting between the main device and the plurality of sub-devices; A connecting control signal line is provided, and the main device communicates N bits (N:
1. A parameter setting device for an electronic musical instrument, comprising a control means for controlling said plurality of sub-devices using said control signal line so as to sequentially transmit data (a positive integer) bit by bit.