JPH0557790B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dial output device in a subscriber telephone.

For example, when making a call from an internal line to an outside line at a company, a pause time is required at the switchboard to switch and connect the lines. Therefore, the caller cannot perform the next dialing operation until this pause time has elapsed. Further, since the elapse of this pause time can generally be confirmed only by the caller who can hear it from the handset, there are cases where the next dial operation is mistakenly performed before the dial tone is heard, and the dial operation is invalidated. Therefore, for the caller, this pause time feels very long, and the dialing operation becomes troublesome.

The present invention enables a caller to perform dialing operations continuously regardless of the passage of pause time, for example, when making a call from an internal line to an outside line, and to perform dialing operations reliably and easily. With the goal.

Hereinafter, the present invention will be explained in detail based on an embodiment shown in the drawings.

The figure is an overall circuit diagram of this embodiment. In the figure, 1 is a keyboard with numerical keys arranged in a matrix, 2 is a pause button for performing a pause operation, and 3 is a crystal oscillation element. 4 is a one-chip IC including a circuit to be described later, and this IC4
The keyboard 1, pause button 2, and crystal oscillation element 3 are externally attached. In this IC4, 5
A keyboard logic 6 outputs signals corresponding to the operations of the keyboard 1 and the pause button 2, and a memory 6 stores the output of the keyboard logic 5, that is, the contents of dial operations.

9 is a timing generation circuit that performs an output operation in response to the output of the reference oscillation circuit 8; 7 is a write address generation circuit that provides a write address to the memory 6 in synchronization with the output timing of the timing generation circuit 9; 10 is an output circuit Signal and timing generation circuit 9 synchronized with dial output from 11
This is a read address generation circuit that provides a read address to the memory 6 based on the output timing of the .

The output circuit 11 performs a dial output based on the output from the command decoder 12 at a predetermined timing, and also outputs a dial output synchronization signal in synchronization with this dial output. The dial output is not output when there is no output from the command decoder 12, but even in that case, the output synchronization signal is continuously output at a predetermined output timing. The read address generation circuit 10 is configured to provide a read address to the memory 6 in synchronization with the output timing of the timing generation circuit 9 when there is a dial output synchronization signal from the output circuit 11. Reference numeral 12 denotes an instruction decoder that decodes the output of the memory 6 and provides the decoded output to the output circuit 11 and the pause circuit 13, which will be described next.

13 is a pause circuit, and this pause circuit 1
Reference numeral 3 includes a pause control circuit 14, a pause counter 15, and a pause clock generation circuit 16 which receive the output of the command decoder 12 and form a pause control output when the output content includes an operation of the pause button 2. A pause clock generating circuit 16 generates a clock signal for controlling the count period of the pause counter 15. pause counter 1
5 starts a counting operation upon receiving the control output from the pause control circuit 14, is counted up by a clock signal, and outputs a count end signal when a predetermined count is reached, including a circuit 11 and a read address generation circuit. Give 10.

The output circuit 11 stops the output operation and does not output the dial output or the dial output synchronization signal while the pause counter 15 is in the counting operation. That is, the output circuit 11 does not output either the dial output or the dial output synchronization signal while the pause counter 15 is counting, and outputs the dial output and the output synchronization signal when there is an output from the command decoder when the pause counter 15 is not counting. Both are performed, and if the output from the instruction decoder is not during counting, only the output synchronization signal is output.

When the output synchronization signal is not outputted from the output circuit 11 in the read address generation circuit 10, carry is also prohibited at the output timing of the timing generation circuit 9, that is, no data is read. The stoppage of the output operation of the output circuit 11 is canceled by receiving the count end signal from the pause circuit 13. Note that 17 is a mute output circuit that receives the output of the pause counter 15 and generates a mute output when the pause counter 15 is in counting operation. This mute output circuit 17 is used to mute unnecessary sounds from the receiver during pause so that they are not heard. The dial output in this embodiment may be either a tone dial or a pulse dial.

In the embodiment with the above configuration, when the caller makes a call from within the company to outside the company, the caller presses the "0" key for connecting to an outside line, and then presses the pause button 2 "P _A ".
The operation will be described in the case where the user presses , and then presses the keys "1", "2", etc. corresponding to the telephone number of the called party.

“0” is given by the keyboard logic 5 when the caller performs the key operation as described above.
Output signals "PA", "1", "2", etc. are sequentially written into the memory 6 based on the write address generated by the write address generation circuit 7. On the other hand, at the stage when the second "P _A " is written, the already written "0" is read out based on the dial output synchronization signal and the timing signal from the timing generation circuit 9. It is read out according to the generated read address and sent to the instruction decoder 12.

The command decoder 12 provides the decoded output of the signal to the output circuit 11, and the output circuit 11 performs dial output based on the decoded output. The decoded output from the instruction decoder 12 is also given to the pause circuit 13, but the pause circuit 13 does not operate.

The output circuit 11 reads out a signal synchronized with the above dial output timing and outputs it to the address generation circuit 1.
0, and as a result, the second “ _PA ” written in the memory 6 based on the read address generated by the read address generation circuit 10 is read out and sent to the instruction decoder 12, and the instruction decoder 12 The decoded output is given to the output circuit 11 and the pause circuit 13.

As a result, the pause counter 15 of the pause circuit 13 starts a counting operation, and the output operation of the output circuit 11 is stopped during the counting operation. With this stoppage of the output operation, the dial output from the output circuit 11 is no longer performed, and the synchronization signal synchronized therewith is no longer provided to the read address generation circuit 10. As a result, the read address generation circuit 10 can obtain the timing signal from the timing generation circuit 9 but cannot obtain the output synchronization signal, so it stops generating the read address.
Therefore, on the one hand, the dial output of "P _A " given from the instruction decoder 12 to the output circuit 11 is not performed, and on the other hand, the reading of "1" written third in the memory 6 is also not performed. .

Then, the pause counter 15 of the pause circuit 13
is counted up and a count end signal is given to the output circuit 11 and the read address generation circuit 10, so that the output of the output circuit 11 is restarted, and the read address generation circuit 10 generates a read address and writes 3 to the memory 6. The 1st written “1” is read out and given to the instruction decoder 12. In the above, the decoded output of " _PA " which has already reached the output circuit 11 becomes invalid because the output is stopped, and is not dialed out.

Since the pause circuit 13 is not activated, the values after "1" are processed in the same manner as the above "0", and are sequentially dialed out from the output circuit 11.

In this way, from the caller's side, the dialing operation becomes convenient and easy, since the caller will not be unable to perform the next dialing operation due to the pause time when passing through the exchange. Also,
Because pose operations are performed via memory,
If you press pause button 2 twice in a row, you will get double the pause time, if you press it three times in a row, you will get triple the pause time, etc. Depending on the number of times you press the pause button, you can create any pose. It is possible to set the time.

As described above, according to the present invention, the operation input of dial data and pause instruction data is stored in the memory, and the dial output is generated while performing a pause operation according to the stored contents, so that the operation input and the dial output are This allows the caller to perform a series of dial operations without waiting for the pause time to elapse. Therefore, even if the next dial operation is performed before the pause time has elapsed, the next dial operation will not be invalidated, making the dial operation extremely convenient and easy for the caller. Demonstrated.

Further, the present invention has excellent practicality, as there is no need for any registration operation or address designation operation for memory storage.

[Brief explanation of the drawing]

The figure is a circuit diagram of an embodiment of the present invention. 1...keyboard, 2...pause button, 6...memory, 13...pause circuit, 14...pause control circuit, 15...pause counter, 16...
...Pause clock generation circuit.

[Claims]

1. In a remote monitoring and control system of a teleconverter/telemeter system, a master station and a plurality of slave stations are opposed to each other by a two-wire telephone line, and at the slave stations, the two-wire telephone line is branched into a first four-wire line. connecting a telephone and a data terminal device to the first four-wire line, branching a substation to the first four-wire line via a second four-wire line to connect the telephone and the data terminal, and connecting the telephone and data terminal to the two-wire telephone line; For the 4-wire line, the voice band is divided into two bands to transmit the call signal and the data signal, and a supervisory control signal information bit for making and receiving calls is set in the data signal using the polling method. 1. A duplex communication system, characterized in that signal control is carried out for simultaneous full-duplex telephone calls and data communication between the master station and the slave stations or between the master station and the slave stations.