JPH0556460A - Synchronizing signal generator for test - Google Patents

Abstract

PURPOSE:To preclude the possibility of a defective operation of a monitor television receiver by storing a horizontal picture element number in a H register in response to number of picture elements of a image sensor to be tested so as to obtain a synchronizing signal almost coincident with a synchronizing signal of a waveform correct at all times. CONSTITUTION:Number of picture elements for a horizontal period H is set to an H register 21 and its 12-bit output and a 10-bit output whose lower-order bits omitted are added by an added by an adder 22. An 8-bit output resulting from omitting the lower-order from the 12-bit output from the adder 22 is fed to a 1st pulse generator 23, a 7-bit output resulting from omitting the low-order 5-bits from the 12-bit output from the adder 22 is fed to a 2nd pulse generator, 24, and a 6-bit output resulting from omitting the low-order 6-bits from the 12-bit output from the adder 22 is fed to a 4th pulse generator 24. The 8 and 6-bit outputs resulting from omitting the low-order 4/6-bits from the 12-bit from the adder 22 are fed to a multiplexer 26. A 11-bit output resulting from omitting 1-bit from the 12-bit output from the register 21 are subtracted from an output of the multiplexer 26 by a subtractor 27 and the result is fed to a 3rd pulse generator 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test sync signal generator applied to a sync signal generator for a television monitor output of a device for testing a two-dimensional image sensor used in a video camera.

[0002]

2. Description of the Related Art First, a general structure of an image sensor test apparatus in which the synchronizing signal generator of the present invention is used will be described with reference to FIG. CCD, one of the image sensors
When the device is tested, the analog signal of the analog system 11 of the CCD driving unit and the timing signal from the timing system 12 of the CCD driving unit are used as the CCD under test.
Is supplied to the device 13, and the output of the CCD device under test 13 is A
The data is converted into a digital signal by the D converter 14 and is once taken into the image data memory 15, the data taken into the image data memory 15 is processed by the image processing unit 16, and the processing result is stored in the output memory 17. Be done. The synchronizing signal generator 18 generates a synchronizing signal of the television signal, the synchronizing signal is supplied to the television monitor 19, and the output memory 17 is read in synchronization with the synchronizing signal and supplied to the television monitor 19. ..

[0003]

There are various types of image sensors, such as 200,000, 240,000, and 400,000 pixels, and the basic rate (frequency of the basic clock) depends on the element.
Is different. Even if the basic rates are different, the ratio of the pulse width to the horizontal cycle of the sync signal must be constant, but in the past, the count value that determines the pulse width remained constant, so the ratio of the pulse width to the horizontal cycle was There was a case where the TV monitor did not work well due to a large deviation from the official pair.

Further, the conventional image sensor test apparatus does not have a function of generating a high-definition television (HDTV) synchronizing signal. HDTV in the future
Conventional NTSC to test the image sensor for
It is not economically preferable to add the HDTV sync signal generator to the image sensor test apparatus for the PAL system or PAL system television because the hardware scale becomes large.
In this respect, one sync signal generator can
It is desired to be able to generate a PAL television synchronization signal and also an HDTV synchronization signal.

[0005]

According to the present invention, a value corresponding to the number of pixels of the horizontal period H is set in the H register,
The output of all bits of the H register and the output of which the lower 2 bits are omitted are added by an adder, and the output of which the lower 4 bits of the H register is omitted is subtracted from the output of which the lower 1 bit of the H register is omitted. Subtracted by a calculator, the output of the H register is input to the H clock generator, the basic clock is counted, and an H clock having a period of H or H / 2 is generated. The pattern memory is sequentially read every H clock, and the read output controls the cycle of the H clock generated from the H clock generator to H or H / 2. In the first pulse generator, the basic clock is counted from the H clock by the output value obtained by omitting the lower 4 bits of the adder to generate a pulse having a pulse width of approximately 0.08H, and the second pulse generator generates the pulse of the adder. The basic clock is counted from the H clock by the output value with the lower 5 bits omitted, and a pulse with a pulse width of approximately 0.04H is generated. The third pulse generator outputs the subtractor output value from the H clock as the basic value. The clock is counted to generate a pulse having a pulse width of approximately 0.42H. The output pulses of the first, second and third pulse generators and the output of the pattern memory are supplied to the first level selection signal generator, and the first level selection signal is generated according to the states of these inputs, A digital value corresponding to each point of the first level selection signal is output from the digital level generator to output a digital synchronizing signal, and the digital synchronizing signal is converted and output to an analog synchronizing signal by the DA converter.

According to the second aspect of the present invention, in the fourth pulse generator, the basic clock is counted from the H clock by the output value obtained by omitting the lower 6 bits of the adder, and the pulse width is approximately 0.02H. Instead of the pulse being generated and supplying the output with the lower 4 bits omitted to the subtractor, the output with the lower 6 bits omitted from the adder can be switched and supplied by the first multiplexer. The outputs of the third and fourth pulse generators and the output of the pattern memory are supplied to the second level selection signal generator, the second level selection signal is generated according to the states of these inputs, and the second level selection signal is generated. Can be switched to the digital level generator by the second multiplexer instead of the first level selection signal.

[0007]

FIG. 1 shows an embodiment of the present invention. The number of pixels in one horizontal cycle H (including the horizontal blanking period) is set in the H register 21. The H register 21 has, for example, 12 bits, and the 12-bit output and the 10-bit output in which the lower 2 bits are omitted are added by the adder 22.
The 8-bit output from which the lower 4 bits of the 12-bit output from the adder 22 is omitted is supplied to the first pulse generator 23, and the lower 5 bits from the adder 22 is omitted 7
The bit output is supplied to the second pulse generator 24, and the 6-bit output from the adder 22 in which the lower 6 bits are omitted is supplied to the fourth pulse generator 25.

An 8-bit output and a 6-bit output from which the lower 4 bits and 6 bits are omitted are supplied from an adder 22 to a pair of inputs of a multiplexer 26, respectively. 1 with the lower 1 bit from the H register 21 omitted
The output of the multiplexer 26 is the subtractor 2 from the 1-bit output.
Subtracted by 7. The output of the subtractor 27 is supplied to the third pulse generator 28. The basic clock from terminal 29 is the first
Is supplied to the fourth pulse generators 23, 24, 28, 25 and the H clock generator 31. The output of the H register 21 is given to the H clock generator 31, and the cycle is H or H / 2.
To generate the H clock. The pattern memory 32 is read every H clock.

A pattern of the synchronizing signal is stored in the pattern memory 32, and the H clock generator 31 determines whether to generate H or H / 2 based on the pattern data read from the pattern memory 32. Is done. H
The clock is the first to fourth pulse generators 23, 24, 28,
25, and the synchronous start pulse from the terminal 33 is supplied to the first to fourth pulse generators 23, 24, 28, 25, H.
It is given to the clock generator 31 and the pattern memory 32. First to fourth pulse generators 23, 24, 28, 25
Each time the synchronous start pulse and the H clock are respectively input, the basic clock is counted by each given digital value, and a pulse having a width corresponding to the digital value is output. The read address of the pattern memory 32 is reset by the synchronous activation pulse.

First to fourth pulse generators 23, 24, 2
Synchronous signal can be created using pulses from 8, 25
Explain that. FIG. 2A shows a HDTV sync signal.
T in the figure ₀Is the starting point of the synchronization signal, and the starting point t₀Sync from
Time t to each change point of the signal (waveform)₁~ T₆Is the horizontal circumference
The relationship with the period H is as shown in the figure. water
The flat period H is about 29.63 μS in HDTV. Also
In HDTV, each part of the sync signal is low level L, medium level
Take one of three levels, M and high level H.

As shown in FIG. 2B, the synchronizing signals of the NTSC system and the PAL system have a time t _{7 to} t ₁₁ from the starting point t ₀ to each change point of the synchronizing signal, as shown in the figure with respect to the horizontal period H. Get involved. The horizontal period H is about 63.5 μS in the NTSC system and 64 μS in the PAL system. Each part of the synchronization signal takes either a low level L or a medium level M. t
₂ and t ₇ are both about 0.04H, t ₃ and t ₁₁ are both about 0.08H, t ₅ and t ₈ are both 0.5H,
Both t ₆ and t ₉ are H.

[H + (H / 4)] / 16 = 5H / 64 = 0.078H≈0.08H. Since the output of the H register 21 without the lower 2 bits is H / 4, the adder 22 outputs H + (H / 4) = A.
Is calculated and the lower 4 bits of A are omitted.
/16=0.078H≈0.08H=B is supplied to the first pulse generator 23. Therefore, the first pulse generator 23 outputs a pulse having a width of about 0.08H. The second pulse generator 24 has a value A / 32 in which the lower 5 bits of A are omitted.
= B / 2≈0.04H is supplied to the second pulse generator 2
A pulse having a width of 4 to about 0.04H is output. A value B / 4≈0.02H in which the lower 6 bits of A are omitted is supplied to the fourth pulse generator 25, and a pulse having a width of about 0.02H is output from the fourth pulse generator 25.

T ₄ = t ₅ −t ₁ and t ₅ is 0.5
Since the output is H, that is, the lower 1 bit of the H register 21 is omitted, the output of the subtracter 27 is 0 by selecting the output (B / 4) of the adder 22 in which the lower 6 bits are omitted. .5H-B / 4≈t ₄ , and
At this time, the third pulse generator 28 outputs a pulse having a width of about t ₄ . Lower 4 of adder 22 in multiplexer 26
When the output B is omitted bit is selected, the output of the subtractor 27 is _{0.5H-B ≒ t 8 -t 11} = t 10 , and the pulse of the third pulse generator 28 width of about t ₁₀ from the output To be done.

As described above, the first to fourth pulse generators 2
3,24,28,25 to about 0.08H≈t ₃ = t ₁₁ ,
About 0.04H≈t ₂ = t ₇ , about t ₄ or about t ₁₀ , about 0.
Since pulses of each width of 02H≈t ₁ can be obtained, by combining these, the HDTV sync signal, NTSC /
It will be appreciated that any of the PAL sync signals can be created. First to fourth pulse generators 23, 2
The respective outputs of 4, 28, and 25 and the read output of the pattern memory 32 are supplied to the digital synchronizing signal generator 34 to generate a digital synchronizing signal, and the digital synchronizing signal is D
The A converter 35 converts the analog signal into an analog signal to obtain a synchronization signal.

FIG. 3 shows a concrete example of the digital synchronizing signal generator 34. The output pulse of the first pulse generator 23 is supplied to the OR circuits 36 and 37, the output pulse of the second pulse generator 24 is supplied to the input circuit A1 of the OR circuit 38 and the dual decoder 39, and the fourth pulse generator 25. Is supplied to the input terminal A2 of the dual decoder 39,
The output pulse of the third pulse generator 28 is supplied to the OR circuit 41. The read output of the pattern memory 32 is also supplied to the OR circuits 36, 37, 38, 41. OR circuit 3
The outputs of 6 and 41 are supplied to the input terminals E0 and E1 of the dual decoder 39, respectively. OR circuit 37, 38, 4
Each inverted output of 1 is inverted and supplied to the AND circuit 42.

The OR circuits 37, 38, 41 and the AND circuit 42 constitute a first level selection signal generator 43, the output of which is supplied to the input terminal A1 of the multiplexer 44, and the input terminal A2 of the multiplexer 44 is always kept "". 0 ”is given. The output terminals Q03 and Q04 of the dual decoder 39 are connected to each other, and the connection point and the output terminal Q
00 is connected to both input sides of the exclusive OR circuit 45,
The output terminal Q02 and the output side of the exclusive OR circuit 45 are connected to the input terminals B0 and B1 of the multiplexer 44, respectively. OR circuits 36 and 41 and dual decoder 3
9. The exclusive OR circuit 45 constitutes a second level selection signal generator 46.

The outputs Q0, Q1 of the multiplexer 44 are supplied to the input terminals A, B of the level generator 47, and the input terminals D0, D1, D2 of the level generator 47 have 8-bit digital levels M, H, L respectively. Is supplied. The level generator 47 receives the input terminal D according to the values of the input terminals A and B.
The digital level of 0, D1 or D2 is output terminal Q
Through the DA converter 35. When the mode selection signal from the terminal 48 is "0", the multiplexer 44 selects the input of its input terminals A0 and A1, and when the mode selection signal is "1", the input of the input terminals B0 and B1 is selected. .. Further, in FIG. 1, the multiplexer 26 has a terminal 48.
If the mode selection signal is 0, the 8-bit output with the lower 4 bits omitted is selected, and the mode selection signal is 1
In the case of, the 6-bit output with the lower 6 bits omitted is selected.

The synchronizing signal of the NTSC / PAL system is shown in FIG. 4H.
The waveform is as shown in FIG. 2, and this waveform has a waveform of 0.5H in section 49 and a waveform of 0.5H in section 51.
The length 52 of the section 52 is combined with a waveform. From the starting point t ₀ , that is, the synchronous start pulse (FIG. 4A), data D ₁ , D ₂ , and D ₃ indicating which of the sections 49, 51, and 53 belong to each part of the synchronization signal are arranged as shown in FIG. 4G. These data are stored in the pattern memory 32 in this order. When the data D ₁ and D ₂ are read, that is, in the intervals 49 and 51, the H clock generator 31 generates an H clock having a cycle of 0.5H, and when the data D ₃ is read, that is, the interval 52. Then, the H clock generator 31 is controlled to generate an H clock having a cycle of H.

Therefore, when the synchronous start pulse shown in FIG. 4A is input, the H of the address counter in the pattern memory 32 is set.
The count value of the clock changes as shown in FIG. 4I.
The H clock generator 31 initially generates the H clock as shown in FIG.
4 to 4D, the first pulse generator 23 generates the pulse shown in FIG. 4E, and the third pulse generator 28 generates the pulse shown in FIG. 4F. Data D ₁
Is read out, the output pulse of the second pulse generator 24 is inverted through the OR circuit 38 and the AND circuit 42 and output as the waveform of the section 49. This waveform is repeated, and when the H clock count reaches 7, the data D ₂ is read from the memory 32. In this state, the third pulse generator 2
The output pulse of No. 8 is inverted by the OR circuit 41 and the AND circuit 42 and output as the waveform of the section 51. This waveform is repeated, and when the H clock count reaches 13, the section 49 is restarted.
When the waveform of is repeated and the count of H clock reaches 19,
Data D ₃ is read, the H clock cycle becomes H,
The output pulse of the first pulse generator 23 is inverted through the OR circuit 37 and the AND circuit 42 and output as the waveform of the section 52, which is repeated. In this way NTSC /
A signal having substantially the same waveform as the PAL synchronizing signal is output from the first level selection signal generator 43 as the first level selection signal.

NT of "1" and "0" shown in FIG. 4H
The SC / PAL sync signal is supplied to the input terminal A1 of the multiplexer 44, the input terminal A0 is always "0", and the input terminals A0 and A1 are selected as the first level selection signal and supplied to the level generator 47. To be done. The level generator 47 inputs a digital value indicating a medium level M when A = 0 and B = 0, a digital value indicating a low level L when A = 0 and B = 1, and a digital value indicating A = 1 and B = 0. The digital value indicating the high level H is output. Therefore, from level generator 47 to NT
An SC / PAL digital sync signal is output, and this is converted into an analog signal by the DA converter 35 to obtain an analog sync signal.

The HDTV sync signal has the waveform shown in FIG. 5H. This waveform is composed of a combination of a waveform having a length of 0.5H in the section 53, a waveform having a length of 0.5H in the section 54, and a waveform having a length of H in the section 55. Section 53 is 0.
02H low level L and 0.02H high level H, and 0.
The middle level M of 04H and the low level L of (0.5-0.8) H are successively connected, and the interval 54 is high level H of 0.02H at the beginning of 0.5H and 0.02H at the end. It consists of a low level L and an intermediate level M between them, and the section 55 is 1H.
It has a high level of 0.02H at the beginning, a low level L of 0.02H at the end, and an intermediate level M between them. The section 53 is repeated from the starting point (the synchronization start signal in FIG. 5A), then the section 54 is repeated twice, and the section 55 is repeated. Data D ₄ , D ₅ , and D ₆ indicating which of the sections 53, 54, and 55 belong to each part of the synchronization signal from the synchronization start pulse (FIG. 5A) are arranged as shown in FIG. 5G, and this data is arranged in this order. It is stored in another area of the pattern memory 32. That is, the mode selection signal of the terminal 48 is also supplied to the pattern memory 32, the mode selection signal is "0",
In the NTSC / PAL system data area, the HDTV data area is read when the mode selection signal is "1".

In the dual decoder 39, the input terminal E0
Input is "1" and output terminals Q00-Q03 are output,
Input terminal E1 is "1" and output terminals Q10 to Q13
Is output. Further, the input states of the input terminals A0 and A1 are decoded to output the output terminals Q00 to Q03 and Q10 to Q1.
3 and 3, respectively. The H clock is generated as shown in FIG. 5B, the pulse shown in FIG. 5C is generated from the fourth pulse generator 25, the pulse shown in FIG. 5D is generated from the second pulse generator 24, and the first pulse generator 23 is generated. From the third pulse generator 28 shown in FIG. 5F.
The pulse shown in is generated. The output of the second level selection signal generator 46 is selected by the multiplexer 44 in response to these four pulses, and at that time, the output generated from the level generator 47 is dual so that the HDTV sync signal shown in FIG. 5H is generated. The contents of the decoder 39 are created. Therefore, if the mode selection signal at the terminal 48 is set to "1", the DA converter 35 can obtain the HDTV synchronizing signal.

[0023]

As described above, according to the present invention, if the number of horizontal pixels is stored in the H register 21 according to the number of pixels of the image sensor under test, the adder 22 and the subtractor 2
7. Even if the basic clock frequency is changed using the first to third pulse generators 23, 24 and 28, the H clock generator 31, and the pattern memory 32, the horizontal cycle is always predetermined according to the change. Since a pulse with a pulse width of the ratio is generated and each part of the sync signal is generated from these three pulses, it is always possible to obtain a sync signal with a correct waveform and a sync signal, which may cause a malfunction of the monitor TV. Absent.

The HDTV sync signal can be obtained only by adding the fourth pulse generator 25, multiplexers 26 and 44, and the second level selection signal generator 46 to the portion required to generate the NTSC / PAL sync signal. Can be generated, and the hardware scale can be remarkably reduced compared to the case where the NTSC / PAL sync signal generator and the HDTV sync signal generator are provided independently, and the configuration is inexpensive. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a ratio of a waveform of a synchronization signal to a horizontal cycle H of each part.

3 is a block diagram showing a specific example of a digital synchronizing signal generator 34 in FIG.

FIG. 4 is a time chart showing a synchronizing signal generating operation of the NTSC / PAL system.

FIG. 5 is a time chart showing a synchronizing signal generating operation of HDTV.

FIG. 6 is a block diagram showing a general configuration of an image sensor test device.

[Procedure amendment]

[Submission date] July 24, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

The OR circuits 37, 38, 41 and the AND circuit 42 constitute a first level selection signal generator 43, the output of which is supplied to the input terminal A1 of the multiplexer 44, and the input terminal A2 of the multiplexer 44 is always kept "". 0 ”is given. The output terminal Q03 of the dual decoder 39 and
Q10 is connected to each other, the connection point and the output terminal Q
00 is connected to both input sides of the exclusive OR circuit 45,
The output terminal Q02 and the output side of the exclusive OR circuit 45 are connected to the input terminals B0 and B1 of the multiplexer 44, respectively. OR circuits 36 and 41 and dual decoder 3
9. The exclusive OR circuit 45 constitutes a second level selection signal generator 46.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

The synchronizing signal of the NTSC / PAL system is shown in FIG. 4H.
The waveform is as shown in FIG. 2, and this waveform has a waveform of 0.5H in section 49 and a waveform of 0.5H in section 51.
The length 52 of the section 52 is combined with a waveform. From the starting point t ₀ , that is, the synchronous start pulse (FIG. 4A), data D ₁ , D ₂ , and D ₃ indicating which of the sections 49, 51, and 52 each part of the synchronization signal belongs to are arranged as shown in FIG. 4G. These data are stored in the pattern memory 32 in this order. When the data D ₁ and D ₂ are read, that is, in the intervals 49 and 51, the H clock generator 31 generates an H clock having a cycle of 0.5H, and when the data D ₃ is read, that is, the interval 52. Then, the H clock generator 31 is controlled to generate an H clock having a cycle of H.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

The HDTV sync signal has the waveform shown in FIG. 5H. This waveform is composed of a combination of a waveform having a length of 0.5H in the section 53, a waveform having a length of 0.5H in the section 54, and a waveform having a length of H in the section 55. Section 53 is 0.
02H low level L and 0.02H high level H, and 0.
And level M within 04H, (0.5- 0.1) and a low level L of H, are continuous and level M sequentially in a 0.02 H, section 54 is low at the beginning of 0.02 H of 0.5H With level L
It consists of a high level H of 0.02H and a medium level M of (0.5-0.04) H , and the interval 55 is 0.02 at the beginning of 1H.
Low level L of H and high level H of 0.02H, (1-
0.04) H and medium level M. The section 53 is repeated from the starting point (the synchronization start signal in FIG. 5A), then the section 54 is repeated twice, and the section 55 is repeated. Section 5 for each part of the synchronization signal from the synchronization start pulse (FIG. 5A)
Data D ₄ , D indicating which of 3, 54, 55 they belong to
₅ and D ₆ are arranged as shown in FIG. 5G, and this data is stored in another area of the pattern memory 32 in this order.
That is, the mode selection signal at the terminal 48 is the pattern memory 32.
, The mode selection signal is "0", NTSC /
The data area of the PAL system and the data area of the HDTV are read when the mode selection signal is "1".

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

Claims (2)

[Claims] 1. An H register in which a value corresponding to the number of pixels in a horizontal period H is set, and an adder for adding all bits in the output of the H register and an output in which the lower 2 bits are omitted. , A subtracter for subtracting the output of the output of the adder omitting the lower 4 bits of the output from the output of the H register, and the output of the H register are input, and the basic clock is input. An H clock generator that counts and outputs an H clock having a cycle of H or H / 2, and the H clock generator sequentially reads out every H clock and outputs the H clock.
A pattern memory for controlling whether the period of the H clock generated from the clock generator is H or H / 2, and an output in which the lower 4 bits in the output of the adder are omitted are supplied. A first pulse generator that counts the basic clock from the H clock to generate a pulse having a pulse width of approximately 0.08H and an output in which the lower 5 bits of the output of the adder are omitted are supplied, and only that value is supplied. A second pulse generator that counts the basic clock from the H clock to generate a pulse having a pulse width of approximately 0.04H, and the output of the subtractor are supplied, and the value of the second pulse generator is used to output the basic clock from the H clock. And the pulse width is almost 0.
A third pulse generator that generates a 42 H pulse, and output pulses of the first, second, and third pulse generators,
A first level selection signal generator which is supplied with the output of the pattern memory, and which generates a first level selection signal according to the input states of the three pulses and the output of the supplied memory; A test sync signal generator comprising: a digital level generator that outputs a digital sync signal having a digital value corresponding to a first level selection signal; and a DA converter that converts and outputs the digital sync signal into an analog sync signal. 2. An output from which the lower 6 bits of the output of the adder is omitted is supplied, and the basic clock is counted from the H clock by that value, and the pulse width is approximately 0.02H.
4th pulse generator for generating the pulse of the above, and instead of supplying the output omitting the lower 4 bits to the subtracter, switching and supplying the output omitting the lower 6 bits in the output of the adder. And a first multiplexer capable of performing the above, the output pulses of the first, second, third, and fourth pulse generators and the output of the pattern memory are supplied, and a second level selection signal is generated in accordance with these states. A second level selection signal generator for switching between the second level selection signal and the second level selection signal instead of the first level selection signal and supplying the second level selection signal to the digital level generator.
The test synchronization signal generator according to claim 1, further comprising: a multiplexer.