JPH0555879A - Staircase wave generating circuit - Google Patents

Abstract

PURPOSE:To provide this staircase wave generating circuit with simple constitution and effective flatness under high voltage and rapid conditions. CONSTITUTION:A voltage dividing means for dividing voltage between VH and VL is constituted of a serial circuit of n resistors R1 to Rn and divided voltages V1 to Vn-1 are obtained. One terminals of switch means S1 to Sn-1 are respectively connected to divided voltages V1 to Vn-1 through n reverse current interrupting diodes D1 to Dn-1, one terminal of a switch element Sn is connected to a high level power supply VH and the other terminal is connected to an output terminal OUT to form a switching means. The diodes D1 to Dn-1 prevent the current flows in the shown right direction through the switch elements S1 to Sn-1. A resistor R0 is connected between the output terminal OUT and the power supply VL and the switch elements S1 to Sn are turned on by trigger signals TR1 to TRn outputted from a trigger means 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a staircase wave generation circuit, which can be suitably used for a framing camera, for example.

[0002]

2. Description of the Related Art A framing camera deflects photoelectrons generated by the image formation on the photoelectric surface of a streak tube by an optical system by a high voltage applied to a deflection plate to form an electron-optical image on the fluorescent surface. Is moved to obtain a time-resolved image. Since the high voltage applied to the deflecting plate sequentially moves the image formed on the fluorescent surface, it is necessary to apply a high-voltage and high-speed staircase wave. As a method of generating a high-voltage staircase wave, a method of combining a sawtooth wave and a lamp voltage is known (US Patent N
o.3,887,841 June 3,1975). This is to obtain a staircase wave by superimposing two ramp waves having different periods.

[0003]

A staircase wave generation circuit used in a framing camera needs to have a simple structure and high withstand voltage in consideration of high voltage and high speed conditions.
Moreover, the flatness must be good. However, in the staircase wave generation circuit according to the conventional example described above, it is difficult to accurately match the ramp voltage accuracy (linearity) and the slope of the sawtooth wave with the slope of the ramp voltage, so that an accurate framing image cannot be obtained. On the other hand, although there are various methods for obtaining a sharply rising staircase voltage, it was difficult to find a method satisfying the above conditions.

An object of the present invention is to solve the above problems.

[0005]

The staircase wave generation circuit of the present invention has a plurality of voltage dividing elements (resistor, Zener diode, etc.) connected in series between two power supplies having different voltage levels and two Voltage dividing means for dividing the potential difference between the power supplies into a plurality of levels, and a plurality of switching elements (FET, bipolar transistor, photo transistor) having one end to which the divided output of the voltage dividing means is provided and the other end commonly connected to the output terminal. Coupler, etc.) and a reverse current blocking element (diode, etc.) that blocks the flow of current through the switch element when the voltage of the divided output of each of these switch elements is lower than the output terminal voltage. It is characterized in that it is provided with a switch means for outputting a wave voltage and a trigger means for individually turning on a plurality of switch elements.

Further, it may be characterized in that a capacitor is further provided between the ground potential and each of the divided outputs of the dividing means.

The switch means may further include a return switch element which is connected to the output terminal and one of the two power supplies and is turned on / off by the output of the trigger means.

[0008]

According to the present invention, the power supply voltage is divided into a plurality of levels of voltage by the voltage dividing means, and the plurality of levels of divided voltage are sequentially output by sequentially turning on the plurality of switch elements.

If a capacitor is further provided,
The output impedance of the circuit for generating the divided voltage can be reduced.

When the recovery switch element is further provided, by turning on the recovery switch element, the output from the output terminal is immediately reset to one of the two power supplies.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the basic configuration of the circuit of the embodiment. As shown in the figure, the voltage _dividing means is constituted by a series circuit of _n resistors R ₁ to R _n , which is a high level power source V _H.
And a low level power supply V _L. During this time of a potential difference V _H -V _L is divided by the resistors R ₁ to R _n, the divided voltage V ₁ ~V _n-1 are obtained. In addition, for example, switch elements S _{1 to} S composed of FETs and bipolar transistors
One end of the _n-1 are connected to respective divided voltage V ₁ ~V _n-1 through the diode D ₁ to D _n-1 for preventing reverse flow. One end of the switch element S _n is connected to the high level power supply V _H. Further, the other ends of the switch elements S _{1 to} S _n are connected to the output terminal OUT, and these form a switch means. The diodes D _{1 to} D _n-1 have divided voltages V _{1 to} V _1.
When each of _n-1 becomes lower than the output terminal OUT, the divided voltage V ₁ to Vn is passed through the switch elements S _{1 to} S _n-1.
This is to prevent a current from flowing to V _n-1 . A resistor R ₀ is connected between the output terminal OUT and the power supply V _L. Trigger means 4 is constituted by ECL and TTL, is to turn on the trigger signal TR ₁ to Tr _n switching elements S ₁ to S _n.

In the above-mentioned staircase wave generation circuit, n = 4
The operation will be described with reference to the timing chart of FIG.

First, the switch elements S _{1 to} S _n are 4 in total.
, Therefore the resulting voltage level is the power supply V _H ,
In addition to the two levels of the power supply V _L , there are a total of five levels of the divided voltages V _{1 to} V ₃ . As shown on the left side of FIG.
When all the switch elements S _{1 to} S ₄ are off (Fig. 2
In the state (t _{0 in} (a)), the output terminal OUT has a resistance R _0.
In so short-circuited to the power source V _L, the output level V _OUT =
It becomes V _L. Switching element S by trigger signal TR _1
When only ₁ is turned ON, the output level V _OUT becomes V ₁ (state of t _{1 in} FIG. 2A). When the switch element S ₂ in addition to the switching element S ₁ is turned ON by the trigger signal TR _2, t of the output level V _OUT is to be V ₂ (FIGS. 2 (a)
State ₂ ). At this time, since the level V ₂ is higher than the level V ₁ , the diode D ₁ is reverse biased and the current to the level V ₁ is blocked. Further, when the switch element S ₃ is turned on by the trigger signal TR ₃ in addition to the switch elements S ₁ and S ₂ , the output level V _OUT becomes V ₃ (state of t _{3 in} FIG. 2A). Furthermore, switch element S ₄
Is turned on by the trigger signal TR ₄ , the output level V _OUT
Becomes the same potential as the power supply V _H (state of t _{4 in} FIG. 2A). Finally, when the switch elements S _{1 to} S ₄ are turned off, the voltage does not immediately become V _L, and the fall thereof becomes somewhat gentle due to discharge of the stray capacitance of the load connected to the output terminal OUT (Fig. 2 (a) after t ₅ ). Here, a switch element S _L is provided as shown by the dotted line, and when this switch element S _L is turned on, the output terminal OUT is short-circuited with the power supply V _L and the output level V _L is immediately output.
_OUT = _VL .

On the other hand, as shown in FIG. 2B, when the switch elements S ₂ and S ₄ are sequentially turned on, the output level V _OUT rises from the level of the power source V _L to V ₂ , and the switch element S continues.
_{When 4} is turned on, the output level V _OUT changes from V ₂ to the power supply V
_Reach the _H level. Therefore, in this case, as shown in FIG.
A two-step staircase voltage different in step width and step from that of (a) can be obtained.

Here, when the staircase voltage is generated so that one voltage change is generated by the ON operation of the plurality of switch elements, a slight shift in control timing causes ON resistance noise of the switch elements. It does not have a very good waveform. However, in the above-mentioned staircase wave generation circuit, the output level V
_{Since OUT} is changed, control becomes easier, and
In principle, such a noise does not occur because the control timing does not deviate.

Therefore, according to the present invention, a high-speed staircase voltage of 10 ns or less can be obtained by using a high-speed switching element such as an FET or a bipolar transistor for the switch element S. Moreover, the step width can be easily changed only by changing the timing of triggering the switch element S. Further, since the output voltage of each stage is a divided voltage by the voltage dividing means, the flatness can be extremely excellent. Further, since the staircase wave generating circuit of the present invention is composed of elements such as FETs, diodes and resistors capable of withstanding a high withstand voltage of about 1 kV or more, a high stepwise wave voltage can be easily obtained.

FIG. 3 shows a staircase wave generating circuit according to the second embodiment of the present invention.

In this embodiment, the switch elements S _{1 to} S _{4 are}
Together with composed of FET, connect a diode D ₁₁ to D ₁₄ between its gate and source to protect the switching element S ₁ to S ₄ from the reverse voltage. Further, the switch elements S ₁ ~
The pulse transformers T _{1 to} T ₄ are connected between S ₄ and the trigger means 4 to isolate the power source.
Then, the trigger signals TR _{1 to} TR 4 from the trigger means ₄
Is input to the switch elements S _{1 to} S ₄ via the buffers B _{1 to} B ₄ and the capacitors C _{1 to} C ₄ . Further, capacitors C _{11 to} C ₁₄ are connected to the power source V _H and the divided voltages V _{1 to} V ₃ , respectively, and the other ends of these capacitors are connected to the ground line.

In this circuit, when the trigger means 4 and the FET constituting the switch element S are transformer-coupled and only an AC component can be transmitted, a square wave having a long period, that is, a step width of a staircase voltage is long. Then sag occurs, and FET
May gradually change from the ON state to the OFF state.
Therefore, a burst pulse is applied to the gate of the FET during the step width of the staircase voltage so that the ON state of the FET (switch element S) is lengthened. FIG. 4 shows an example in which the circuit of FIG. 3 is operated in the same manner as the time chart of FIG. In this figure, the trigger signals TR ₁ ...
The relationship between TR ₄ , the waveform of the staircase voltage, and the burst pulse is shown.

FIG. 5 shows a main part of a staircase wave generating circuit according to the third embodiment of the present invention.

In this embodiment, the switch elements S _{1 to} S _{4 are}
Is composed of a photo coupler. With this arrangement, the trigger means 4 and the switch element S for generating the high-voltage staircase voltage can be insulated, so that the isolation with respect to the power source is facilitated as in the second embodiment using the pulse transformer. ..

Next, a specific example of a framing camera to which the staircase wave generation circuit of the present invention is applied will be described.

FIG. 6 is a block diagram of a specific example thereof, and FIG. 7 is a time chart showing the operation. As shown in the figure, the high-voltage staircase voltage (shown in FIG. 7B) from the vertical deflection voltage generation circuit 13 is applied to the vertical deflection electrode 26 of the streak tube 20, and the horizontal deflection voltage generation circuit 14 is applied to the horizontal deflection electrode 27. A high-voltage square-wave voltage (shown in FIG. 7 (d)) is applied.
Further, the MCP (micro channel plate) 28 has an MCP gate voltage from the gate voltage generation circuit 15 (see FIG. 7).
(C) Shown) is applied. The waveform shown in FIG. 7A corresponds to the trigger pulse TRIG. Indicates IN.

In the framing camera configured as described above, when the light to be measured (image) is incident on the photocathode 22 of the streak tube 20, photoelectrons are emitted from the photocathode 22 and are coupled to the MCP 28 by the electron optical system. To be imaged. At this time, since the staircase voltage is applied to the vertical deflection electrode 26, the electron beam is vertically deflected in four steps according to the voltage change. Further, since the square wave is applied to the horizontal deflection electrode 27, the electron beam deflected in the vertical direction is further deflected in two steps in the horizontal direction. Therefore, M
Images of 8 frames are formed at different positions on the CP 28. Further, since the gate voltage is applied to the MCP 28, it functions as a shutter, and therefore the fluorescent surface 30.
The image formed in Fig. 6 and Fig. 7 (e) is (1),
As shown by (2), (3), ... (7), (8), there are eight side-by-side images. Then, the images of the eight frames are the periods (1), (2), ... (7), of FIG.
This corresponds to the measured light image of (8).

The present invention is not limited to the above embodiment, but various modifications can be made.

For example, the staircase voltage generated by the circuit of the present invention is not limited to low voltage to high voltage, but can be changed from high voltage to low voltage by reversing the polarities of the elements and the power supply. Further, in the embodiment, only the application to the framing camera is shown, but it is also possible to widely apply to the CRT and the like, and by doing so, high-speed and high-resolution continuous imaging becomes possible.

[0028]

As described above in detail, according to the present invention, the power supply voltage is divided into a plurality of levels of voltage by the voltage dividing means, and a plurality of switching elements are sequentially turned on to divide a plurality of levels. The voltage is output sequentially. Therefore, it is possible to obtain a staircase voltage having a high voltage and a high speed, an extremely sharp rise or fall, and high flatness. Moreover, since the output impedance of the circuit for generating the divided voltage can be lowered by further including the capacitor, the rise of the output can be made steeper and the flatness can be improved. Since the output is immediately reset to one of the two power supplies by further including the return switch element, the cycle of repetitive operation can be shortened.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of a staircase wave generation circuit according to an embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the staircase wave generation circuit according to the embodiment of the invention.

FIG. 3 is a configuration diagram of a staircase wave generation circuit according to a second embodiment.

FIG. 4 is a time chart explaining the operation of the second embodiment.

FIG. 5 is a main part configuration diagram of a staircase wave generation circuit according to a third embodiment.

FIG. 6 is a configuration diagram of a framing camera to which the present invention has been applied.

FIG. 7 is a time chart explaining the operation of the framing camera to which the present invention is applied.

[Explanation of symbols]

4 ... Trigger means 14 ... Horizontal deflection voltage generating circuit 15 ... Gate voltage generating circuit 20 ... Streak tube 21 ... Photosensitive surface plate 22 ... Photoelectric surface 23 ... Grid 24 ... Electron lens 25 ... Anode electrode 26 ... Vertical deflection electrode 27 ... Horizontal deflection electrode 28 ... microchannel plate (MCP) 29 ... output faceplate 30 ... fluorescent face S ₁ to S _n ... switching elements V ₁ ~V _n-2 ... divided voltage D ₁ ~D _n-2 ... reverse-blocking diode R ₂ ~ R _n ... resistor for voltage division OUT ... output terminal. 61 ... Logic circuit

Claims (3)

[Claims] 1. A voltage dividing unit which has a plurality of voltage dividing elements connected in series between two power sources having different voltage levels, and which divides a potential difference between the two power sources into a plurality of levels; A plurality of switch elements to which the divided output of each of the voltage dividing means is provided and the other end of which is commonly connected to an output terminal, and when the voltage of the divided output of each of these switch elements is lower than the output terminal voltage. A reverse current blocking element that blocks a current from flowing through the switch element, and switch means that outputs a staircase wave voltage from the output terminal; and trigger means that individually turns on the plurality of switch elements. A staircase wave generation circuit. 2. The staircase wave generation circuit according to claim 1, further comprising a capacitor between the ground potential and each of the divided outputs of the voltage dividing means. 3. The switching device according to claim 1, further comprising a return switching device that is connected to the output terminal and one of the two power supplies and is turned on and off by an output of the trigger device. Staircase wave generation circuit.