JPH0555374A - Field programmable gate array program device - Google Patents

Abstract

PURPOSE:To enable a current defective FPGA product to be profitably used by a method wherein data concerning the inner block of a field programmable gate array found in a field are written in a memory block built in the FPGA. CONSTITUTION:When data concerning an inner block measured/found on a use site are written in a ROM built in an FPGA 11 by a write device 27, the separate data of the FPGA 11 are inputted into an FPGA program support device 21 first. Then, data (regarding an inner block) read out from the FPGA program support device 21 are sent to a write device 27, and the device 27 writes the data concerned in a ROM block. By this setup, an FPGA 11 urnusable due to deterioration failure with time or malfunction on a use site can be applicable to other uses, whereby it can be enhanced in useful life.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a field programmable gate array (FPGA = FIELD PROGRAMMABLE GAT).
FP at the field of use of an integrated circuit device (LSI) called E ARRAY, hereinafter referred to as FPGA)
The present invention relates to a programming device for programming a GA.

[0002]

2. Description of the Related Art Recently, among the types of LSIs, attention has been paid to LSIs in which a user can freely define (program) a circuit at a field of use (field) and change the definition of the circuit in the field. A field programmable gate array (FPG) is one of such LSIs.
A) ”.

An FPGA is constructed by regularly arranging a plurality of relatively large circuit blocks and wiring blocks on a chip. Inside the circuit block and wiring block, there are many devices that can be programmed to electrically connect or disconnect the circuit. By programming (defining) these devices, the user can connect the inside of the block and the connection between blocks. Can be programmed in the field (field of use). Devices using "fuses", "antifuses", "transistor switches", etc. have been put to practical use as devices that can be electrically connected or disconnected.

[0004]

Here, the above FPGA is used.
The problems peculiar to the above will be described in comparison with the case of manufacturing an LSI product other than the FPGA.

As is well known, industrial products generally have variations in product quality depending on the maturity of their manufacturing process. Post-manufacturing product testing is performed to check this quality variation, eliminate defective products, and rank products.

The LSI product test includes a basic function test,
There are various tests such as environmental resistance test and aging test, but here we focus only on the basic function test.
This basic function test indirectly checks with an electric signal whether the designed circuit pattern is accurately realized on the actual chip.

An electric signal is a combination of an input / output terminal and an input / output signal pattern for checking the designed function, and is called a "test input / output pattern". In this test, chips that do not produce the expected output for the input signal are rejected as defective products. Furthermore, even in the case of non-defective products, the degree of success of the process is different, and the degree of success is reflected in the above test result as "output signal delay time". This ranks the products.

Specifically, the "usable clock frequency" is determined according to the maximum guaranteed value of the delay time data of a certain chip. For example, 2MHz chip, 5MHz chip, 1
It will be ranked such as 0 MHz chips.

By the way, the maturity of the manufacturing process is particularly low for LSIs of the type in which new product development competition is intense and the product life of individual products is short. Therefore, particularly in such an LSI product, extremely large quality variation occurs. FPG
A is also one of such LSI products.

There is a device configuration shown in FIG. 3 as a device arrangement for performing automatic wiring for programming in the field of use in the FPGA. This device includes an FPGA program reading / writing device 103 having a mounting base on which an FPGA 101 is mounted, and an FPGA program reading / writing device 10.
And an FPGA program support device 105 which is electrically connected to 3 and which allocates (floor plans) the internal circuit blocks of the FPGA.

In the FPGA, there are the following problems regarding programs in the field of use (field), particularly circuit allocation.

In the conventional FPGA, there was no means for knowing the "performance of each internal logic circuit block" of the FPGA at the site of use. Therefore, when the circuit allocation (programming) is performed, the optimum program according to the “individual performance of each internal logic circuit block”, that is, the logic circuit block allocation (floor plan) cannot be executed. Since the optimum circuit allocation (programming) cannot be performed, it has been forced to use the over-specification (over-specification) of the FPGA as described below. It should be noted that “using FPGA over-specification” means that it is inevitable to use an FPGA product of a higher rank than the required rank of the circuit to be assigned (programmed).

Further, the FPGA has the following problems regarding the wiring allocation by the program at the use site (field). Generally, there are variations in the wiring delay time of "individual" LSI products, and the same applies to FPGAs. Furthermore, in FPGAs, there is variation in wiring delay time “for each internal block” even for the same product.

The user of the conventional FPGA cannot know the variation of the wiring delay time for each product and the variation for each internal block. That is, in the field program device of FPGA composed of a personal computer, etc.,
The "standard" delay time (maximum minimum guaranteed delay time) of the product A was estimated and displayed. This delay time display requires manual wiring (the user specifies the wiring route and switching device on the personal computer) partially because the software of the automatic wiring device described below is not perfect. The delay time is a criterion in that case.

Further, the FPGA automatic wiring device does not automatically wire by using the delay time of each product or each internal block, but the standard delay time (maximum and minimum guaranteed delay time).
The automatic wiring was performed using the “estimated value” of. The delay time estimation value is estimated on the “safe side” in comparison with the actual delay time of the FPGA, that is, both the maximum and minimum delay times are “larger” than actual.

Therefore, it is impossible to use the FPGA products that can be used if the optimum wiring corresponding to the actual delay time of each product is executed, and the FPGA products of the higher product ranks must be used. There was a problem. That is, the use of FPGA over-spec has been obliged. For example, I have to use 10MHz products for circuits that require 5MHz products.
Is a problem.

On the other hand, in the known technique, the internal block operation failure (failure) occurs while the FPGA is used in the field.
If this occurs, there is a problem that this FPGA is "discarded".

Although it is a defective product, it is not preferable in terms of resource saving and energy saving because it is produced by consuming a large amount of energy using a rare material. If the internal block malfunction (fault) is fatal or if many blocks are malfunctioning, disposal is unavoidable.

However, in the case of an FPGA, if a slight malfunction (fault) of several blocks at most is possible, it is possible to avoid the block and reprogram it for use. Further, if the failure is performance deterioration due to element deterioration, it can be diverted and used for an application in which low-level performance is required.

The present invention is an optimum F which is not over-spec.
The purpose is to enable the use of PGA products and expand the range of use of FPGAs with lower product ranks than before, and at the same time, to effectively use the current defective FPGA products. To do.

[0021]

According to the present invention, there is provided a programming device for programming a field programmable gate array having a built-in memory block for storing data relating to its own internal block, at the site of use, comprising:
There is provided a programming device for a field programmable gate array, comprising a writing means for writing data regarding an internal block of the field programmable gate array found in a field to a storage block built in the field programmable gate array itself.

In a preferred aspect of the present invention, the data relating to the internal block is preferably two terminal names of the field programmable gate array and maximum and minimum delay time values between the terminals.

In a preferred aspect of the present invention, it is preferable that the data regarding the internal block is a defective element name inside the internal block.

[0024]

The present invention provides a device that allows a user at the site of use to store "data relating to internal blocks of the FPGA itself" in a storage block such as a ROM or RAM. For this reason, the hardware for newly writing data on the internal block of the FPGA, that is, a device for writing the data on the internal block to the storage block, is newly provided to the conventional programming device, and the measurement or the discovery is made in the field of use (field). Data about the FPGA is written in the memory block of the FPGA itself, and it is read when the FPGA is diverted, so that the FPGA that has become unusable due to secular change in the field, occurrence of malfunction, etc. is diverted to other uses. This facilitates the operation and increases the useful life of the FPGA.

Here, "data relating to the internal block of the FPGA itself" means "usable clock frequency", "maximum minimum delay time value", "defective (or non-guaranteed) circuit block" for each internal circuit block. “Name (or position)” or “type (or name) of defective (or non-guaranteed) element circuit inside the block”. The internal block means, for example, a logic circuit block or a wiring block.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a field programmable gate array (FPGA) programming device according to the present invention will be specifically described with reference to the drawings.

FIG. 1 shows an example in which the FPGA 11 is mounted on the LSI 13, and further shows the basic structure of the FPGA 11 in an enlarged manner. In the FPGA 11, a programmable logic circuit block 15, a programmable wiring block 17, and a memory as an example of a storage block (built-in memory), that is, a ROM block 19 are arranged in a predetermined rule arrangement. A user can interconnect these logic circuit blocks 15 using the in-block logic of the programmable logic circuit block 15 and the programmable wiring block 17.

In the ROM block 19, for example, R
Test data on the internal blocks of the FPGA other than the OM block 19, that is, the programmable logic circuit block 15 and the programmable wiring block 17 is written. By the way, a so-called “FPGA structure with a built-in memory” in which the ROM block 19 is incorporated in a part of the circuit of the FPGA 11 is known, but the content (use) of the commonly known “built-in memory” is defined by a user program. The ROM block 19 is used for a built-in memory or for storing a state when the user's system is in operation.

The FPGA programming device according to the present invention has a configuration as shown in FIG. That is, the FPGA program support device 21 such as a personal computer equipped with the program software of the FPGA 11 and the FP
An FPGA program read / write device 25 having a mounting base 23 on which the GA 11 is mounted and connected, and having a function of programming a device for the programming, and an FPG.
It is mainly composed of a writing device 27 for writing data on an internal block measured or found at a use site in a ROM block built in A.

Further, the FPGA program support device 21
Is the defective portion found or actually measured in the field.
FPG using PGA program read / write device 25
In addition to writing to the ROM block 19 of A, an internal block can be prioritized by using the FPGA program basic specification data, and an operation that extracts a special limiting condition from the FPGA program basic specification data can be performed. .. Under the priority order and the limiting condition, the FPGA program reading / writing device 25 is used to allocate the logic circuit blocks of the FPGA or automatically wire the wiring blocks.

FPGA program read / write device 25
Is an FPGA program (program in the field)
Read / write device, which has only the function of reading and writing "data relating to the program" of the FPGA. The "data relating to the program" is the program itself, the rewriting prohibition setting data of the program, the reading prohibition setting data of the program, the setting data of the connection configuration of a plurality of FPGAs (a plurality of FPGA simultaneous program setting data), and the like.

Further, when the writing device 27 writes the data regarding the internal block measured / discovered at the use site in the ROM built in the FPGA, first, the FPGA individual data is input to the FPGA program support device 21, The writing device 2 writes the read data (data related to the internal block) from the FPGA program support device 21.
7, and the writing device 27 writes the data in the ROM block based on it.

The data written in the internal block is written by the writing device 27, and the arbitrary data related to the internal block found by the user in the field is stored in the FPGA.
It becomes possible to write in M.

In the conventional FPGA programming device, the FP
There was no hardware to read the data about the GA internal block. That is, the conventional hardware is a read / write device for assigning a program to the FPGA in the field (field), for example, circuit allocation, and is a device having only a function of reading and writing "data relating to the program" of the FPGA.

The following two examples are given as the data regarding the internal block. 1. FP measured using various measuring devices in the field
"Maximum and minimum delay time value" between two terminals of GA. 2. The "defective element (device) name of the internal block" found in the field due to a malfunction or the like while using the FPGA.

The above-mentioned delay time value 1 is an actual measurement value that reflects an increase in the delay time that occurs due to, for example, the secular change that generally occurs in LSI devices. For example, from the N0001 terminal to S0
When the minimum delay time to the 002 terminal is 20 and the maximum delay time is 25, the writing device 27 is written in the ROM block.
You can write "N0001, S0002,20,25" using.

By writing the deterioration of the FPGA performance due to the secular change or the like in the ROM as the actual measurement data of the delay time value, this data can be read out and used when it is diverted to a use with lower performance. It is possible and convenient when programming for diversion. The data should be recorded on paper and saved, and it should be possible to retrieve it when diverting it, but this cannot be adopted because management is complicated. for that reason,
It is better to write directly to the ROM block of the FPGA.

The defective element (device) names of the above-mentioned internal blocks are, for example, "circuit element name of internal logic circuit block" and "switching device name of internal wiring block". The former example is AND0 of 53 logic circuit blocks.
The AND circuit element of 001 and the OR circuit element of OR0002 are malfunctioning.
You can use 7 to write "53, AND0001 &OR0002".
An example of the latter is when 120 switching devices of 62 wiring blocks and 005 switching devices are malfunctioning. In this case, "62,1" is stored in the ROM block.
Just write "20 &005".

As described above, the "program data of the FPGA" allows the "arbitrary data regarding the internal block found by the user in the field" to be written and stored in the ROM of the FPGA and read out as needed for use in the program.

The value of the maximum and minimum wiring delay time between the individual blocks is the value actually measured in the measurement (test) at the time of manufacturing completion, and the value actually measured in the field is also written, so that the individual FPGA of the written FPGA is written. Product test data is extremely accurate because it reflects variations in the manufacturing process of individual products.

By the way, in the present invention, the present invention cannot be effectively implemented if "the ROM block itself has a defect". Therefore, in order to avoid such a situation, it is more preferable to manufacture only the ROM block by the established process technology because the manufacturing process is relatively simpler than that of the other blocks.

Regarding the manufacture of the FPGA of the present invention, the ROM block is incorporated at the design stage, and the RO block is manufactured at the manufacture stage.
It is possible to incorporate the M block in the same chip by a known ROM-embedded LSI design and manufacturing technology.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications and changes can be made within the scope of the gist of the present invention.

[0044]

As described above, in the FPGA programming device of the present invention, the FP measured or found in the field is used.
Data about the GA is written in the ROM of the FPGA itself, and by reading this when the FPGA is used, the FPGA that has become unusable due to aging deterioration in the field, occurrence of malfunction, etc. is diverted to other uses. This facilitates and increases the useful life of the FPGA.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a basic structure of a field programmable gate array (FPGA) according to the present invention.

FIG. 2 is a diagram showing an example of an FPGA programming device according to the present invention.

FIG. 3 is a diagram showing an example of a conventional FPGA programming device.

[Explanation of symbols]

11 FPGA (Field Programmable Gate Array) 13 LSI 15 Programmable Logic Circuit Block 17 Programmable Arrangement Block 19 ROM Block 21 FPGA Program Supporting Device 23 Mounting Platform 25 FPGA Program Reading / Writing Device 27 Writing Device

Claims (3)

[Claims] 1. A programming device for programming a field programmable gate array containing a storage block for storing data relating to its own internal block in a field of use, which relates to an internal block of a field programmable gate array found in a field. A programming device for a field programmable gate array, comprising a writing means for writing data to a storage block built in the field programmable gate array itself. 2. The programming device for a field programmable gate array according to claim 1, wherein the data regarding the internal block is a name of two terminals of the field programmable gate array and a maximum and minimum delay time value between the terminals. 3. The programming device for a field programmable gate array according to claim 1, wherein the data regarding the internal block is a defective element name inside the internal block.