JPH0555263A - One-dimensional channel carrier transistor - Google Patents

Abstract

PURPOSE:To reduce noises in a high frequency by a method wherein a one- dimensional electronic structure, which is formed on the side surface of a semi conductor having a serrate section, is used as the active layer if a FET. CONSTITUTION:An undoped GaAs layer 11 formed by a periodic multiple line having a serrate section structure is provided on a GaAs substrate 10. Moreover, an N-type AlGaAs layer 13 is provided in such a way as form a heterojunction between the layer 11 and the layer 13. Here, the layer 13 has an impurity region doped with a conductivity type impurity. Accordingly, a one-dimensional carrier region is formed along the line of a heterojunction interface having a serrate section. A gate electrode 20 is formed on the serrate structure from the side over the substrate to constitute a one-dimensional channel carrier transistor. Thereby, fluctuations in the passage path of a charge carrier can be suppressed in one-dimensional manner and channel carrier density is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-dimensional channel carrier transistor, and particularly to a one-dimensional channel carrier transistor suitable for use as an amplifier in a transmitter / receiver for satellite broadcasting, cellular radio, etc., which is required to have high frequency compatibility and low noise characteristics. The present invention relates to a channel carrier transistor.

[0002]

2. Description of the Related Art In Japan, since July 1987, DBS
The 24-hour television broadcasting by the (Direct Broadcasting Satellite Service) has started, and the demand for higher performance of the DBS receiving system is increasing. In addition, HEMT (High El
ectron Mobility Transistor) has led to a rapid increase in demand.

Actually, the gate length L _g = 0.25 to 0.3 μ
0.9dB in AlGaAs / GaAs HEMT at m level, AlGaAs / InGaAs Pseudomorph
icHEMT has an NF (noise figure) of 0.5 dB of 12
It has been achieved in the GHz band. For these, for example
Reference 1: The Third Asia Pacific Microwave Conference Proceedings, Tokyo, 19
1990, pp. 951-954 (The 3rd Asia-Pasific M
icrowave Conference Proceedings, Tokyo, 1990, pp.95
1-954) or Ref. 2: Extented Abstract of the Twenty First Conference
On Solid State Devices and Materials, Tokyo, 1989, pp. 285-288 (Exten
dedAbstract of the 21st Conference on Solid State
Devices and Materials, Tokyo, 1989, pp.285-288).

By the way, in order to miniaturize antennas and spread wireless communication systems for personal devices, FETs (field-effect transistors) with lower power consumption and excellent noise index are required. As for the improvement in optimization of the gate structure and the like, the technology is already in a saturated state, and it is becoming more difficult to reduce NF dramatically.

On the other hand, a one-dimensional electron gas (1DEG) system is
The idea of 1DEG-FET to be used for the active layer of ET has been proposed, and its device characteristics are, for example, Document 3: Eye
EE, IDM, 1989,
89-125, pp. 5.8.1-5.8.4 (IEEE, IE
DM, 1989, 89-125, pp.5.8.1-5.8.4).

An element plan view and a sectional view of this one-dimensional FET are shown in FIGS. 2 (a) and 2 (b). Normal HEMT structure is M
It is formed by a technique such as BE (molecular beam epitaxy) and is removed by mesa etching leaving a fine line region 30 having a width of about 0.15 μm (31 part), one-dimensional fine lines are arranged, and a gate length L _{g of} 0.3 μm level is formed. To achieve. A gate electrode 20 and source / drain electrodes 21 and 22 are formed respectively.

N + AlGaAs 13, i-AlGaAs
A two-dimensional electron gas (2DEG) is formed at the interface between the (undoped layer) 12 and the undoped i-GaAs layer, and a line width of 0.
The one-dimensional area (very thin linear area) 30 of 15 μm
Multiple layers are formed with a dead space 31 having a line width of 0.2 μm removed by mesa etching. A trial production of a 1DEG-FET having such a structure shows a one-dimensional effect predicted from a simple theory. Reference 4: Japanese Journal of Applied Physics, Vol. 19, 198
Year 0, pages L735-L738 (Japanese Journal of
Applied Physics, Vol. 19, 1980, pp. L735-L738). That is, the effect of increasing the mobility in the low electric field region was not found even at an extremely low temperature of 4K. Also, at 12 GHz, the source / drain current I _DS = 10 m
The NF at A was also 1.5 dB, which was only a bad value as compared with the normal HEMT structure.

Further, a HEMT having a deep recess structure is generally used, for example, Reference 5: JP-A-62-20071.
In the structure shown in Japanese Patent Laid-Open No. 1 or the element cross-sectional structure disclosed in Document 1, the transistor width w is 200 μm.
Then, although the NF when I _Ds = 10 mA can be realized at 0.8 to 1.0 dB, the 1DEG-FET shown in FIG.
Transistor width w is 60 to flow _Ds of 10 mA.
0 μm was required.

[0009]

As described above, the reason why the required transistor width w becomes three times larger is that the 1DEG-F
In the ET, (1) there is a dead space 31 in which no current flows (width w _{1 to} 0.2 μm), (2) a depletion layer due to the gate electrode metal 20 on both sides gathering at the mesa step, so that the one-dimensional electron system Lithographic width (w ₀ ~
It is considered that the width actually more effective than 0.15 μm is estimated to be about 70% of the width of the one-dimensional thin line described above.

For these reasons, simply arranging the one-dimensional regions simply changes one GaAs wafer to a normal HE.
When 10,000 FETs can be taken with MT structure, 1DEG-F
With ET, only about 4000 pieces can be obtained, which causes a significant increase in cost and causes a problem in production technology such that the size of the FET becomes several times larger.

As a result of analyzing the difference in noise characteristics between HEMT and MESFET, the inventors found a general theory described below, which is different from the conventional hypothesis. First, the noise generated in a field-effect transistor is the classical electron streamline in which electrons flow from the source to the drain (streamline showing the flow of electrons when regarded as a simple fluid: easily defined from the analogy of fluid dynamics). Due to fluctuations and turbulence due to thermal motion from. This is called intrinsic noise here. On the other hand, the noise generated by disturbing the electron flow due to the peculiar cause of the GaAs material, such as the defect in the crystal and the surface level between the source and the gate, is generated by GaAs MESFET
It is a noise factor common to sHEMTs and can be called, so to speak, parasitic noise. Further, this parasitic noise also has a portion derived from the source gate resistance Rsg and the gate resistance Rg.

The difference in noise between HEMT and GaAs MESFET is due to the fact that, in the case of MESFET, the three-dimensional fluctuation from the classical electron streamlines is essentially two-dimensional in the case of HEMT. ing.

In the MESFET, the active layer (channel) is three-dimensional (bulk-like), so that the electrons can three-dimensionally fluctuate around the electron streamline. That is, the fluctuations from the classical electron streamlines are made three-dimensional. On the other hand, in the HEMT, since the electrons are two-dimensionally confined in the AlGaAs / GaAs interface, the movement direction of the electrons is mainly limited. Therefore, the classical electron streamlines are also two-dimensional, the fluctuations in the direction perpendicular to the above heterointerface are suppressed, and the fluctuations from the classical electron streamlines are only two-dimensional within the plane of the heterointerface. Will end up.

Since the intrinsic noise is given as a logarithmic quantity with respect to the degree of freedom of fluctuation, assuming that the noise in the three-dimensional direction is 1, the noise in the two-dimensional direction is 2/3. This is because the degree of freedom of three-dimensional fluctuation is proportional to 10 3/3, and the degree of freedom of two-dimensional fluctuation is proportional to 10 2/3.

By the way, noise at a high frequency is generated by scattering of electrons and heat generation. In a HEMT in which the degree of freedom of electron scattering is reduced from three-dimensional to two-dimensional by using a two-dimensional channel in the active layer, this heat generation is suppressed and noise can be reduced.

FIG. 4A is a plan view of an ordinary HEMT structure element. The noise generation mechanism will be further described with reference to this drawing. The electrons emitted from one point 60 on the source electrode 21 reach the region of the gate electrode 20 while drift-diffusing by the electric field. By the way, the electrons emitted from the source are accelerated by the electric field in the gate direction (x direction), but do not exist in the direction parallel to the gate (y direction), and therefore are dominated by diffusion only. .. 2D
Assuming that the diffusion coefficient of EG is D and the arrival time to the gate electrode is τ _s , the position where the electron starting from the point 60 on the source 21 moves in the direction of the gate 20 and arrives is the random electron path 51. The average arrival point of the electron is in any one of the regions in the source side gate electrode, which is expanded by l _s from the point 64 obtained by moving the point 60 in the x direction.

Here, the diffusion coefficient D is given by the equation 1, and the diffusion distance l _s is given by the equation 2.

D = kTμ / q (Equation 1) where k is Boltzmann's constant, T is absolute temperature, μ is electron mobility, and q is elementary charge.

L _s = √ (Dτ _s ) ... (Equation 2) Now, the mobility of 2DEG μ = 8,000 cm ² / V ·
s, kT = 24.8 meV (room temperature), D = 19
It becomes 8.4 cm ² / V · s. 1 psec as τ _s (=
10 ^-12 sec) as a typical value, l _s = 14
It becomes about 0 nm.

In the case of GaAs MESFET, the diffusion region is three-dimensional (three-dimensional), whereas in the case of HEMT, it is two-dimensional (planar), so that the intrinsic noise is significantly small. As for the electrons reaching the point 61 of the gate electrode region, the random path 50 of the electrons, the electron spread l at the end of the drain side gate electrode, and the lateral diffusions 72 and 73 are also the same as in the formulas 1 and 2. Can be evaluated.

The inventors of the present invention have come up with the idea that the noise can be further reduced by using the one-dimensional electron system for the FET, based on the discovery of the noise. That is, according to the above-mentioned examination, the degree of freedom of the one-dimensional fluctuation is proportional to the 1/3 power of 10 and, in principle, becomes 1/2 the intrinsic noise of the HEMT system using 2DEG (two-dimensional electron gas). ..

If a structure capable of suppressing the lateral diffusion of the electrons can be devised, it becomes possible to significantly suppress the generation of noise at high frequencies.

FIG. 4B is a conceptual diagram of a plane structure in which the lateral diffusion of electrons is suppressed. That is, the width w ₀
Multiple one-dimensional electron paths are formed. Electrons starting from a point 62 on the source make a random motion 52 and reach directly below the gate 20. At this time, the random electron path is confined only within the one-dimensional structure of the width w ₀ , and it is extremely rare to move to another path, so that the fluctuation can be greatly reduced. The same applies to the other electrons 63 that have reached the source-side gate end. At this time, at least the scattering at the side wall of the one-dimensional structure with the width w ₀ must be such that the inelastic scattering that loses energy is suppressed as much as possible.

Next, the conventional 1DEG-FET (see, for example, FIG.
In the cases of (a) and (b)), why high frequency low noise
The effects could not be observed, and the causes are as follows.

(1) Increasing degree of scattering with decreasing Fermi wave number In the case of the 1DEG structure using such a method, 1D
The EG electron density decreases. Compared with the 2DEG structure, this has a problem that the Fermi wave number is smaller, electrons are more likely to be scattered in the one-dimensional thin line, noise at high frequencies does not decrease, and the fundamental amount of current decreases. There is. Therefore, the 1DE produced in this way
When the G-system is applied to the FET, the performance of the G-system is lower than that of the HEMT. In addition, in the case of the structure of FIG. 3, since the depletion layer is extended from both sides of the mesa step surface by the Schottky gate electrode 20 in the one-dimensional region, the effective one-dimensional region width is further reduced and the current amount is also increased. The problem of falling further occurs, and FET
Performance has been reduced.

(2) Increasing inelastic scattering on the side surface of the 1DEG channel Further, in the case of this conventional example, a simple mesa etching is performed by using a lithography technique as a manufacturing means of the 1DEG line to make the side surface of the 1DEG channel the gate electrode. Since the structure is such that it is wrapped, the non-uniformity of the potential barrier on the side surface of the 1DEG channel and the inelastic scattering due to impurities and defects mixed during the formation of the thin line are increased to deteriorate the noise characteristic at high frequencies.

(3) Increasing the parasitic resistance Rsg As a means usually used for suppressing the parasitic resistance, a low resistance n + GaAs having a sheet resistance of 10 to 50 Ωcm ^-2 is used.
There is a method of sandwiching the layer between the source and the drain, for example.
However, in the prototype FET of FIG. 2, no means for reducing such parasitic resistance is used, and it is considered that the superiority in noise characteristics was not exhibited.

By solving the above-mentioned problems,
The high-frequency low noise characteristic derived from one-dimensionality is found.

[0029]

In order to solve the above technical problems, the present invention has the following features. That is, according to one aspect of the present invention, a semiconductor region for forming a flow of charge carriers therein, a control means for controlling the flow of the charge carriers, and a pair for supplying the charge carriers. Electrodes for providing a substantially one-dimensional energy potential to the charge carriers and confining the charge carriers in a direction intersecting the one-dimensional direction. A one-dimensional channel carrier transistor is provided that provides a type energy potential. Here, the key-shaped energy potential is meant to exclude the case where the shape of the energy potential changes gently. The charge carrier refers to an electron existing in the conduction band of the semiconductor or a hole existing in the valence band. The flow of these charge carriers forms a channel, which is in ohmic contact with the pair of electrodes.
The control means may be of the type that controls the flow of charge carriers, for example by applying an electric field to a well known channel.

According to a limited aspect of the invention, the semiconductor region comprises first and second semiconductor regions, which induce the charge carriers on the basis of the energy difference at the energy band edges of these semiconductor regions. Thus provided is a one-dimensional channel carrier transistor. This type of transistor is commonly referred to as a HEMT. While the conventional HEMT uses a two-dimensional carrier gas, the device according to the present invention uses a one-dimensional carrier gas. The second semiconductor region has an impurity region doped with a conductivity type impurity (donor or acceptor), and charge carriers generated by the impurity region exist in the first semiconductor. This is based on the difference in band edge energy between the first semiconductor region and the second semiconductor region. As an example of a specific material combination of the first semiconductor / second semiconductor region, GaAs / AlG is used.
aAs, InGaAs / AlGaAs, InGaAs /
Examples include GaAs and InGaAs / InAlAs.

According to another limited aspect of the invention,
A one-dimensional channel carrier transistor having a plurality of the one-dimensional potentials is provided in the semiconductor region.
A plurality of one-dimensional potentials are formed along each other and electrically coupled with the pair of electrodes.

According to a further limited aspect of the present invention, there is provided a one-dimensional channel carrier transistor in which these one-dimensional potentials are periodically arranged in a direction intersecting with the one-dimensional direction.

According to another aspect of the present invention, the degree of freedom of diffusion (fluctuation) of charge carriers flowing in the channel is substantially 1.
An active region having a dimensionally limited potential barrier; control means for controlling the flow of the charge carriers;
A one-dimensional channel carrier transistor is provided having a pair of electrodes for supplying the charge carriers to the active region, the potential barrier having a bend for confining the charge carriers. Here, the “bend” refers to a structure in which two barrier surfaces (planes) provided by the potential barrier intersect each other, and the charge carriers are in the vicinity of a substantially triangular region (potential) formed by these barrier surfaces. Trapped outside the barrier). Examples of the formation of such a bend include a potential barrier having a triangular wave-shaped cross section, a trapezoidal wave-shaped one, and a rectangular wave-shaped one. On the contrary, as an example in which no bend is formed, there is a case where the cross-sectional shape of the potential barrier is a gentle sin curve. In short, when the cross-sectional shape of the potential barrier is schematically represented in the XY coordinate system, the coordinates at which the differential coefficient dY / dX representing the inclination is substantially discontinuous is the bending position.

The present invention will be further described with reference to the drawings.
The present invention provides a transistor structure such as an FET, which can take advantage of the characteristics of 1DEG (1-Dimensional Electron Gas, or 1DHG: 1-Dimensional Hole Gas) system, for example, the one-dimensional structure of the structure shown in FIGS. A channel carrier transistor is disclosed. That is, the one-dimensional channel carrier transistor of the present invention has a first semiconductor region 11 formed by periodic multiple lines having a saw-tooth (triangular tooth) cross-sectional structure and an electron affinity smaller than that of the first semiconductor region. (Or, if the charge carrier is a hole, the sum of the electron affinity and the forbidden band width is large.) The second semiconductor region 13 is provided so as to form a heterojunction with the first semiconductor region. The second semiconductor region 13 has an impurity region doped with a conductive impurity, and a one-dimensional carrier region is formed along the line of the heterojunction interface having the sawtooth (triangular) cross section. In addition, an electrode controlling the one-dimensional carrier and a pair of electrodes ohmic-connected to the one-dimensional carrier are formed.

The inventors analyzed the effect of a heterojunction interface having a sawtooth cross section as shown in FIG. Such a serrated shape of the heterojunction interface provides a structure in which the curvature of the heterojunction interface is periodically modulated, and is an excellent structure that solves the problem of reduction in the amount of current, which is a drawback of the conventional 1DEG structure. I found that. This effect will be described in action. If the length along one saw tooth as shown in FIG. 1B is λ and the inclination angle of the saw tooth with respect to the base is θ, the effective width of one saw tooth is λco
It becomes sθ. When a sawtooth structure made of undoped GaAs11 / n-AlGaAs13 is formed on the GaAs substrate 10 having a grating line of the above width so that the cross section has a sawtooth structure, the undoped GaAs layer 1
Two-dimensional electron gas is formed on the sawtooth side surface (GaAs side) in the vicinity of the heterojunction interface between the 1 and n-AlGaAs layers 13. The gate electrode 20 is formed on the sawtooth structure from above to form a one-dimensional channel carrier transistor.

[0036]

First, taking an example in which the curvature of the heterojunction interface is modulated in a sawtooth shape, n-AlGa is compared with the case of the conventional (2DEG) structure in which the curvature of the heterojunction interface is constant.
How the depletion layer extending in the As layer changes will be described.

2 (a) and 2 (b) are respectively shown in FIG.
It is an energy diagram along line segment A'A and line segment B'B of (b). In the figure, the height of the Schottky barrier between the n-AlGaAs layer 13 and the gate electrode 20 is V
_A'0 , V _B'0 , and the thickness of the depletion layer 15 generated by this barrier are represented by d _A'0 , d _B'0 . Further, the band gaps between the n-type AlGaAs layer 13 and the undoped GaAs layer 11 are V _A0 and V _B0 , and the thickness of the depletion layer generated by this band gap is represented by d _A0 and d _B0 . As a result of the analysis, the height of the barrier satisfies the following condition: V _A'0 > V _{2D '} > V _B'0 > V _B0 > V _2D > V _A0 ( _Equation 3). Here, V _{2D '} and V _2D represent the Schottky barrier and the band gap in the case where the curvature of the heterojunction interface is constant, that is, in the case of the 2DEG structure in which no bending exists. When the energy barrier V is used, the thickness d of the depletion layer can be expressed as d = √ (2ε _s V / qN _D ) ... (Equation 4). Here, ε _s is the dielectric constant of AlGaAs, q is the charge of electrons, and N _D is the impurity concentration of the n-AlGaAs layer. Since the thickness of the depletion layer is determined by the size of the energy gap according to Formula 4, the formula corresponding to Formula 3 is established. That is, d _A'0 > d _{2D '} > d _B'0 > d _B0 > d _2D > d _A0 (Equation 5) In this equation, d _2D' and d _2D have a constant curvature at the heterojunction interface. In the case of, that is, in the case of the 2DEG structure in which no bending exists, the thickness of the depletion layer generated by the Schottky barrier and the band gap is shown.

Considering the case of application to the FET, n-AlGaAs is controlled so that the electrons accumulated in the GaAs layer 11 can be controlled most efficiently by the negative gate bias.
It is necessary to determine the layer thickness, which is n−A
Maximum film thickness d where no charge neutral region appears in the 1GaAs layer
_It can be realized by _A'A and _dB'B . These film thicknesses can be represented by the sum of the above-mentioned depletion layers. That is, d _A'A = d _A'0 + d _A0 ... ( _Equation 6) d _B'B = d _B'0 + d _B0 ... ( _Equation 7) According to the condition of Expression 3, the following conditions are satisfied for the thickness of the depletion layer.

D _A′0 −d _B′0 > d _B0 −d _A0 ... ( _Equation 8) From Equation 8, the following equation holds between Equation 6 and Equation 7.

D _A'A > d _B'B ( _Equation 9) Therefore, in order to control the FET efficiently by the gate voltage, the film thickness of the n-AlGaAs layer should be d _B'B . It must be formed with a thickness or less.

Next, when the present invention is applied to HEMT,
The effect exerted on the electrons accumulated on the GaAs layer 11 side will be described. As described above, the periodic curvature modulation (bending) of the heterojunction interface causes the depth of the depletion layer 15 extending in the n-AlGaAs layer to be shallow near the point A in FIG.
A deepening effect was obtained near point B (or point C) (Equation 3). Due to the effect of this curvature modulation, the electrons that should have accumulated in the deep region of the depletion layer move to the shallow region of the depletion layer. Therefore, the two-dimensional electron gas is not formed along the side surface of the sawteeth, but has a non-uniform distribution in which a large amount is accumulated near the point A and a small amount is accumulated near the point B. On the other hand, when the present invention is applied to, for example, a MESFET, one-dimensional confinement of charge carriers due to bending can be expected, but the position is often non-uniform accumulating near points B or C in FIG. 1B. It is expected to be distributed.

Now, returning to HEMT, the doping concentration ND of the n-AlGaAs layer is 1.0 × 10 ¹⁸ cm ^-3 and λ = 1.
When set to 200Å, the electron density distribution of one saw tooth is as shown in FIG. That is, the high-density electron distribution spreads in the upward convex portion (near point A) as viewed from the GaAs side, and the low-density electron distribution spreads in the downward convex portion (near point B). The difference reaches about one digit, and the high-density electron distribution generated in the convex portion is 2.5 times higher than the peak density of 2DEG. Such an effect of increasing the electron density is a new effect due to bending, which never occurs in the conventional 1DEG forming method of confining 2DEG in a narrow region as shown in FIG.

Further, the inventors have evaluated λ, which is the optimum length for the formation of 1DEG and its application to FET, making the most of the effect of the density of electron density. For the explanation, a local sheet density n _local (x) and an averaged sheet density n _av thereof are introduced below.

N _local (x) = ∫n (x, y) dy (Equation 10) n _av = ∫n _local (x) dx (Equation 11) where y-axis, x The axes are both starting from point A, the y-axis is perpendicular to the line segment BC, and the x-axis is in the direction of the line segment AC (see FIG. 1 (b)). FIG. 6 shows the x dependence of n _lonal (x) under the condition that θ = 45 ° is fixed.
= 1200, 2000, 4000 [Å] are shown. Further, in FIG. 7, the λ dependence of n _av is θ = 3.
The result of having investigated about 0, 45, 60 [degree] is shown. Figure 6
7 and FIG. 7 show the sheet density n _{2D of} 2DEG as a unit. The peak value (x = 0) of n _local (x) hardly changes even if λ is changed, and what is important is to realize a distribution that is about 2.5 times as dense as n _2D. is there. As λ increases, n _local (x) / n _av shows that the flat region expands, that is, the region having 2DEG-like behavior becomes longer, and therefore n _av / n _2D
Is the geometric effect of the curvature modulation of the interface, 1 / cos θ
It approaches (= √2). On the contrary, when λ becomes small, the region where the 2DEG-like effect appears is excluded,
As in the case of λ = 1200 Å in FIG. 5A, it becomes extremely steep and the one-dimensionality becomes remarkable.

Further, in order to treat this structure as a channel of 1DEG-FET and improve the performance of 2DEG-FET or higher, n _av must have a value of n _2D or higher.
That is, n _av ≧ n _2D ··· (Equation 12) Therefore, from the above analysis results, for example, when θ = 45 °, 1DEG is formed, and the condition for obtaining a current value similar to that of the conventional 2DEG-FET is We can conclude that it is about 850Å.

Thus, by using the 1DEG structure by the effect of periodic curvature modulation of the heterojunction interface, it is possible to solve the problem (1) that the degree of electron scattering increases with the decrease in Fermi wave number described in the problem. Furthermore, since this structure is surrounded by the n-AlGaAs layer, inelastic scattering on the side wall surface is suppressed, and the problem (2) can be solved. Further, by utilizing the high-density effect, it is possible to solve a production problem that a large current can be taken with the same transistor width as that of the HEMT even though it is 1DEG. Only by using this 1DEG structure, a transistor having excellent noise characteristics at high frequencies can be manufactured.

[0047]

EXAMPLES Example 1 The present invention will be described in more detail by way of examples. 22 is a perspective view showing a basic configuration when the one-dimensional channel carrier transistor according to the present invention is applied to a 1DEG-FET, FIG. 1 (a) is its plan view, and FIG. 1 (b) is O- in FIG. It is a O'sectional view. In FIG. 1A, the source electrode and the drain electrode are located on the front and back of the paper, but they are omitted in the figure and only the portion corresponding to the gate electrode 20 is shown. In FIG. 22, a first semiconductor region 11 and a second semiconductor region 13 are arranged in an active region formed on a substrate 10, and a flow (channel) of charge carriers is formed in this first semiconductor region 11. It A pair of electrodes (source 21, drain 22) for supplying charge carriers to the channel and a means for controlling the flow of charge carriers, for example an electrode for applying an electric field (gate 20) are well known methods. It is arranged by. In the figure, an n + layer 19 (Ga) is formed under each electrode of the source 21 and the drain 22 to ensure good electrical connection between the channel and each electrode.
As, etc.) are provided. Further, the impurity diffusion region 12 is provided to make ohmic contact.

A 10 nm thick SiO ₂ film is formed on the semi-insulating GaAs (100 plane) substrate 10 by CVD. Then, the SiO ₂ film is formed by using phase shift lithography.
Stripes are left at intervals of 60 nm. In addition, sulfuric acid (H ₂ S
Wet etching of O ₄ : H ₂ O ₂ : H ₂ O = 1: 8: 40) is performed for 15 seconds. With this (11-1)
(Here, 1 ￣ represents the inverse of 1.), (1
11) A saw-tooth substrate having θ = 55 ° in which the surfaces appear and are aligned in a straight line is completed. The intersecting portion of these two surfaces constitutes the bending or key shape referred to in the present invention.

The fluctuation width of the line formed by using the lithography technique described in the conventional example is determined by the substantial fluctuation of the lithography. However, in the method of selective etching using the plane orientation as in Example 1, a crystal plane is exposed by overetching, so there is no problem of variation in one-dimensional lines due to lithography. Therefore, the above-mentioned problem (2) can be solved. Further, this angle forms a structure in which the sawtooth shape is sharper than in the case of θ = 45 ° described in the above operation, and electrons tend to be densely accumulated as shown in FIG. 7. Generally, θ can be set between 20 ° and 80 °.

Next, after cleaning the substrate 10, the undoped GaAs layer 11 is formed to a thickness of 5 by MOCVD (metal organic thermal decomposition).
It was grown to 0 nm. The growth temperature at this time is a low temperature of 650 ° C., and the partial pressure of AsH ₃ is high. Next, the crystal growth temperature was raised to 800 ° C. and n containing 1 × 10 ¹⁸ cm ^{−3 of} Si was added.
-Al _X Ga _1-X As layer (x = 0.3) 13 was 40nm growth. At this time, the n-Al _x Ga ₁ -x As layer 13 and the GaA
An electron storage layer is formed at the hetero interface with the s layer 11. Further, an n + GaAs layer containing Si at 2 × 10 ¹⁸ cm ⁻³ is formed to a thickness of 160 nm (this can solve the problem (3)), and thereafter, the gate electrode and the source / drain electrode form a normal HEMT. It is made in the same manner as when performing. In addition, undoped Al is formed on the n-AlGaAs layer 13.
The structure for forming a GaAs layer with a thickness of 10 to 15 nm to improve the gate breakdown voltage is also effective as in the normal 2DET-FET structure. Source and drain electrodes are formed by a known method, and a gate electrode 20 is provided to complete the device.

The transistor width w on the plane of the device of the present invention constituted by the above steps is 200 μm, the gate length L _g is 0.25 μm, and the distance L _sg between the source electrode and the gate electrode is 1.5 μm.

FIG. 8 shows the measurement results of the noise figure NF and the gain G _a with respect to the drain current I _DS at this time in comparison with the conventional FET. As a result of the multidimensional (1666) channels one-dimensionalized, a remarkable improvement in characteristics is achieved.

FIG. 9 shows the source / drain voltage V _SD = 2.0V
In the graph showing the dependency of the source / drain current I _{DS on} the gate voltage Vg in the saturation region at the time of, the 1DEG structure has an advantage that a sharp curve as shown in the drawing is drawn as compared with the 2DEG structure. This is because the convex portion below the GaAs layer has a lower electron density than the other portions, and thus electrons are easily rejected.
Therefore, when the gate voltage is negatively applied to reduce the electron density, pinch-off occurs first from the downward convex portion, then the pinch-off spreads toward the upward convex portion, and finally the electron density The situation arises of reaching the highest part. This is an effect peculiar to the bent heterojunction interface structure that cannot realize the conventional 2DEG structure in which the uniformity of the electron density is maintained, but realizes the non-uniform electron density distribution. For this reason, the transconductance gm can be made about twice as large as that of a normal 2DEG-FET in a wide gate voltage Vg range.

Further, a structure in which the channel layer 11 and the carrier supply layer 13 of the above embodiment are reversed is also possible (FIG. 1).
0).

[Second Embodiment] FIG. 11 shows a second embodiment of the present invention.
1 shows a sectional view of a 1DEG-FET according to FIG. In the 1DEG-FET according to this embodiment, an undoped Al _Z Ga _1-Z As layer 16 (z =) is formed on a GaAs substrate 10 formed on saw teeth.
It has the same structure as the 1DEG-FET according to the example 1 except that 0.3) was grown to a thickness of 30 nm by the MOCVD method. According to this Example 2, undoped Al
_{The Z} Ga ₁ -Z As layer 16 plays a role as a barrier layer of the undoped GaAs layer 11 which is a channel layer of 1DEG, and makes the one-dimensional property more apparent. Therefore, the noise shown in FIG. 8 is further reduced by using the structure of the second embodiment.

In terms of crystal growth technology, AlGaA containing Al, which is more difficult to diffuse than Ga, is first formed on the GaAs substrate on the sawtooth.
There is also an advantage that the degree of freedom of the crystal structure is increased by crystallizing a desired structure after the s-layer 16 is conformally grown.

[Embodiment 3] FIGS. 12, 13 and 14
[FIG. 8] A sectional view of a 1DEG-FET according to a third embodiment of the present invention. The 1DEG-FET structure according to the third embodiment has the same structure as the 1DEG-FET according to the first embodiment except for the growth method of the Al _Y Ga _{1 -Y} As layer 13 of FIG. That is, in FIG. 12, the Al _Z Ga _1-Z As layer 16 (z =
The layer 18 in which Si is grown to a thickness of about a monoatomic layer when it is grown (0.3) is called a δ-doped layer in the case of one atomic layer, but the number of monolayers is not limited to one and may be several monolayers. Absent)
To form. Making the impurity doping as thin as a monoatomic layer has the advantage that the density of electrons accumulated in the undoped GaAs layer 11 can be increased. When applied to a conventional 2DEG structure, this doping density causes an approximately double increase in sheet density.

Therefore, when the effect of the monatomic doped layer 18 is applied to the periodic curvature modulation structure of the heterojunction interface according to the present invention, in Example 1, the sheet density n _{2D of} 2DEG is about 2.5 times higher. The electron density, which was the density, is at least twice as high. That is, high density electrons of 5.0 × 1.0 ¹² cm ⁻² can be obtained in the upward convex portion, and a high-performance 1DEG-FET can be manufactured.

Further, the ratio of the Al _Z Ga _{1 -Z} As layer 16 is z.
= 0.5 and crystal growth is performed, Al _Z Ga _1-Z As
The layer begins to grow first in the valley. After that, by growing the δ-doped layer 18, 1DE as shown in FIG.
The present invention may be applied to the G-FET structure.

The present invention may be applied to the 1DEG-FET structure as shown in FIG. Since this structure is characterized in that the downward convex portion is thin, it has an advantage that the film thickness setting of the depletion layer can be easily controlled.

[Embodiment 4] FIG. 15 is a sectional view of a 1DEG-FET according to still another embodiment of the present invention. The 1DEG-FET structure according to this embodiment has the same structure as the 1DEG-FET according to Embodiment 1 except for the structure of the GaAs layer 11. That is, the temperature for growing the GaAs layer 11 is set to 800 ° C., which is higher than that in the first embodiment, and the AsH ₃ pressure is set to the atmospheric pressure for normal crystal growth. Under such a condition, the Ga atoms are easily diffused by applying thermal energy. Using this property,
Ga atoms that were supposed to accumulate in the upward convex portion under the conditions of Example 1 can be moved to the downward convex portion in the present Example. Therefore, as shown in FIG. 15, a structure in which the thickness of the GaAs layer 11 is periodically different can be realized. In the growth of the n-AlGaAs layer 13, since the heavy Al atoms suppress the diffusion of Ga atoms, uniform crystal growth is performed again.

According to this embodiment, the thickness of the n-AlGaAs layer 13 is thick in the convex portion on the GaAs layer 11,
The part that is convex downward is thin. Therefore, the effect of rejecting electrons by the negative application of the gate voltage as described in Example 1 becomes more remarkable in the portion where the electron density of the downward convex is thin. The curve shown by the broken line in FIG. 9 is data using the structure of Example 4.

In addition, the GaAs layer 11 and n-A of the above embodiment are used.
A structure in which the lGaAs layer 13 is reversed is also possible (FIG. 1).
6).

[Embodiment 5] FIG. 17 is a sectional view of a 1DEG-FET according to still another embodiment of the present invention. In the 1DEG-FET structure according to this embodiment, an undoped Al _Y Ga _1-Y As layer 16 (Y = 0.3) is grown to a thickness of 30 nm on the GaAs substrate 10 formed on the sawtooth by the MOCVD method. 1DEG-FET according to Example 4
It has the same configuration as. According to the fifth embodiment, the undoped Al _Y Ga _{1 -Y} As layer 16 plays a role as a barrier of the undoped GaAs layer 11 which is the channel layer of 1DEG, and makes the one-dimensional property more apparent. Therefore, by using the structure of this embodiment, there is an advantage that the noise shown in FIG. 8 is further reduced.

[Embodiment 6] FIGS. 18, 19 and 20.
FIG. 11 is a sectional view of a 1DEG-FET according to still another embodiment of the present invention. The 1DEG-FET structure according to this embodiment has the carrier supply layer Al _Y Ga _{1 -Y} A in FIG.
1DEG-F according to Example 4 except for the method of growing the s layer 13
It has the same structure as ET. The method of growing the δ-doped layer is the same as that of the third embodiment. This has an advantage that the electron density accumulated in the undoped GaAs layer 11 can be increased similarly to the third embodiment.

Therefore, according to the sixth embodiment, the advantage that the noise can be further reduced is obtained as in the third embodiment.

Furthermore, in the growth of the Al _Z Ga ₁ -Z As layer 16, z = 0.5 was set and the 1DEG-FET shown in FIG.
It is also possible to apply the present invention to the structure.

The present invention may be applied to the 1DEG-FET structure shown in FIG. This structure has an advantage of further increasing the effect of the present invention that high-density electrons are accumulated in the convex portion upward because the single-electron layer doping is grown only in the convex portion relatively upward.

[Embodiment 7] A 1DEG-FET structure in which the present invention is applied to the structure described below may be used. FIG. 21 shows a sectional view of the 1DEG-FET structure. Semi-insulating Ga
After cleaning the As (100 plane) 10, an undoped GaAs layer 14 was grown to 0.5 μm by the MOCVD method. Next, the surface of the sawtooth substrate is treated with H ₂ plasma or HC.
2 × 10 ¹⁸ cm ^-3 after cleaning with l gas
N-Al _X Ga _1-X As (x = 0.3) 13 contained in 4
0 nm is formed. Other than that, the same structure is manufactured by using the same method as that of the first embodiment.

In the first to seventh embodiments described above, the semiconductor material is GaAs11 of the channel layer.
Can also be replaced by In _X Ga _1-X As having a strained layer. This does not replace the conventional Pseudomorphic HEMT. However, at this time, the maximum film thickness that can withstand the strain corresponding to the In composition x exists, as in the prior art.

Further, it is also possible to form a lattice-matched InGaAs / InAlAs heterojunction on the InP substrate instead of the GaAs substrate to form a higher performance HEMT.

[0072]

According to the present invention, the one-dimensional electronic structure formed on the side surface of the semiconductor having a sawtooth-shaped cross section is used as the active layer of the FET. Therefore, (1) a low noise characteristic utilizing the characteristics of the one-dimensional electronic system is obtained. (2) The heterojunction interface structure in which the curvature is periodically modulated in a sawtooth (triangular tooth) shape causes the density of the electron to vary, and the dark portion is the peak density of the channel carrier (for example, 2DEG) of the conventional device. The effect is more than doubled. 1DE for areas with high electron density
By using the G channel, the conventional 1DEG
It is possible to overcome the essential problem of the reduction of the amount of current, which is a drawback of the channel fabrication method, and it is possible to overcome the conventional high performance HEM.
Even if compared with T, 1DEG-FET can exhibit the same performance.

[Brief description of drawings]

FIG. 1 is a perspective view and a cross-sectional view showing an embodiment of a one-dimensional channel carrier transistor of the present invention.

FIG. 2 is a band diagram of the device shown in FIG.

FIG. 3 is a plan view and a cross-sectional view of a conventional one-dimensional FET.

FIG. 4 is a plan view of an FET for explaining the effect of the present invention.

FIG. 5 is an electron density distribution diagram for explaining the effect of the present invention.

FIG. 6 is a diagram comparing the electronic sheet densities of the present invention and the conventional 2DEG.

FIG. 7 is a diagram comparing the electronic sheet densities of the present invention and the conventional 2DEG.

FIG. 8 is a graph showing high frequency characteristics of FETs of the present invention and a conventional example.

FIG. 9 is a graph showing the gate voltage dependence of the source / drain current in the saturation region of the FET of the present invention and the conventional example.

FIG. 10 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 11 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 12 is a diagram for explaining a transistor according to an example of the present invention.

FIG. 13 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 14 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 15 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 16 is a diagram for explaining a transistor according to an example of the present invention.

FIG. 17 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 18 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 19 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 20 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 21 is a diagram for explaining a transistor according to one example of the present invention.

FIG. 22 is a diagram for explaining the basic configuration of a one-dimensional channel carrier transistor according to the present invention.

[Explanation of symbols]

11 ... Undoped GaAs, 13 ... n-Al _x Ga _1-x A
s, 15 ... Depletion layer, 16 ... Undoped Al _y Ga _1-y A
s, 18 ... Single layer or several layers of δ-doped layer, 20 ... Gate electrode, 21 ... Source electrode, 22 ... Drain electrode, 30 ...
One-dimensional electron channel, 31 ... Inactive region, 50 to 53
... Electron diffusion path, 70-73 ... Electron diffusion region.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Harunori Sakaguchi 3550 Kitayo-cho, Tsuchiura-shi, Ibaraki Hitachi Cable Ltd. (72) Inventor Tadanori Tsuchiya 3550 Kidayo-cho, Tsuchiura-shi, Ibaraki Hitachi Cable Metal Research Institute Co., Ltd.

Claims (16)

[Claims] 1. A semiconductor region for forming a flow of charge carriers therein, control means for controlling the flow of the charge carriers, and a pair of electrodes for supplying the charge carriers. , The semiconductor region is substantially 1 for the charge carriers
A one-dimensional channel carrier transistor that provides a dimensional energy potential and a substantially key-shaped energy potential for confining the charge carriers in a direction intersecting the one-dimensional direction. 2. The one-dimensional channel carrier transistor according to claim 1, wherein the charge carrier is an electron existing in a conduction band of a semiconductor or a hole existing in a valence band. 3. A one-dimensional channel carrier transistor according to claim 1, wherein the flow of charge carriers forms a channel. 4. The one-dimensional channel carrier transistor according to claim 3, wherein the channel is in ohmic contact with the pair of electrodes. 5. The one-dimensional channel carrier transistor according to claim 1, wherein the control means controls the flow of the charge carriers by applying an electric field. 6. The one-dimensional channel carrier transistor according to claim 1, wherein the semiconductor region has first and second semiconductor regions.
A one-dimensional channel carrier transistor having the semiconductor region of (1) and inducing the charge carriers based on the energy difference at the energy band edge of these semiconductor regions. 7. The one-dimensional channel carrier transistor according to claim 6, wherein the second semiconductor region has an impurity region doped with a conductive impurity. 8. The one-dimensional channel carrier transistor according to claim 6, wherein the specific material combination of the first semiconductor / second semiconductor region is GaAs / AlGaA.
s, InGaAs / AlGaAs, InGaAs / Ga
A one-dimensional channel carrier transistor made of As or InGaAs / InAlAs. 9. The one-dimensional channel carrier transistor according to claim 1, wherein the semiconductor region has a plurality of the one-dimensional potentials. 10. The one-dimensional channel carrier transistor according to claim 9, wherein the plurality of one-dimensional potentials are formed along each other. 11. The one-dimensional channel carrier transistor according to claim 10, wherein the plurality of one-dimensional potentials are periodically arranged in a direction intersecting with the one-dimensional direction. 12. An active region having a potential barrier for substantially one-dimensionally limiting the degree of freedom of diffusion of charge carriers flowing through a channel, control means for controlling the flow of the charge carriers, and the charge carriers. A one-dimensional channel carrier transistor having a pair of electrodes for supplying to the active region, wherein the potential barrier has a bend for confining charge carriers. 13. The one-dimensional channel carrier transistor according to claim 12, wherein the cross section of the potential barrier has a triangular wave shape, a trapezoidal wave shape, or a rectangular wave shape. 14. The one-dimensional channel carrier transistor according to claim 12, wherein the control means controls the flow of the charge carriers by applying an electric field, and a conductivity type is provided between the control means and the active region. A one-dimensional channel carrier transistor having a charge carrier supply region including an impurity region doped with impurities. 15. The one-dimensional channel carrier transistor according to claim 14, wherein the thickness of the depletion region generated in the charge carrier supply region is non-uniform due to the influence of the bending. 16. The one-dimensional channel carrier transistor according to claim 15, wherein the charge carrier supply region has no neutral region.