JPH0553981A - Bus arbitrating circuit - Google Patents

Abstract

PURPOSE:To suppress the increase of a signal line for arbitration even when increasing external devices connected to a bus. CONSTITUTION:In the case of acquiring the use right of the bus between the plural external devices, this bus arbitrating circuit compares device number bit data C3-C0 set by a device number setting switch IDS with device number bit data/SD of the other external device and makes the larger device number bit data preferential only when the use right of the bus is simultaneously requested, and both device number bit data C3-C0 of the relevant external device and device number bit data/SD of the other external device are serially and successively outputted from the most significant digit for the unit of a bit and compared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit which mainly determines which external device, out of a plurality of external devices connected to this bus, can preferentially use a bus wired to a computer. Regarding

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional bus arbitration circuit of this type.

In FIG. 3, NOR _{1 to} NOR ₉ are negative logic NOR circuits, and INV _{1 to} INV ₄ are open collector type inverter circuits. / ID ₃ to / ID ₀ are bit data of the device number of the external device to which the bus arbitration circuit belongs among a plurality of external devices connected to a bus (not shown), and / ARB ₃ to / ARB ₀ are the same bus. Bit data of device number of other external device connected to / AR
B is a device number bit data / ARB ₃ from another external device.
This is device number output switch-on data for outputting ~ / ARB ₀ . Here, the symbol “/” indicates that it is a low active signal. Also, / ID ₃ , / ARB
₃ is the most significant digit, and / ID ₀ and / ARB ₀ are the least significant digits. There are a plurality of other external devices, but on behalf of them, the device number bit data of one external device / ARB ₃ ~ /
ARB ₀ and device number output switch-on data / ARB are shown.

Although the overall circuit configuration of the bus arbitration circuit is complicated, the basic circuit can be explained by the circuit portion consisting of the NOR circuit NOR ₁ , the inverter circuit INV ₁ and the NOR circuit NOR ₂ . The function of this circuit portion is compared with the device number bit data / ID ₃ of the external device and the device number bit data / ARB ₃ of the other external device, and when it is the same or larger, it is effective in the next stage. It is transmitted, and when it is small, it is considered as invalid and is not transmitted to the next stage. Both inputs of the NOR circuit are both "L".
The output is "H" only in the case of, and the output is "L" in all other cases.

When the device number output switch is turned on and the device number output switch ON data / ARB becomes "L", the device number bit data / ARB ₃ is input from the bus to the input terminal of the NOR circuit NOR ₂ .

Consider the case where / ID ₃ is “L”. /
Since ARB is "L", the output of the NOR circuit NOR ₁ becomes "H" and one input of the NOR circuit NOR ₂ becomes "H".
Becomes The output of the inverter circuit INV ₁ becomes “L”. Therefore, if it is left as it is, the NOR circuit NOR
The output of ₂ becomes "L", which is a valid signal for the low active circuit (NOR circuit NOR ₃ ) in the next stage.

Even if / ARB ₃ is "H", the output of the inverter circuit INV ₁ is "L".
B ₃ is drawn into the end "L", the NOR circuit 2 inputs of a NOR ₂ the "H""L", and the output of the NOR circuit NOR ₂ is "L".

Next, assuming that / ARB ₃ is "L" like / ID ₃ , the two inputs of the NOR circuit NOR ₂ are "H" and "L", and the output of the NOR circuit NOR ₂ is "L". L ".

The fact that the output of the NOR circuit NOR ₂ is "L" means that it is transmitted as an effective signal to the NOR circuit NOR _{3 of the} next stage.
This is because the NOR circuit NOR ₃ is low active. In this case, / ID ₃ is "L" and / ARB ₃
Is "H" or "L" means that the original ID ₃ excluding "/" is "H" and ARB ₃ is "L" or "H". ₃ ≧ ARB ₃
It was that.

Next, consider the case where / ID ₃ is “H”. / ARB is "L", NOR circuit NOR ₁
Output becomes "L", and one input of the NOR circuit NOR ₂ becomes "L". The output of the inverter circuit INV ₁ is “H”
Becomes Therefore, if it is left as it is, the NOR circuit N
The output of OR ₂ becomes “L”, which is a valid signal for the low active circuit (NOR circuit NOR ₃ ) in the next stage.

If / ARB ₃ is "H" like / ID ₃ , the output of the inverter circuit INV ₁ is also "H", so the two inputs of the NOR circuit NOR ₂ are "L" and "H". The output of the NOR circuit NOR ₂ becomes “L”, and the low-active NOR circuit NO of the next stage is
It will be transmitted as a valid signal to R ₃ .
In this case, / ID ₃ is "H" and / ARB ₃ is "H" means that the original ID ₃ excluding "/"
Is "L", and ARB ₃ is "L", which means that ID ₃ = ARB ₃ .

[0012] / When ID ₃ there is / ARB ₃ at "H" and is "L", the even output of the inverter circuit INV ₁ is "H", / ARB ₃ to be "L" Therefore, the output of the inverter circuit INV ₁ is eventually pulled to “L”, and the two inputs of the NOR circuit NOR ₂ are both “L”,
"L", and the output of the NOR circuit NOR ₂ is "H". The fact that the output of the NOR circuit NOR ₂ is “H” means that it becomes invalid for the low active NOR circuit NOR ₃ of the next stage. In this case, / ID ₃ is "H" and / ARB ₃ is "L", which means that the original ID ₃ excluding "/" is "L",
And it means that ARB ₃ is "H", and ID
_It means that ₃ <ARB ₃ .

The conclusion of the above is that
Whether or not / ID ₃ is "H" or "L", if the device number of the relevant external device is greater than or equal to the device number of another external device in that bit, then that The device number of the bit remains as a valid one and is transmitted to the next stage, but when it is small, it is lost as an invalid one and the transmission is stopped at that stage.

The comparison between the higher-order second bit / ID ₂ and / ARB ₂ is made by comparing the NOR circuit NOR ₃ and the inverter circuit INV.
₂ and NOR circuit NOR ₄ is performed in the circuit portion.

The comparison between the higher-order third bit / ID ₁ and / ARB ₁ is made by comparing the NOR circuit NOR ₅ and the inverter circuit INV.
_This is performed in the circuit portion consisting of ₃ and NOR circuit NOR ₆ . The comparison between the least significant digit / ID ₀ and / ARB ₀ is NO
R circuit NOR ₇ , inverter circuit INV ₄ and NOR
This is performed in the circuit portion including the circuit NOR ₈ . However, the comparison operation of each circuit portion is valid only when the output of each circuit portion located in the preceding stage is valid "L". If there is a circuit portion that outputs even an invalid "H" in the previous stage, the comparison operation becomes invalid and the comparison operation is stopped at that stage.

Therefore, only when the device number of the external device concerned is larger than the device numbers of other external device or devices in all the bits (the device numbers are not the same because they are all different) NOR Circuit NOR ₉
The bus use right acquisition signal GRANT, which is the output of, becomes active (valid “H”) (note that there is no inverter circuit in the next stage of the NOR circuit NOR ₉ ), and the external device concerned is the other unit or The bus will be used in preference to multiple external devices.

Here, points to be noted are, as will be described later, in the device number bit data of the external device concerned, all of / ID ₃ to / ID ₀ from the most significant digit to the least significant digit are simultaneously output. , The device number bit data of other one or more external devices is also / AR from the most significant digit to the least significant digit.
The point is that all of B ₃ to / ARB ₀ are output at the same time. That is, all bits are compared in parallel.

Hereinafter, referring to FIG. 4, the device numbers are # 9 and #.
A specific operation in the case of A and #E (these are hexadecimal (hexadecimal) notation) will be described.

The external device which intends to use the bus first confirms whether the bus request signal / RQST is output. If the bus request signal / RQST has already been output, the bus request signal / RQST cannot be output by itself, and therefore, the right to use the bus cannot be acquired in this case. Bus request signal /
When RQST is not output, the bus request signal / RQ is synchronized with the rising edge of the system clock CLK.
After outputting ST, all bit data / ID ₃ to / ID ₀ of the device number of the external device in question are simultaneously sent to the arbitration signal lines AL _{3 to} AL ₀ , and the device number output switch is turned on. All bit data / ARB ₃ to / ARB ₀ of the device number of the external device are simultaneously read into the arbitration signal lines BL _{3i to} BL _0i .

The arbitration signal lines BL _{3i to} BL _0i are
The same number of other external devices are connected to the same line. Further, the arbitration signal lines AL ₃ ~AL ₀ of the external device
Are connected to corresponding locations of the bus arbitration circuit in all other external devices.

Therefore, simultaneous reading of all bit data / ARB ₃ to / ARB ₀ of all other external devices is performed in parallel.

In this case, device number # 9 and device number #A
2 external devices simultaneously output the bus request signal / RQST (time t ₁ ). Then, since the bus requests from both external devices compete with each other, the arbitration circuit described above is executed in the bus arbitration circuit in each external device, and the one with the larger device number is generated at the next rise timing of the system clock CLK. The external device #A makes the bus use right acquisition signal GRANT active (“H”) to acquire the bus use right (time t ₂ ). The external device # 9, which has the smaller device number, cannot activate the bus use right acquisition signal GRANT, but retains the output state of its own bus request signal / RQST.

When the external device having the device number #A finishes using the bus (time t ₃ ), the external device has its own bus request signal / RQST and all bit data of the device number / ARB.
₃ to / ARB ₀ output is stopped. Then, at the next rising timing of the system clock CLK, the external device # 9 having the next highest device number receives the bus right acquisition signal GR.
ANT is activated and the bus use right is acquired (time t ₄ ).

Even if another external device with the device number #E outputs the bus request signal / RQST while the external device with the device number # 9 is using the bus (time t ₅ ), the device is already available. Since the bus request signal / RQST with the number # 9 is output, the external device with the device number #E cannot participate in the bus arbitration.

When the external device with the device number # 9 finishes using the bus (time t ₆ ), the external device has its own bus request signal / RQST and all bit data of the device number / ARB.
₃ to / ARB ₀ output is stopped. As a result, all of the external devices that simultaneously output the bus request signal / RQST have finished using the bus, and the bus request signal / R
QST becomes inactive (“H”). That is,
The bus will be free.

Therefore, when the external device having the device number #E again outputs the bus request signal / RQST in the bus-free state (time t ₇ ), it is accepted this time, and in this case, another conflict occurs at the same time. Since there is no external device, the arbitration operation is practically not performed, and the system clock CLK
The device number #E activates the bus use right acquisition signal GRANT at the timing of the next rising edge of, and acquires the bus use right (time t ₈ ).

The above operation is repeated, and the priority order of the bus use right is determined only when a plurality of external devices request the bus use right at the same time, and in other cases, the win comes first. The arbitration of the right to use the bus will be fair on average.

[0028]

However, in the case of the bus arbitration circuit having the circuit configuration as shown in FIG. 3, as the device number bit data of the external device concerned, / ID from the most significant digit to the least significant digit thereof is used. _{All 3} to / ID ₀ are output at the same time, and even as device number bit data of other external devices,
Since it uses the total bit parallel comparison processing method that outputs all the most significant digit to the least significant digit / the ARB ₃ ~ / ARB ₀ simultaneously, for arbitration larger the number of external devices connected to the bus There is a problem in that the number of signal lines BL _{3i to} BL _0i increases and the wiring as a whole becomes complicated.

The present invention was devised in view of such circumstances, and limits the number of arbitration signal lines to a small number regardless of the increase in the number of external devices connected to the bus.
The purpose is to simplify the wiring as a whole.

[0030]

In a bus arbitration circuit according to the present invention, a plurality of other external devices are connected to a bus together with the external device, and the device number bit data of the external device and other If the device number bit data of another external device is larger than the device number bit data of another external device, the bus use right is transferred to this other external device and the device number bit data of the external device concerned is transferred. When the data is larger, this external device is a bus arbitration circuit that acquires the right to use the bus, and during the arbitration period composed of a plurality of bus arbitration clocks, the external arbitration clock synchronizes with the bus arbitration clock. The device number bit data of the external device is serially output from the most significant digit, and the device number bit data of other external devices are also serially output from the most significant digit. In this way, the device number bit data of each bit output serially are compared, and if the bit data of the external device in question is larger or the same, the arbitration operation is continued and the bit data of the other external device is compared. If the one is larger, the arbitration operation is stopped and the bus use right is transferred to another external device. If the bit data of the external device is larger or equal to the least significant digit, the external device uses the bus. It is characterized in that it is configured to acquire the right.

[0031]

The device number bit data to be compared with each other is serially output bit by bit rather than in parallel and compared, so that the arbitration period can be lengthened even if the number of external devices connected to the bus increases. Therefore, it is not necessary to increase the arbitration signal line.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bus arbitration circuit according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a bus arbitration circuit according to an embodiment of the present invention.

In FIG. 1, AND _{1 to} AND ₅ are AN
D circuit, INV _{11 to} INV ₁₃ are open collector type inverter circuits, INV ₂₀ are normal type inverter circuits, N
OR ₁₁ is a NOR circuit, and FF _{1 to} FF ₉ are D type (delay type)
Flip-flop circuit, CNT is a synchronous 2-bit 2
An advance counter circuit, DSE is a line data selector circuit composed of a 2TO4 IC, and IDS is a device number setting switch.

L ₁ is a bus request signal / BRQ signal line, L ₂ is a serial output type device number bit data / SD
, L ₃ is a signal line of a bus arbitration clock CLK for synchronizing bus arbitration, L ₄ is a signal line for outputting a bus request signal / BRQ from the bus arbitration circuit of the external device, and L ₅ is a bus. A signal line for pulling the arbitration clock CLK to the bus arbitration circuit, L ₆ is a signal line for pulling serial output type device number bit data / SD of another external device or devices to the bus arbitration circuit. is there.

The bus request signal / BRQ indicates that the bus is in an open state when it is "H", and means that the bus is in use when it is "L". The serial output type device number bit data / SD is a device number bit data and also a signal for arbitration operation when a plurality of external devices connected to the bus try to acquire the bus use right at the same time. Signal line L ₁ ,
L ₂ and L ₃ form part of the signal line on the bus.

RQ is a bus request signal in the external device, and ACK is the bus arbitration circuit itself that confirms that the external device has acquired the bus use right and transmits it to the bus arbitration circuit of another external device. Bus use right acquisition confirmation signal, and the corresponding bus request signal RQ and bus usage right acquisition confirmation signal ACK are the bus request signal / B.
It is a high active signal which is the opposite of RQ and serial output type device number bit data / SD.

The operation truth value of the binary counter circuit CNT is as follows.

Input / output CLK CLR QA QB RC Irrelevant “L” “L” “L” “L” Not relevant “H” Count Not relevant “H” “H” “H” “H” Also, line data The operation truth value of the selector circuit DSE is as follows.

Here, EN is an enable terminal of the line data selector circuit DSE.

[0041] Next, the operation of the bus arbitration circuit of this embodiment configured as described above and connected as shown in the drawing will be described with reference to the timing chart of FIG.

The external device sets the bus request signal RQ to "H" at the rising timing of the bus arbitration clock CLK to acquire the bus use right (time t).
₁₁ ). At this time, the level B of the Q output of the flip-flop circuit FF ₂ is “L” and the output level of the inverter circuit INV ₁₁ is “H”, so the output level A of the AND circuit AND ₁ becomes “H”. (Time t ₁₁ ). Since the Q output level D of the flip-flop circuit FF ₄ is “L”, the output level F of the RC terminal of the binary counter circuit CNT is “L”. Therefore, the output level J of / Q of the flip-flop circuit FF ₅ is "H". Since the output level of / Q of the flip-flop circuit FF ₇ is also "H", all three inputs of the AND circuit AND ₃ become "H", and its output level K rises to "H" of the bus request signal RQ. accompanied by the "H" (time t _11).

The relevant bus arbitration circuit, to which the relevant "H" bus request signal RQ is input, receives the bus arbitration clock CLK.
If the bus request signal / BRQ of another external device or a plurality of external devices is "H" and the bus is in the open state at the rising timing of the signal line L ₁ at the falling timing of the next bus arbitration clock CLK. "L" is output via the signal line L ₄ relative to the bus request signal / B
The RQ to "L" of the active (time t _12). That is, since the Q output of the flip-flop circuit FF ₁ becomes “H”, the output level B which is the Q output of the flip-flop circuit FF ₂ becomes “H”, and the output of the inverter circuit INV ₁₁ becomes “L”. Is. When the output level B is set to "H" and the bus request signal / BRQ is once set to active "L", the corresponding external device acquires the bus use right and terminates the use of the bus to abandon the bus use right. Until (time t ₂₇ ), the output level B is kept at “H” and the active “L” bus request signal / BRQ is continuously output.

The output level A of the AND circuit AND ₁ returns to "L" (time t ₁₂ ) but the flip-flop circuit F
The output level B of F ₂ is held at “H”. When the output level B becomes “H”, the flip-flop circuit FF ₄ /
Since the Q output level is “H”, the Q output level of the flip-flop circuit FF ₇ is “L”, and the output level of the inverter circuit INV ₁₃ is “H”,
The output level C of the ND circuit AND ₂ becomes “H” (time t ₁₂ ).

When the output level C of the AND circuit AND ₂ becomes “H”, the Q output level of the flip-flop circuit FF ₃ becomes “H” at the next rising timing of the bus arbitration clock CLK, and at the same time, the flip-flop circuit FF ₄ the Q output level D becomes "H" (time t _13).
Since the / Q output level of the flip-flop circuit FF ₄ becomes “L”, the output level C of the AND circuit AND ₂
Return to the "L" (time t _13). Binary counter circuit CNT
Since the clear terminal CLR of the signal is inverted from "L" to "H", the binary counter circuit CNT detects the bus arbitration clock
Counting is started in a state synchronized with (time t ₁₃ ). Further, since the / Q output level H of the flip-flop circuit FF ₉ is "H", when the output level D becomes "H", A
Since the output level of the ND circuit AND ₅ becomes “H” and the enable terminal EN of the line data selector circuit DSE becomes “H”, the line data selector circuit DSE
Outputs the 4-bit device number bit data C _{0 to} C ₃ set by the device number setting switch IDS serially from the most significant digit in synchronization with the bus arbitration clock CLK. C ₃ is the most significant digit and C ₀ is the least significant digit.

Here, it is assumed that there are three external devices requesting the bus, including the external device, and the device number of the external device is 1010B in binary notation.
And the device numbers of the other two external devices are 11
00B and 0110B.

The device number 1010B of the relevant external device is 2
Second largest. The device number of the external device is C ₃ =
1, C ₂ = 0, C ₁ = 1 and C ₀ = 0.

When the binary counter circuit CNT starts counting and the line data selector circuit DSE becomes active (time t ₁₃ ), the arbitration operation by the bus arbitration circuit is started. The arbitration period T ₀ is a period of 4 clocks from time t ₁₃ when the output level D becomes “H” to time t ₁₈ when the output level D returns to “L”. The arbitration period T ₀ is started at the same timing in other external devices,
Each device number bit data is serially output to the signal line L ₂ from the most significant digit to the least significant digit.

The bus arbitration circuit of each external device suspends the arbitration operation after that when its own device number bit data is smaller than the other device number bit data. In the first clock period of the arbitration period T ₀ , the output level E of the line data selector circuit DSE is the device number 1010.
The highest digit of B is "H". On the other hand, device number 1100
Another most significant digit of the serial output type device number bit data / SD external devices B is, / SD is "L" because it is inverted to a low-active (time t _13).

When the output level E of the line data selector circuit DSE becomes "H", the output level of the inverter circuit INV ₁₂ becomes "L", and the 2 inputs of the NOR circuit NOR ₁₁ are set to the state of the bus arbitration circuit concerned. Limited to "L",
It becomes "H". Since the serial output type device number bit data / SD from the signal line L ₆ is also “L”,
There is no change in the "L" and "H" states, and the NOR circuit NO
The output level G of R ₁₁ remains “L” (time t ₁₃ ).

In the second clock period of the arbitration period T ₀ , the output level E of the line data selector circuit DSE.
Becomes the second bit “L” of the device number 1010B (time t ₁₄ ). While the other serial output type device number bit data / second bit SD external device device number 1100B is "L" (time t _14). When the output level E of the line data selector circuit DSE becomes “L”, the output level of the inverter circuit INV ₁₂ becomes “H”, and NO
The two inputs of the R circuit NOR ₁₁ are "H" and "L" only in the state of the bus arbitration circuit concerned, but the signal line L ₆
Since the serial output type device number bit data / SD from "L" is "L", "H" of the output of the inverter circuit INV ₁₂ is pulled to "L", so that the two inputs are "L",
It becomes "L", and the output level G of the NOR circuit NOR ₁₁ is inverted to "H". (Time t ₁₄ ).

When the output level G of the NOR circuit NOR ₁₁ is inverted to "H", the flip-flop circuit FF ₈ becomes
Due to the existence of the inverter circuit INV ₂₀ , the Q output level thereof is set to “H” at the next fall timing of the bus arbitration clock CLK, and at the same time, the flip-flop circuit FF ₉
Invert Roh / Q output level H to "L" (time t _15).
When the output level H is inverted to "L", the AND circuit AND
Output level of ₅ , that is, line data selector circuit DSE
Since the enable terminal EN becomes "L", the line data selector circuit DSE stops outputting the unit number of the external device becomes inactive (time t _15).

Then, the line data selector circuit DSE
The output level E of is held at "L". Since the serial output type device number bit data / SD of the other external device becomes "H" during the third clock period of the arbitration period T ₀ , the two inputs of the NOR circuit NOR ₁₁ become "H" and "L". its output level G is inverted to "L" (time t _16).

[0054] The output level F of the RC terminal of the fourth clock period starts the binary counter circuit CNT arbitration period T ₀ becomes "H" by the count-up (time t _17).

[0055] When the output level F is set to "H", the bus arbitration clock CLK output level J of the flip-flop circuit FF ₅ at the next rising timing is inverted to "L" (time t _18), along with this The output level K of the AND circuit AND ₃ is inverted to “L” (time t ₁₈ ), and the flip-flop circuits FF ₃ and FF ₄ are cleared by low active.
There is clear, the output level D is inverted to "L" (time t _18). Then, the inversion of the output level D to "L" makes the binary counter circuit CNT inactive, its output is held at "L", "L", and the arbitration period T
₀ ends.

It should be noted, with return to the output level F is "L" of the RC terminal, since the inverted output level D is "L", the flip-flop circuit FF _8, FF ₉ is cleared by low active is cleared , / Q output level H is inverted to "H" (time t _18).

In this case, the external device with the device number 1010B temporarily relinquishes the right to use the bus, and the device number 11010B.
The other external device of 0B has acquired the bus use right. Other external device that won the bus use right, the serial output type device number bit data / SD output a stop held to "L" (time t _18: However, the time t ₂₀ from here
Up to / SD "L" is a timing chart of another external device), indicating that the bus is in use. Retaining this serial output type device number bit data / SD at "L" means that for the bus arbitration circuit concerned,
This means that one input of the AND circuit AND ₂ is held at “L” via the signal line L ₆ , and its output level C
Is held at "L".

[0058] Incidentally, later the output level F is returned to "L" (time t _18), at the rising edge of the next bus arbitration clock CLK, the output level of the flip-flop circuit FF ₅ returns to "H", the same time The output level K of the AND circuit AND ₃ also returns to “H” (time t ₁₉ ).

Device number 1100B that acquired the bus use right
When the other external device finishes using the bus, the external device sets the serial output type device number bit data / SD to "H" at the rising timing of the bus arbitration clock CLK.
(Time t ₂₀ ). This informs other external devices that the bus has been used up. For the relevant bus arbitration circuit, this corresponds to returning the level input to the AND circuit AND ₂ to “H” via the signal line L ₆ . The external device with the device number 1100B also returns the bus request signal / BRQ to "H" at the same time, but since the external device which is not using the bus outputs "L" as the bus request signal / BRQ, / BRQ Holds "L". The bus request signal / BRQ holds "L" until all the external devices currently participating in the arbitration operation have finished using the bus, and as a result, the external devices not currently participating in the arbitration operation. Is refused to participate.

[0060] At this point, has already been cleared flip-flop circuit FF ₄ once, (from time t ₁₈₎ of the / Q output level is turned to "H". Further, the output level B are kept "H" from the time t _12. Device number 1
As a result of the external device of 100B returning the serial output type device number bit data / SD to "H" to notify the end of the use of the bus, all three inputs of the AND circuit AND ₂ become "H", and the output level C is again set. It becomes “H” (time t ₂₀ ).

When the output level C of the AND circuit AND ₂ becomes "H", the arbitration period T ₀ is entered through the same operation as in the previous case. That is, first, since the Q output level of the flip-flop circuit FF ₃ becomes "H", the Q output level D of the flip-flop circuit FF ₄ becomes "H", and its / Q output level becomes "L", so the AND circuit. AND
₂ output level C is returned to "L" (time t _21). Also,
When the binary counter circuit CNT starts counting, the line data selector circuit DSE becomes active (time t ₂₁ ).

The device number 1010 is arbitrated here.
B is the relevant external device and the other external device with the device number 0110B. That is, each external device serially outputs the device number bit data from the most significant digit to the least significant digit. For the external device device number 1010B, other external device device number 0110B, first, because the larger the most significant digit, to stop the arbitration operation after time t ₂₂ is the bus arbitration circuit of other external devices become. In the bus arbitration circuit of the external device, the arbitration operation is performed over the entire arbitration period T ₀ , but the device number bit data to be compared is its own,
The two inputs of the NOR circuit NOR ₁₁ are always "L" and "H", and its output level G is always "L" (time t ₂₁
From time t ₂₅ ).

When the binary counter circuit CNT counts up and the output level F of its RC terminal becomes "H", since the output level H is "H", the AND circuit AND
₄ the output level I becomes "H" (time t _24). At the next rising timing of the bus arbitration clock CLK, the / Q output level J of the flip-flop circuit FF ₅ is inverted to “L”, so that the output level K of the AND circuit AND ₃ is inverted to “L”, and the flip-flop circuit FF is flipped. ₃ , FF ₄
There is clear, the output level D is inverted to "L" (time t _25). The inversion of the output level D to "L" makes the binary counter circuit CNT inactive, and the arbitration period T ₀ ends.

Then, as described above, the AND circuit AND ₄
Output level because I is inverted to "H" of the (time t _24),
The Q output level of the flip-flop circuit FF ₆ is "H" at the next rising timing of the bus arbitration clock CLK.
Then, the Q output level of the flip-flop circuit FF ₇ becomes "H" and the / Q output level becomes "L" (time t ₂₅ ). The fact that the Q output level of the flip-flop circuit FF ₇ is inverted to "H" means that the bus use right acquisition confirmation signal ACK has become "H", and the bus use right is acquired to another external device. Tell them what you did. At the same time, a serial output type device number bit data / SD output a stop and held at "L" indicating that in use of the bus (time t _25).

AND when the output level D becomes "L"
The output level of the circuit AND ₅ becomes “L”, the enable terminal EN becomes “L”, and the line data selector circuit D
SE is made inactive and the output level E is made "L". The output level of the inverter circuit INV ₁₂ becomes "H", but the Q output level of the flip-flop circuit FF ₇ is "H", which is inverted by the inverter circuit INV ₁₃ and becomes "L". The two inputs of NOR ₁₁ both become "L" and "L", and their output level G
But the "H" (time t _25).

Since the binary counter circuit CNT becomes inactive and the output level F of the RC terminal becomes "L",
The output level I of the AND circuit AND ₄ returns to "L" (time t ₂₅ ). After the output level F returns to “L” (time t ₂₅ ), the / Q output level J of the flip-flop circuit FF ₅ returns to “H” at the next rise timing of the bus arbitration clock CLK ( At time t ₂₆ ), and at this time, the output level I has already become “L”, but since the / Q output level of the flip-flop circuit FF ₇ remains “L”, the output level K of the AND circuit AND ₃ Remains "L". Similarly, the flip-flop circuit F
Since the Q output level of F ₇ is kept at “H”, the bus right acquisition confirmation signal ACK is also kept at “H”.

When the external device of the device number 1010B which has acquired the bus use right as described above ends the use of the bus, the external device outputs the serial output type device number bit data at the rising timing of the bus arbitration clock CLK. / SD is returned to "H" to inform other external devices that the use of the bus is completed, and the bus request signal R
To return to the "L" the Q to give up the right to use the bus (time t _27). Accordingly, the flip-flop circuit FF ₁ ,
The FF ₂ , FF ₆ , and FF ₇ are cleared, the output level B and the bus use right acquisition confirmation signal ACK are returned to “L”, and at the same time, the inverter circuit INV ₁₃ is inverted to “H”.
Since There the first input of the NOR circuit NOR _11, the output level G of the NOR circuit NOR ₁₁ is returned to "L" (time t _27).

The external device with the device number 1010B also returns the bus request signal / BRQ to "H" at the same time, but the external device with the device number 0110B that is not using the bus outputs "L" as the bus request signal / BRQ. / BR
Q holds "L".

The same arbitration operation as described above is performed for the external device having the device number 0110B.

As described above, the bus arbitration circuit of this embodiment compares the device number bit data of the external device concerned with the device number bit data of the other external device, and compares the device number bit data of the other external device. When the data is larger, the bus usage right is transferred to the other external device. When the device number bit data of the external device is larger, the external device acquires the bus usage right. In the circuit, in an arbitration period T ₀ consisting of a plurality of clocks of the bus arbitration clock CLK, in synchronization with the bus arbitration clock CLK, the device number bit data of the external device is output serially from the most significant digit, and Similarly, the device number bit data of other external devices are also serially output from the most significant digit, and device number bit data serially output in this way in bit units. If the device number bit data of the relevant external device is larger or the same, the arbitration operation is continued, and if the device number bit data of the other external device is larger, the arbitration operation is stopped. Transfer the bus usage right to another external device, and if the device number bit data of the external device to the least significant digit is greater or equal, configure the external device to acquire the bus usage right. is there.

Therefore, even if the number of external devices connected to the bus increases, unlike the conventional all-bit parallel comparison processing method, it is not necessary to increase the number of arbitration signal lines, and the arbitration period T ₀ is increased. be able to. However,
It may be necessary to increase the bit number of the binary counter circuit CNT or the device number setting switch IDS.

[0072]

As described above, according to the present invention, all the bits of the device number bit data to be compared are not simultaneously output in parallel and compared as in the conventional example, but serially one bit at a time. Since the output is made for comparison, even if the number of external devices connected to the bus increases, it can be dealt with by lengthening the arbitration period, and the arbitration signal lines can be reduced to simplify the wiring as a whole. ..

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a bus arbitration circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram showing a bus arbitration circuit according to a conventional example.

FIG. 4 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

AND _{1 to} AND ₅ AND circuit INV _{11 to} INV ₁₃ open collector type inverter INV ₂₀ normal type inverter NOR ₁₁ NOR circuit FF _{1 to} FF ₉ D type flip flop CNT binary counter circuit DSE line data selector circuit L ₁ to L ₆ signal line / BRQ bus request signal / SD serial output type device number bit data CLK bus arbitration clock RQ bus request signal ACK bus usage right confirmation signal

Claims (1)

[Claims] 1. When a plurality of other external devices are connected to the bus together with the external device, and the bus use requests are issued from the multiple devices at the same time, the device number bit data of the external device is stored. If the device number bit data of the other external device is larger than the device number bit data of the other external device, the bus use right is transferred to the other external device to wait, and the external device When the device number bit data is larger, this external device is a bus arbitration circuit that acquires the right to use the bus, and is synchronized with the bus arbitration clock during the arbitration period consisting of multiple clocks of the bus arbitration clock. , The device number bit data of the relevant external device is serially output from the most significant digit, and the device number bit data of other external devices are also serially output from the most significant digit. Then, the device number bit data in each bit serially output in this way is compared, and if the bit data of the external device concerned is larger or the same, the arbitration operation is continued and the other external device is continued. If the bit data of the external device is larger, the arbitration operation is stopped and the right to use the bus is transferred to another external device. If the bit data of the external device is larger up to the least significant digit, the external device uses the bus. A bus arbitration circuit characterized by being configured to acquire a right.