JPH0553699A - Operational margin detection circuit - Google Patents

Abstract

PURPOSE:To provide the operational margin detection circuit to be integrated in an LSI with the other circuits. CONSTITUTION:An arithmetic unit 1 inputs arithmetic data A and B at the leading edge of a clock signal phi, outputting the arithmetic result to a latch 3 circuit as well as to a carry C. The latch circuit 3 latches the arithmetic result outputted from the arithmetic circuit 1 at the trailing edge of the clock signal phi. An exclusive OR gate 5 performs the direct input of the carry C as well as the indirect input through a delay circuit 2. A latch circuit 4 latches the output of the exclusive OR gate 5 at the trailing edge of the clock signal phi.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a large scale integrated circuit (hereinafter,
(Hereinafter referred to as an LSI), an operation margin detection circuit that detects an operation margin of an internal circuit provided in the LSI.

[0002]

2. Description of the Related Art Recently, LSIs used in microcomputers and the like have been promoted to have higher performance, smaller size and lower power consumption. Along with this, portable devices such as a handy terminal using an LSI and an electronic notebook have been developed.

LSI incorporated in these portable devices
Operates in synchronization with a clock signal generated by an oscillator circuit including a crystal or ceramic resonator or the like. In this case, the oscillation frequency of the oscillator circuit is
For example, it is set to 32 kHz for a watch, depending on the application.

Equipment such as a handy terminal generally uses a dry battery as a power source for portable use. However, since the electric power capacity stored in the dry battery is limited, the dry battery is consumed and the voltage drops as the device is used.

On the other hand, the operation speed of an LSI generally decreases as the power supply voltage decreases. For this reason, when the power supply voltage drops below a certain value due to the exhaustion of the dry battery, the operating speed of the LSI cannot follow the clock frequency set by the oscillator circuit, and malfunction occurs.

For example, in the case of an electronic desk calculator, even if the LSI malfunctions, the battery may be replaced with a new one and the calculation may be performed again. In the case of a handy terminal or the like, however, if the LSI malfunctions, information on the customer or the product may be obtained. Important data such as may be lost.

In order to prevent such a malfunction, a device such as a handy terminal is usually provided with a power supply voltage detection circuit, and an interrupt is generated when the voltage of the dry battery falls below a voltage that guarantees a normal operation of the LSI. Generate a signal,
This interrupt signal is input to an interrupt terminal provided in the LSI. When an interrupt signal is given, the LSI performs power fail processing such as data saving, battery lamp lighting and stop processing, etc. in response to the interrupt signal. In addition, the user of the device looks at the display of the battery lamp and saves necessary data to the host machine or replaces the dry battery.

As described above, conventionally, a portable device such as a handy terminal is provided with a power supply voltage detection circuit as a circuit for detecting an operation margin for guaranteeing a normal operation of an LSI.

[0009]

However, the power supply voltage detection circuit as the above-mentioned operation margin detection circuit has the following problems. That is, in general, it is difficult to highly integrate the power supply voltage detection circuit,
SI is formed separately. Therefore, in the portable device provided with the power supply voltage detection circuit, not only is the size of the device increased by the size of the power supply voltage detection circuit, but the power supply voltage detection circuit causes a rise in the product cost of the device.

The present invention has been made in view of the above problems, and can be constructed with a small number of gates.
It is an object to provide an operation margin detection circuit that can be incorporated inside SI.

[0011]

An operation margin detection circuit according to the present invention is an operation margin detection circuit integrated and provided on a semiconductor substrate, in which a first signal is input, delayed by a predetermined time, and output. A delay circuit; a logic circuit that outputs a specific signal based on the output of the first signal and the delay circuit; and a holding circuit that holds the output of the logic circuit based on a second signal. Characterize.

[0012]

In the present invention, the operating margin of the circuit provided in the LSI is detected by utilizing the fact that the operating speed of the circuit decreases when the power supply voltage decreases. That is, in the present invention, the logic circuit is provided with the first signal and the signal obtained by delaying the first signal by the delay circuit. This logic circuit outputs a specific signal, for example, when both logic values match. The holding circuit holds the output of this logic circuit based on the second signal.

For example, when the circuit for which the operation margin is to be detected has completed a predetermined operation, the first signal is output and the operation margin is detected until the logical value of the second signal is inverted. It is assumed that the malfunction can be avoided if the operation of the circuit to be completed is completed. Then, when the power supply voltage is sufficiently high and the operation margin is sufficient, there is sufficient time between the output of the first signal and the inversion of the logical value of the second signal. Holds the specific signal.

On the other hand, when the power supply voltage is lowered and the operation speed of the circuit is lowered, the logic circuit is operated by the logic circuit between the output of the first signal and the inversion of the logic value of the second signal. The signal cannot be output, and the holding circuit holds a signal different from the specific signal. This makes it possible to detect whether the operation margin is sufficient or insufficient.

[0015]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to an arithmetic circuit provided inside an LSI.

The arithmetic unit (ALU) 1 has arithmetic data A and B.
Is input to perform a predetermined arithmetic operation process. In this case,
The arithmetic data A and B are input to the arithmetic unit 1 in synchronization with the rising edge of the clock signal φ.

The latch circuit 3 latches the calculation result output from the calculator 1 in synchronization with the falling edge of the clock signal φ. Then, the latch circuit 3 outputs the latched calculation result as a calculation output S.

On the other hand, the arithmetic unit 1 outputs the carry C in the course of arithmetic processing. This carry C is a signal that is not finalized until all the calculations are completed. The delay circuit 2 inputs the carry C, delays it by a preset delay time Td, and outputs it. The delay time Td of the delay circuit 2 is preset according to the operation margin of the arithmetic unit 1.

The exclusive OR gate 5 inputs the carry C and the output of the delay circuit 2. The latch circuit 4 latches the output of the exclusive OR gate 5 in synchronization with the falling edge of the clock signal φ. The output of the latch circuit 4 is output as the operation margin signal Q.

Next, the operation of the operation margin detection circuit according to this embodiment will be described.

The arithmetic unit 1 inputs the arithmetic data A and B in synchronization with the rising edge of the clock signal φ and starts the arithmetic operation. Then, the computing unit 1 finishes the computation after the computation time Ta. The calculation time Ta varies depending on the power supply voltage and is sufficiently shorter than the high level width of the clock signal φ when the power supply voltage is sufficiently high. Therefore, when the power supply voltage is sufficiently high, the arithmetic unit 1 ends the arithmetic operation with a sufficient time until the clock signal φ falls, so that the latch circuit 3 latches the correct arithmetic result. On the other hand, when the power supply voltage decreases, the operation speed of the arithmetic unit 1 becomes slower, the arithmetic time Ta becomes longer, and the arithmetic operation is not completed before the clock signal φ falls. Different values get latched.

By the way, since the carry C is a signal that is not determined until all the operations of the arithmetic unit 1 are completed, the critical path from the input of the arithmetic data A and B to the arithmetic unit 1 to the output of the carry C. Becomes This carry C is delayed by the delay time Td set in the delay circuit 2 and input to the exclusive OR gate 5. Therefore, the exclusive OR gate 5 outputs a low level after a delay time Td from the output of the carry C, and outputs a high level before that.

Assuming that the power supply voltage is sufficiently high, the calculator 1
Is sufficiently short, the delay time T set according to the operation time Ta and the operation margin of the operation unit 1
The value obtained by adding d and is also shorter than the high level width of the clock signal φ. Therefore, when the clock signal φ falls, the output of the exclusive OR 5 gate is at a low level, and the latch circuit 4 latches the low level. That is, when the operation margin signal Q is at low level, it means that the operation unit 1 has a sufficient operation margin.

As the power supply voltage decreases, the calculation time Ta of the calculator 1 gradually becomes longer and approaches the high level width of the clock signal φ. However, the calculation time Ta and the delay time T
When the value obtained by adding d and is shorter than the high level width of the clock of the clock signal φ, the calculation result by the calculator 1 is correctly latched by the latch circuit 3, and the latch circuit 4 outputs the low level.

When the power supply voltage further decreases, the value obtained by adding the calculation time Ta of the calculator 1 and the delay time Td of the delay circuit 2 exceeds the high level width of the clock signal φ. Then, the clock signal φ falls before the output of the exclusive OR gate 5 becomes low level, and the latch circuit 4 latches the high level. Therefore, a high level is output as the operation margin signal Q.

When the operation margin signal Q is at high level, it means that the operation margin of the computing unit 1 is insufficient. In this case, in the LSI, an interrupt is generated by the high level output of the operation margin signal Q, and a predetermined power fail process is executed.

In the present embodiment, the operating margin is detected not by directly detecting the power supply voltage but by utilizing the decrease in the operation speed due to the decrease in the power supply voltage. Therefore, the operation margin detection circuit can be configured by only the logic circuit such as the delay circuit, the exclusive OR gate, and the latch circuit, and thus the operation margin detection circuit can be easily integrated with other circuits inside the LSI. This makes it possible to reduce the number of components mounted on, for example, a printed circuit board as compared with the related art, and to further reduce the size and cost of a portable device such as a handy terminal. Further, in the present embodiment, the operation margin is detected directly by using the critical path instead of detecting the decrease in the power supply voltage, so that there is an advantage that the operation margin detection accuracy is higher than in the conventional case. ..

FIG. 2 is a circuit diagram showing an operation margin detecting circuit according to the second embodiment of the present invention.

The present embodiment differs from the first embodiment in that two sets of operation margin detection circuits are provided.
That is, the carry C output from the arithmetic unit 1 is the delay circuit 2
a and exclusive OR gates 5a and 5b. A delay time Td is set in the delay circuit 2a. Also,
The output of the delay circuit 2a is given to the exclusive OR gate 5a and the delay circuit 2b. Delay circuit 2b
Has a delay time Td1 set therein. This delay circuit 2b
Is supplied to the exclusive OR gate 5b. The latch circuits 4a and 4b latch the outputs of the exclusive OR gates 5a and 5b, respectively, in synchronization with the falling edge of the clock signal φ. The outputs of the exclusive OR gates 5a and 5b are output as operation margin signals Q and Q1, respectively.

In the circuit of this embodiment, the operation margin of the arithmetic unit 1 is detected in two stages as the power supply voltage decreases.

Next, the operation of the circuit of this embodiment will be described.

When the power supply voltage is sufficiently high and the operating margin of the computing unit 1 is sufficient, the computing time Ta of the computing unit 1 is short, so the computing time Ta, the delay time Td and the delay time T
The value obtained by adding d1 is shorter than the high level width of the clock signal φ. Therefore, in synchronization with the falling edge of the clock signal φ, the latch circuit 3 latches the calculation result output from the calculator 1, and the latch circuits 4a and 4b respectively receive the exclusive OR gates 5a and 5b. The low level which is the output of is latched. That is, in this case, the operation result is correctly output as the operation output S, and the operation margin signals Q and Q1 are at the low level.

When the power supply voltage is slightly reduced although it does not affect the operation of the computing unit 1, the computing time Ta of the computing unit 1
Is shorter than the high level width of the clock of the clock signal φ, the correct operation result is latched in the latch circuit 3 in synchronization with the falling edge of the clock signal φ, and the correct operation result is output as the operation output S. The value obtained by adding the operation time Ta and the delay time Td is also shorter than the high level width of the clock signal φ, and the latch circuit 4a latches the low level output of the exclusive OR gate 5a at the falling edge of the clock signal φ. , The operation margin signal Q becomes low level.

However, when the value obtained by adding the operation time Ta, the delay time Td and the delay time Td1 becomes longer than the high level width of the clock signal φ, the latch circuit 4b synchronizes with the falling edge of the clock signal φ and outputs the exclusive signal. Logical OR gate 5b
Input high level as output of. Therefore, the operation margin signal Q1 becomes high level.

As described above, when the operation margin signal Q is at the low level and the operation margin signal Q1 is at the high level, it is judged that the power supply voltage has decreased although the operation result of the operation unit 1 is not hindered inside the LSI. Then, the preset interrupt processing routine is activated.

As the interrupt processing, for example, the internal clock is switched to one having a low frequency to increase the operation margin, reduce the power consumption of the LSI, and prepare for the case where the power supply voltage further decreases, in advance of the LSI stop. Do.

When the power supply voltage further decreases, the calculation time Ta of the calculator 1 becomes longer and approaches the high level width of the clock signal φ. At this time, the operation time Ta is shorter than the high level width of the clock signal φ, so that the operation result by the operation unit 1 is latched by the latch circuit 3 in synchronization with the falling edge of the clock signal φ, and the operation output S is output. The correct calculation result is output.

However, the value obtained by adding the operation time Ta and the delay time Td and the value obtained by adding the operation time Ta, the delay time Td and the delay time Td1 all exceed the high level width of the clock signal φ. Therefore, in synchronization with the falling edge of the clock signal φ, the latch circuits 4a and 4b both latch the high level as the outputs of the exclusive OR gates 5a and 5b. Therefore, the operation margin signal Q,
Q1 becomes high level.

Inside the LSI, an interrupt processing routine is activated by the signals Q and Q1, and power fail processing is performed as in the first embodiment.

In this embodiment, the same effect as that of the first embodiment can be obtained, and in addition, the power fail process can be executed more reliably.

In the above embodiment, the case where the first signal given to the operation margin detecting circuit is the carry output from the arithmetic unit has been described, but the operation margin detecting circuit of the present invention is critical in the LSI. If the path can be used, it is not limited to the above arithmetic circuit
It is also applicable to OM (read only memory), RAM (read / write memory), multiplier or control system. Further, the location where the operation margin is detected is not limited to one location, and the operation margins of a plurality of circuits provided inside the LSI may be detected.

[0043]

As described above, the operation margin detection circuit according to the present invention includes a logic circuit that outputs a specific signal based on the output of the first signal and the delay circuit, and the logic circuit based on the second signal. Since it is configured by the holding circuit that holds the output of the circuit, the operation margin detection circuit can be integrated inside the LSI. As a result, it is possible to further reduce the size and cost of a portable device such as a handy terminal as compared with the conventional device. Further, the operation margin detection circuit according to the present invention directly detects the operation margin by using the critical path instead of detecting the power supply voltage, and therefore the operation margin detection accuracy is higher than that of the conventional one.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an operation margin detection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an operation margin detection circuit according to a second embodiment of the present invention.

[Explanation of reference numerals] 1; arithmetic unit 2, 2a, 2b; delay circuit 3, 4, a, 4b; latch circuit 5, 5a, 5b; exclusive OR gate

Claims (1)

[Claims] 1. An operation margin detection circuit integrated and provided on a semiconductor substrate, comprising: a delay circuit for inputting a first signal, delaying it for a predetermined time, and outputting it; and a delay circuit for the first signal and the delay circuit. An operation margin detection circuit comprising: a logic circuit that outputs a specific signal based on an output; and a holding circuit that holds an output of the logic circuit based on a second signal.