JPH0553357B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a television signal receiver including a nonlinear de-emphasis circuit, and particularly to a de-emphasis circuit suitable for enhancing the function of a phase-locked loop.

[Background of the invention]

As an example of a method for transmitting a television signal with a positive synchronization signal, NHK Giken Monthly Report, Vol. 27, No. 7
The MUSE (MUSE; Multiple
There is a Sub-Nyquist Sampling Encoding) method.

This method, as stated in the document,
Sub-Nyquist sampling is applied to a wideband high-definition television signal in four fields, which in principle compresses the band to about 1/4.
Furthermore, positive polarity synchronization is used as the synchronization signal.

Figure 2 shows an example of a synchronization processing circuit in the decoder section of a receiver that converts a high-definition television signal (hereinafter referred to as a "Muse signal") band-compressed by the Miuse method to the original wideband high-definition television signal. This is an example in which de-emphasis processing, which undoes non-linear emphasis processing that was processed on the sending side during transmission, is processed in the analog section.

In Fig. 2, 1 is the input terminal for the Muse signal, and 2, 3, and 4 are R, G, and B signals each having a wide band.
Signal output terminals, 5 and 6 are horizontal synchronization signals (HD) and vertical synchronization signals (VD) for monitoring, respectively, 7 is a de-emphasis circuit, 8 is an A/D converter, and 9 is for dividing the video signal and synchronization signal. Synchronous video separation circuit, 1
0 is a video signal processing circuit, 11 is an EPP detection circuit that detects a frame pulse signal corresponding to vertical synchronization,
12 is a PLL control circuit, 13 is a voltage controlled oscillation circuit (VCO), and 14 is an internal synchronization generating circuit that generates clamp pulses and the like.

The meuse signal from input terminal 1 is guided to de-emphasis circuit 7. The de-emphasis circuit 7 includes a non-linear de-emphasis circuit (for example, increases the signal gain by 1/4 when the absolute value of the input signal level |Vi| is smaller than the reference voltage Vs) in the amplitude direction of the waveform, and a 6dB at MHz
Emphasis on the transmitting side is canceled by passing through a de-emphasis circuit in the frequency direction that attenuates the amplitude by the amount. The muse signal that has passed through the day assist circuit 7 is converted into a digital signal by an A/D converter 8, and is subjected to video signal processing and synchronous signal processing in a synchronous video separation circuit 9; The other signal is guided to the EPP detection circuit 11 and the PLL control circuit 12. The EP detection circuit 11 detects a frame pulse corresponding to vertical synchronization inserted into the MUSE signal. The internal synchronization generation circuit 14 is
According to the clock from the VCO 13 and the signal from the EPP detection circuit 11, an internal synchronization signal and clamp pulse are generated. The PLL control circuit 12 compares the phases of the internal horizontal synchronization signal from the internal synchronization generation circuit 14 and the external horizontal synchronization signal, and controls the VCO 13 .

FIG. 3 shows a block diagram of the nonlinear de-emphasis circuit portion. In FIG. 3, 15 is an input terminal for a meuse signal, 16 is an output terminal for non-linear de-emphasis, 17 is an input terminal for a clamp pulse, 18 and 20 are buffer circuits, 19 is a clamp circuit, 21 is a variable gain amplifier, 22 is a threshold level setting circuit, and 23 and 24 are volumes for setting the threshold level.

The muse signal from the input terminal 15 passes through the buffer circuit 18 and is sent to the input terminal 1 by the clamp circuit 19.
After being clamped by a clamp pulse from 7, the signal is guided to a variable gain amplifier 21 via a buffer circuit 20. Threshold level setting circuit 2
In step 2, the threshold level of the variable gain amplifier 21 is determined according to the set values of the volumes 23 and 24. In the variable gain amplifier 21, when the absolute value |Vi| of the input signal voltage is smaller than the set threshold voltage Vs, the gain is reduced to perform non-linear de-emphasis. The output from the variable gain amplifier 21 is led from the output terminal 16 to a de-emphasis circuit on the frequency axis.

Generally, the clamp pulse is created by counting the VCO output signal, so VCO13
If the oscillation frequency is not phase-locked to the horizontal synchronization signal (HD), the clamp pulse will deviate from the predetermined position, and the DC component of the muse signal will change significantly depending on the clamp position. Even in this case, since the set values of volumes 23 and 24 do not change, the relative threshold of nonlinear de-emphasis changes, and correct non-linear de-emphasis is no longer applied. Therefore, the horizontal synchronizing signal (HD) and the frame pulse signal are distorted, the HD detection by the EPP detection circuit 11 and the PLL control circuit 12 is not performed correctly, and the frequency acquisition time in the PLL control circuit 12 becomes long.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned drawbacks of the conventional example in a decoder that returns a television signal that has been subjected to non-linear emphasis, such as a muse signal, to the original signal, and to reduce the phase lock of the PLL circuit section including the VCO. An object of the present invention is to provide a signal processing circuit that saves time.

[Summary of the invention] In order to achieve the above object, the present invention has the following features:
When the VCO output is not phase locked, either a switch circuit is provided after the variable gain amplifier 21 and the signal is output without passing through the variable gain amplifier 21.
Either change the threshold level of the threshold level setting circuit 22, or change the threshold level of the variable gain amplifier 2.
Fix the gain of 1, stop nonlinear de-emphasis, and prevent the waveform from being distorted.
Speed up the phase lock pull-in time of the PLL circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 1a.

In FIG. 1a, 25 is an input terminal for an out-of-lock signal, and 26 is an input terminal for an out-of-lock signal, and when the VCO output is not phase-locked, the signal from the buffer 20 is guided to the output terminal 16 without passing through the variable gain amplifier 21, and the phase is locked. When the variable gain amplifier is in use, the switch circuit for guiding the signal from the variable gain amplifier to the output terminal 16 and the rest are the same as in the embodiment shown in FIG.

The EPP detection circuit 11 outputs an out-of-lock signal when the frame pulse in the MUSE signal and the frame pulse generated by the internal counter are out of phase. The switch circuit 26 is controlled by this unlock signal, and if the phase is locked, the switch circuit 26 is connected in the opposite direction to that shown in FIG. 1a, and the circuit operates in the same way as the embodiment shown in FIG. . On the other hand, when the phase is locked, the switch circuit 26 is connected in the same direction as in FIG. stop. Therefore, even if clamping is not performed at the correct position, the waveforms of the horizontal synchronizing signal (HD) and frame pulse will not be distorted, and the EPP detection circuit 11
Frame pulses can be easily detected and phase lock can be pulled in quickly.

FIG. 1a shows another embodiment of the invention.

In FIG. 1b, 27 is a threshold level setting circuit 2 from which the threshold level setting volumes 23 and 24 are set when the phase is not locked.
The switch circuit for forcibly setting the voltage applied to the terminal 2 to a certain constant value Va, and the rest are the same as the embodiment shown in FIG. In this embodiment, when the phase is locked, switch circuit 27 is connected in the opposite direction as in FIG. 1b, and the circuit operates in the same manner as in FIG. 3. On the other hand, when the phase is not locked,
The switch circuit 27 of FIG. 1b is connected as shown. Threshold level setting circuit 22
determines the threshold level to be output to the variable gain amplifier 21 according to the input signal voltage from the switch circuit 27. However, when the phase is not locked, the input voltage to the threshold level setting circuit 22 is Va. Therefore, the threshold level of the variable gain amplifier 21 also becomes ±Va. In this case, by selecting Va to a value sufficiently large relative to the amplitude of the Muse signal, such as the power supply voltage Vc.c., the Muse signal will not exceed the threshold level, and even if the clamp shifts, the Muse signal will not exceed the threshold level. The gain of the variable gain amplifier 21 is always constant, and non-linear day emphasis is not applied.

FIG. 1c shows another embodiment of the invention.

In FIG. 1c, 28 is a switch circuit for cutting off the input from the threshold level setting circuit 22 to the variable gain amplifier when the phase is not locked, and the rest is the same as the embodiment shown in FIG.

When the phase is locked, the switch circuit 28
is connected in the opposite direction to that in FIG. 1c and operates in the same way as the embodiment in FIG. If the phase is not locked, the switch circuit 28 is connected in the same direction as shown in FIG.

The present invention is not limited to the circuit configuration of the embodiment shown in FIG. 1 or only to the Myuse signal, but is also applicable to a receiver that receives a signal with non-linear emphasis, such as a Myuse signal. .

〔Effect of the invention〕

According to the present invention, when the phase is not locked, the operation of the non-linear de-emphasis section included in the de-emphasis circuit is stopped, the detection of the horizontal synchronization signal (HD) and frame pulse signal is performed correctly, and the phase Lock retraction time is shortened.

[Brief explanation of drawings]

1a, b, and c are block diagrams showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of a Meuse type decoder, and FIG. 3 is a block diagram showing an embodiment of a nonlinear day emphasis system. FIG. 2 is a block diagram showing one embodiment of the circuit. 1... Input terminal for Muse signal, 2... Output terminal for R signal, 3... Output terminal for G signal, 4... B
Signal output terminal, 5... HD sync signal output terminal, 6... VD sync signal output terminal, 7... De-emphasis circuit, 8... A/D converter, 9...
Synchronization separation circuit, 10... Video signal processing circuit, 11
... EPP detection circuit, 12 ... PLL control circuit, 13 ... VCO, 14 ... internal synchronization generation circuit, 15 ... Muse signal input terminal, 16 ...
Output terminal of non-linear day emphasis circuit, 1
7... Clamp pulse input terminal, 18... Buffer circuit, 19... Clamp circuit, 20... Buffer circuit, 21... Variable gain amplifier, 22...
Threshold level setting circuit, 23, 24...variable resistor, 25...out-of-lock signal input terminal, 2
6, 27, 28... switch circuit.

Claims (1)

[Claims] 1. In a device that receives a video signal with positive polarity synchronization and processes the signal, at least a de-emphasis circuit detects a vertical or horizontal synchronization signal inserted in the video signal and locks the phase. A synchronization detection circuit that detects
A voltage controlled oscillator circuit, a PLL control circuit to lock the oscillation frequency of the voltage controlled oscillator circuit to the horizontal synchronizing signal (HD) of each line, and a synchronization generation circuit to generate a new synchronizing signal from the output signal of the voltage controlled oscillator circuit. If the de-emphasis circuit includes a non-linear de-emphasis circuit in which the amount of de-emphasis changes depending on at least the amplitude level, and the oscillation frequency of the voltage-controlled oscillator circuit is not phase-locked to the horizontal synchronizing signal (HD). A de-emphasis circuit characterized in that the non-linear de-emphasis in the non-linear de-emphasis circuit is stopped and the non-linear de-emphasis is performed only when the phase is locked.