JPH0553030B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A sequencer circuit included in an adapter that controls information processing operations of a connected storage device, and a processing control circuit that executes control corresponding to commands from a host device. In the storage means for storing detailed signals necessary for operating the circuit, information identifying whether or not the command from the host device is normal to set the detailed signal to the processing control circuit is added to the command code. By storing the data in the area specified by the corresponding processing start address and setting the processing control circuit according to the correct/incorrect identification based on the identification information, an inexpensive and highly reliable sequencer circuit can be realized. It becomes possible.

[Industrial application field]

The present invention relates to an adapter that controls the operation of a storage device under control according to instructions from a host device.
In particular, the present invention relates to a sequencer circuit that creates and sets detailed signals for executing operations of an internal adapter processing control circuit.

For example, the operation of a drive used as an external storage device of an information processing system is controlled in response to a command from a host device (for example, the above-mentioned control device).
The adapter controls the appropriate drive.

This adapter puts multiple drives under control and is comprised of a sequencer circuit that creates detailed signals according to command codes from a host device, and a hardware circuit (processing control circuit) that controls the drives.

The creation and setting of various detailed signals for this hardware circuit (processing control circuit) to execute control is generally performed by a sequencer circuit, and in order to accurately control the drive based on instructions, the hardware circuit It is desired to quickly process a set of various detailed signals of a processing control circuit (processing control circuit) based on accurate information.

[Problems to be solved by conventional technology and invention]

FIG. 2 is a block diagram illustrating a conventional example, and FIG. 3 is a diagram illustrating the configuration of a drive system.

The system diagram in Figure 3 shows the predetermined drives 3(0) to 3(n), 4(0) to
4(n) control command is sent to the adapters 2a to 2.
Based on the disk control devices (hereinafter referred to as DKCs) 1a and 1b that control operations according to commands via d, and the instruction codes from the DKCs 1a and 1b,
Predetermined drives 3(0) to 3(n), 4(0) to 4
(n) Adapter (hereinafter referred to as
ADP) 2a to 2d, and drives (hereinafter referred to as ADP) that perform data read/write operations based on operation instructions from ADP2a to 2d
(referred to as DKU) 3(0)~3(n), 4(0)~
4(n).

In addition, Fig. 2 shows a block diagram of a conventional example of ADP2a to 2d (in Fig. 2, numerals 2a to 2d are collectively represented by numeral 2), and DKC1a, 1b (in Fig. 2, numerals 1a and 1b are collectively represented by numeral 2). A tag decoder circuit 20 detects an instruction issuing tag from a tag (represented by reference numeral 1); and a tag decoder circuit 20 that detects an instruction issuing tag from a tag (represented by reference numeral 1); counter 24
The sequencer control circuit 21 gives operation instructions to the DKC1.
A bus-out register 22 that captures and stores bus-out information from the computer, and a memory (ROM) 23 that stores the start address and error processing address for each instruction.
(also referred to as mapping memory), an address counter 24 that stores information sent from the memory (ROM) 23, and a memory (ROM) that stores detailed signal information for the processing control circuit 26 to control processing corresponding to instructions. ) 25, tag decoder circuit 20, sequencer control circuit 2
1. Bus out register 22, memory (ROM)
23, 25, a sequencer circuit 30 consisting of an address counter 24, and detailed signal information sent from a memory (ROM) 25, various sets of hardware parts (sets for executing control corresponding to instructions) are performed.
It is composed of a processing control circuit 26 that performs the following.

In addition, the code a shown in FIG. 2 is an information lead that notifies error information, and the code b is a DKU3 (0) to 3.
(n), and signal information read to 4(0) to 4(n), respectively.

In the conventional sequencer circuit 30 configured as described above, when the tag decoder circuit 20 detects an instruction issuing tag from the DKC 1, it notifies the sequencer control circuit 21 through the signal line c.

As a result, the sequencer control circuit 21 instructs the bus-out register 22 to take in bus-out information, and stores the information in the memory (ROM) 23 indicated by the value stored in the bus-out register 22 in the address counter 24. .

Note that the memory (ROM) 23 stores the start address of the memory (ROM) 25 that stores detailed signal information for the processing control circuit 26 corresponding to each command from the DKC 1, and an error processing information that stores error processing information. address is stored.

Further, when a regular instruction is stored in the bus-out register 22, a processing address for accessing the memory (ROM) 25 area storing detailed signal information corresponding to the instruction is sent to the address counter 24. Ru.

If an incorrect instruction is sent to the bus out register 22,
When the error processing address is stored in the address counter 24, the error processing address is sent to the address counter 24.

The memory (ROM) 25 is accessed by the address stored in the address counter 24, and each hardware part in the processing control circuit 26 is set according to the read detailed signal information, and based on this, the corresponding DKU3(0) to 3( n), 4(0)~4
(n) will be controlled.

As mentioned above, the conventional sequencer circuit 30 uses two types of memories (ROM) 23 and 25 to set detailed signals in the processing control circuit 26, which increases the cost and makes it relatively slow. Since two types of memories (ROM) 23 and 25 with low reliability are used, there are problems such as a decrease in reliability.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating an embodiment of the invention.

This block diagram consists of the DKC 1 and the adapter 2 explained in FIG. Detailed signal information set by the counter 24 and the processing control circuit 26 to perform operations in accordance with commands from the DKC 1;
A storage means (memory) 25' that stores an identification code for identifying whether the instruction of the processing start address corresponding to the instruction code is normal or abnormal, and signal information for the processing control circuit 26 to perform error processing. , usually selects information from the bus out register 22 and outputs the control signal e from the sequencer control circuit 21.
The selection means (hereinafter referred to as MPX) 27 for selecting information from the error processing address section 29 and the identification code included in the information output from the storage means (memory) 25' are read, and the processing start address corresponding to the instruction is read. The processing start address identifying means (circuit) 28 discriminates between normality and abnormality, and the error processing address sending means (error processing address section) 29 outputs an error processing address.

[Effect]

Identification for identifying whether the instruction of the processing start address corresponding to the instruction code is normal or not in the detailed signal information stored in the storage means (memory) for the processing control circuit to perform control processing according to the instruction from the DKC. By adding a code, the identification code output from the storage means (memory) is taken into the processing start address identification means (circuit), and accessed from the sequencer control circuit to identify whether the processing start address is normal or not. By configuring this, the number of memory (ROM) used can be reduced, making it possible to realize an inexpensive and highly reliable sequencer circuit.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG. Note that the same reference numerals indicate the same objects throughout the figures. Further, symbols c to i in the figure indicate signal lines within the sequencer circuit 30'.

Next, the sequencer circuit 30' in this embodiment
We will explain the processing operations within.

When the tag decoder circuit 20 detects that a command is issued from the DKC 1, the sequencer control circuit 21 is notified through the signal line c.

The sequencer control circuit 21 stores bus-out information in the bus-out register 22 through the signal line d, and stores information sent from the bus-out register 22 through the signal lines e and f into the address counter 2.
Set to 4.

Address counter 24 sends this information to memory (ROM) 25' as a processing start address corresponding to the instruction code. Memory (ROM) 2
5' outputs predetermined information from the area corresponding to the processing start address value output from the address counter 24, and takes in the identification code in this information to the processing start address identification circuit 28 through the signal line i.

The sequencer control circuit 21 is an address counter 2
4 stores the next information from the bus out register 22, the process start address identifying circuit 28 determines the identification code through the signal line h, and the result is taken in through the signal line g.

If the processing start address is identified as normal, a detailed signal sent from the memory (ROM) 25' is set in the processing control circuit 26, and a predetermined DKU3 (0) is sent through the signal line b by an operation according to the setting.
~3(n), 4(0) ~4(n) are controlled.

If an abnormality is identified at this time, signal lines e and f
The MPX 27 and address counter 24 are controlled through the error processing address section 29.
The information from the address counter 24 is sent to the address counter 24, and the address counter 24 sets the information.

Memory (ROM) 25' is address counter 2
The address sent from DKC1, that is, the error processing address area, is accessed, and the error processing information stored there is set in the processing control circuit 26. Based on this set, the processing control circuit 26 transmits the error information DKC1 through the signal line a. Notify.

〔Effect of the invention〕

According to the present invention as described above, the number of memories (ROMs) used is reduced, and an inexpensive and highly reliable sequencer circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining an embodiment of the present invention, FIG. 2 is a block diagram explaining a conventional example, and FIG.
The figures each show a diagram explaining the configuration of the drive system. In the figure, 1, 1a, 1b are DKC, 2, 2
a to 2d are ADP, 3(0) to 3(n), 4(0)
~4(n) is DKU, 20 is tag decoder circuit,
21 is a sequencer control circuit, 22 is a bus out register, 23, 25, 25' are memories (ROM),
24 is an address counter, 26 is a processing control circuit,
27 is MPX, 28 is a processing start address identification circuit, 29 is an error processing address section, 30, 3
0' indicates a sequencer circuit.

Claims (1)

[Claims] 1. A processing control circuit 26 that controls the storage device to execute operations corresponding to instructions from the host device 1.
is an incrementable sequencer circuit 30' that creates various signal information necessary for executing a control operation by identifying the command from the host device 1, and sets it in the processing control circuit 26. Address counter means 2
4, storing identification information for identifying whether the processing start address corresponding to the instruction code from the host device 1 is normal or abnormal, various signal information for setting the processing control circuit 26, and error processing information. Normally, the output information from the bus out register 22 is selected, and when a predetermined signal e from the sequencer control circuit 21 is received, the output information from the error processing address means 29 is selected. Selection means 27
and processing start address identification means 28 which reads the identification information sent from the storage means 25' and identifies whether the processing start address is normal or abnormal according to instructions from the sequencer control circuit 21, and into the storage means 25'. error processing address sending means 29 for sending an address of error processing information to be stored; setting the processing start address value in the address counter means 24 in response to the command sent from the host device 1; The processing start address identification means 2 stores the identification information stored in the storage means 25' indicated by the counter means 24.
8, determines whether it is normal or abnormal, and if normal, increments the address counter means 24 and continues setting the signal information to the processing control circuit 26, and if abnormal, selects the signal information. By switching the means 27, the error processing information address value sent from the error processing address sending means 29 is set in the address counter means 24, and the processing control circuit 2
A sequencer circuit characterized in that various signal information for error processing is set to 6.