JPH0552521B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides a static var power compensator that compensates for reactive power in a power system in stages by increasing or decreasing the number of banks of capacitors connected to the power system. Regarding the control method.

[Conventional technology]

As the demand for electricity increases, the power system is expanded and
As power transmission lines become longer and have larger capacities, the inductance of circuits also increases. As a result, it becomes difficult to maintain the voltage stability of the power system when the power supply or load is cut off, or when a system fault occurs, such as a ground fault. Therefore, by providing a phase modifier in the middle of the power system and controlling the reactive power at the point where the phase modifier is installed, it is possible to maintain the voltage at this installation point and improve system stability.

Using a synchronous phase modifier as a phase modifier to compensate for capacitive reactive power has drawbacks in operational speed and maintainability, so a circuit breaker is often used to control the opening and closing of capacitor banks connected in parallel to the power grid. However, this also has the disadvantage of shortening the life of the circuit breaker if it is operated frequently. Therefore, at present, static var power compensators are being used, which consist of parallel-connected semiconductor switches (mainly thyristor switches) and multiple sets of capacitor banks whose opening and closing are controlled by the semiconductor switches connected in parallel to the power system. It's getting old.

Figure 1 is a circuit diagram showing a conventional example of the above-mentioned static var power compensator and its control circuit, in which opening and closing of four sets of capacitor banks are controlled. The three-phase circuit part is shown as a single line.

In FIG. 1, four sets of capacitor banks, namely a No. 1 capacitor bank 10, a No. 2 capacitor bank 20, a No. 3 capacitor bank 30, and a No. 4 capacitor bank 40, are connected to the power system 1 through a circuit breaker 9. . Here, each capacitor bank 10, 20, 30, 40 is a three-phase capacitor, and each capacitor bank has thyristor switches 11, 2 connected in antiparallel for each phase.
Since thyristor switches 1, 31, and 41 are connected in series, when the thyristor switch 11, 21, 31, and 41 is turned on, the corresponding capacitor bank is connected to the power system 1, and when it is turned off, the corresponding capacitor bank is disconnected. It will be.

On the other hand, an instrument transformer 2 and a rectifier 3 for rectifying the output of the transformer 2 are connected to the power system 1, and the actual voltage value of the power system 1 is detected. The value is output. The deviation voltage between this actual voltage value and the voltage target value is calculated at the addition point 6, and is inputted to the comparators 13, 23, 33, 43 via the voltage regulator 7. Since the operating voltages set by the operating voltage setters 12, 22, 32, and 42 are input to these comparators 13, 23, 33, and 43, respectively, the above-mentioned deviation voltage and this operating voltage setting value match. When the output from the comparators 13, 23, 33, 43 causes the pulse generators 14, 24, 34, 44 to
is operating and thyristor switches 11, 21, 3
Turn on 1,41.

For example, if the setting voltage of the operating voltage setting device 12 is -E
and the operating voltage setter 22 sets a voltage twice this -
2E, and also the operating voltage setting devices 32 and 42.
are set to three times the voltage -3E and four times the voltage -4E, then when the actual voltage value of the power system 1 decreases and the deviation from the voltage target value reaches -E, the comparator 13 will Working thyristor switch 11
is turned on, and the No. 1 capacitor bank 10 is connected to the power system 1. At this time, the operating voltage setter 12 is set so that the actual voltage value of the power system 1 recovers approximately to the voltage target value due to the phase advance capacity of the No. 1 capacitor bank 10. Furthermore, the deviation voltage mentioned above is −
When it reaches 2E, the comparator 23 also operates following the comparator 13, and the No. 1 capacitor bank 10
and No. 2 capacitor bank 20 are connected to power system 1, and if the actual voltage value decreases significantly and the deviation voltage becomes -4E, capacitor banks No. 1 to No. 4 capacitor banks 10, 20, 30, 40 are connected to power grid 1. will all be connected to the power system 1.

As described above, the required number of banks of capacitors are connected to the power system 1 and the voltage of the power system 1 is restored, so the deviation voltage becomes zero and the capacitor banks connected to the power system 1 are disconnected again. In order to prevent this, the bias voltage from the bias voltage setter 5 is added to the addition point 6. In other words, when the actual voltage value is lower by E than the voltage target value, the deviation voltage becomes -E, the comparator 13 is activated, the No. 1 capacitor bank 10 is connected in parallel to the power system 1, and the voltage of this power system 1 is That is, the actual voltage value increases and the above-mentioned deviation voltage returns from -E to zero. However, since the comparator 13 simultaneously closes the normally open bias contact 51, the set voltage from the bias setting resistor 55, whose output voltage is set to -E, is passed through the adder 59 to the addition point 6. As a result, the deviation voltage input to the comparator 13 becomes -E, and the No. 1 capacitor bank 10 remains connected to the power system 1.

The bias voltage setter 5 includes, in addition to a bias contact 51 operated by the comparator 13, bias contacts 52, 53, and 54 that are opened and closed separately in accordance with the operation of the comparators 23, 33, and 43, an adder 59, and these bias contacts. It is composed of bias setting resistors 55, 56, 57, and 58 that supply a bias setting voltage to the adder 59 through contacts.
6, 57, and 58 are each set to a voltage of -E. Therefore, if the voltage of the power system 1 fluctuates greatly and the deviation voltage becomes -4E, the signals from the four sets of comparators 13, 23, 33, 43 will cause capacitor banks 10, 20, 30,
40 are all connected to the power system 1, but at the same time four sets of bias contacts 51, 52, 5
3 and 54 are closed, and the output of the adder 59, that is, the output of the bias voltage setter 5, becomes -4E.
Each capacitor bank 10, 20, 30, 40 remains connected to the power grid 1.

If the voltage of power system 1 rises above the voltage target value, the value of the deviation voltage changes toward zero, contrary to the above, so the capacitor bank is connected from power system 1 in the order of No. 4 → No. 3 → No. 2. Will be disarranged. In addition, each comparator 13, 23, 33, 43 has hysteresis in its operation, and the thyristor switch 11, 2
1, 31, and 41 are prevented from frequently repeating on/off operations.

Figure 2 is a graph showing the number of operating banks of capacitors, where the horizontal axis represents the deviation voltage and the vertical axis represents the number of operating banks.As shown by the broken line Y, the deviation voltage increases from -E to -2E. In response to this, the number of operating banks has also increased.

[Problem to be solved by the invention]

By the way, in the conventional circuit as shown in FIG.
As shown by the two-dot chain line Z in the figure, when the voltage of the power system drops and the deviation voltage becomes -2E, the first bank, that is, the No. 1 capacitor bank 10, is operating, but the second capacitor bank It is clear from the above explanation that the No. 2 capacitor bank 20 does not enter operation, and when the deviation voltage reaches -3E, the No. 3 capacitor bank 30 enters operation as the second unit. be. That is, if there is a capacitor bank that is excluded from operation and is inactive, the conventional circuit may not be able to connect the necessary number of capacitor banks to the power system 1, and therefore has the disadvantage that reactive power compensation is insufficient.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control system for a static var power compensator that allows a required number of capacitor banks to be connected to a power system even if some capacitor banks are inactive.

[Means to solve the problem]

In order to achieve the above object, in the present invention, the deviation voltage between the actual voltage value and the voltage target value of the power system is set to the operating voltages individually set for a plurality of capacitor banks whose operating order is determined in advance. When a match occurs, the capacitor bank corresponding to the matching voltage is connected to or disconnected from the power system, and a static reactive power compensator is controlled to add or subtract a bias voltage corresponding to the capacity of the operating capacitor bank to or from the deviation voltage. For the device, when the deviation voltage matches the operating voltage of the resting capacitor bank in the plurality of capacitor banks,
A first partial circuit that transfers an operating signal to a capacitor bank whose operating order is next to the inactive capacitor bank based on the deviation voltage and a bank inactive signal indicating the inactive capacitor bank; A second partial circuit for adding a bias voltage corresponding to the capacitance of the idle capacitor bank to the deviation voltage based on the above is provided.

[Effect]

By using the above technical means, when it is the turn of an inactive capacitor bank to operate, this operation command is transferred to the next operating capacitor bank after the inactive capacitor bank, and the capacitance of the inactive capacitor bank is handled. By generating a bias voltage that increases the deviation voltage, the actual voltage value is apparently lowered, and the capacitor bank of the next rank is operated, thereby securing the number of capacitor banks necessary to maintain the voltage of the power system.

〔Example〕

FIG. 3 is a basic circuit diagram showing an embodiment of the present invention. In this figure, the voltage of the power grid 1 is applied to the summing point 6 as an actual voltage value by the voltage transformer 2 and the rectifier 3, and the voltage target value from the grid voltage setting device 4 is also applied to the summing point 6. However, the bias voltage from the bias voltage setter 5 is also applied to the addition point 6. At this addition point 6, the deviation between the actual voltage value and the voltage target value is calculated, and this deviation voltage is given to four sets of comparators 13, 23, 33, and 43 via the voltage regulator 7. The operating voltages input from the operating voltage setters 12, 22, 32, and 42 are compared with the above-mentioned deviation voltage, and when the two voltages match, the output of the comparator is sent to the pulse generator via the capacitor bank selection circuit 60. 1
4, 24, 34, 44. Thyristor switches 11, 21, 3 (not shown) are activated by the output of the pulse generators 14, 24, 34, 44.
1 and 41 (see Figure 1) are turned on and off, and capacitor banks 1 to 4 (not shown)
0, 20, 30, and 40 (see FIG. 1) are connected to or disconnected from the power grid 1.

The bias voltage setter 5 includes four bias setting resistors 55 to 58 for setting the bias voltage, four bias contacts 51 to 54 for separately transmitting the bias voltage set by these to the adder 59,
It consists of an adder 59 that adds and outputs these bias voltages, and bias contacts 51 to
The opening and closing of 54 is controlled by a capacitor bank selection circuit 60. The bias voltage output from the bias voltage setter 5 is added to the above-mentioned deviation voltage at the addition point 6, as in the conventional example shown in FIG.

If the set voltage of the operating voltage setter 12 is -E, and the set voltages of the operating voltage setters 22, 32, and 42 are -2E, -3E, and -4E, respectively, then the power system 1
As the voltage decreases, the capacitor bank changes from No. 1 to No. 2.
No. → No. 3 → No. 4 are connected to power system 1 in the order,
Next, when the voltage increases, the number 4 → number 3 → number 2 → number 1 will be disconnected in the order. If it is desired to change the order in which the capacitor banks are connected and disconnected, the magnitude relationship between the set voltages of the operating voltage setters 12, 22, 32, and 42 may be changed. Furthermore, as mentioned above, since the capacitor banks are connected and disconnected at every voltage step E, four sets of bias setting resistors 5
5 to 58 are each set to a bias voltage of -E.

FIG. 4 is a partial circuit diagram showing a portion of the logic circuit constituting the capacitor bank selection circuit 60. In FIG. 4, 15, 25, 35, and 45 are comparator signal input terminals, and the terminal 15 is connected to the output side of the comparator 13, and the deviation voltage input from the voltage regulator 7 to the comparator 13 is When the voltage is lower than the set voltage -E set by the operating voltage setter 12, the comparator 13
The output is a logic 0, but the deviation voltage outputs a logic 1 which is larger than -E, and this logic signal is input to the terminal 15. Similarly, the output signal of the comparator 23 is applied to the terminal 25, and the comparators 33 and 43 are applied to the terminals 35 and 45, respectively.
An output signal of is applied.

16, 26, 36, and 46 are bank suspension signal input terminals, and when the No. 1 capacitor bank 10 is out of operation, a logic 1 signal is input to the terminal 16, but when the No. 1 capacitor bank 10 is in operation. At this time, a logic 0 signal is input to this terminal 16. Similarly, No. 2 capacitor bank 2 is connected to terminal 26.
A signal indicating whether operation is possible or not is input from 0, and similar signals are input from capacitor banks No. 3 and No. 4 to terminals 36 and 46, respectively.

17, 27, 37, and 47 are pulse generator drive signal output terminals that output signals to the pulse generators 14, 24, 34, and 44, respectively, and are used to connect a thyristor switch to connect the capacitor bank to the power system 1. When it is desired to turn on, a logic 1 signal is output from the terminal corresponding to that capacitor bank. In addition, from 61 to 76
AND element, 91 to 98 are OR elements, 111
to 114 are NOT elements.

As described above, when the deviation voltage input to the comparator 13 becomes -E, the output of the comparator 13, that is, the input to the input terminal 15 changes from logic 0 to logic 1. At this time, if the No. 1 capacitor bank 10 is operable, the input signal of the input terminal 16 is logic 0, and the output of NOT element 111 is logic 1. Therefore, the output of AND element 73 is logic 1.
Therefore, the No. 1 capacitor bank 10 is connected to the power system 1
connected to.

Despite this, if the voltage of the power system 1 further decreases and the deviation voltage increases to -2E, the output of the comparator 23 also changes from logic 0 to logic 1.
At this time, if the No. 2 capacitor bank 20 is operational, the No. 2 capacitor bank 20 is connected to the power system 1 in the same manner as described above, but if the bank 20 is inactive, the input terminal 2
Since logic 1 is input to 6, NOT element 1
The output of 12 will be a logic zero. Therefore, AND element 7
4 becomes logic 0, and the output of the command to connect the bank 20 to the power grid 1 is blocked. However, since the two sets of input signals of the AND element 64 are both logic 1, the logic 1 signal output from the AND element 64 is the same as that of the OR element 93 and the OR element 97.
It is output from the output terminal 37 via the AND element 75 and connects the No. 3 capacitor bank 30 to the power system 1. In other words, when you want to operate the No. 2 bank 20, if this No. 2 bank 20 is inactive,
The No. 3 bank 30, which is next in operation order, is operated. At this time, if the No. 3 bank 30 is also inactive, the No. 4 bank 40, which is next in operation order, will be operated.

FIG. 5 is a second partial circuit diagram of the logic circuit constituting the capacitor selection circuit 60, and a portion of the circuit shown in FIG. 5 is overlapped with the circuit shown in FIG. 4. In other words, 25 is converter 2
It is a signal input terminal from 3, and 16, 26, 3
Reference numerals 6 and 46 are bank suspension signal input terminals, and the state of the input signal is the same as that already explained in FIG. Furthermore, AND elements 64, 65, and 66 are also already shown in FIG.

In FIG. 5, 18, 28, 38, and 48 are bank operation signal input terminals, and when the No. 1 capacitor bank 10 operates and is connected to the power system 1, the input signal at the terminal 18 becomes logic 1. . Similarly, terminals 28, 38, and 48 are No. 2, No. 3, and No. 4, respectively.
When the capacitor bank 20, 30, 40 of the number is connected to the power system 1, it becomes logic 1, and otherwise it becomes logic 0.

Reference numerals 19, 29, 39, and 49 are bias contact drive signal output terminals, and the bias contact 51 from which a logic 1 is output from the output terminal 19 is closed, and when the logic is 0, the bias contact 51 remains open. be. Similarly, output signals from terminals 29, 39, and 49 drive bias contacts 52, 53, and 54, respectively. Also, 77 to 80 are AND elements, 9
9 to 101 are OR elements.

In order to avoid complicating the circuit diagram, only the circuit for the signal input from the comparator 23 to the terminal 25 is shown in FIG. The circuit has a configuration similar to that shown in FIG.

In FIG. 5, when the output of the comparator 23, that is, the input of the terminal 25 switches from logic 0 to logic 1, if the No. 2 capacitor bank 20 is in an operable state, the capacitor bank 20 is connected to the power system 1. and a logic 1 signal is output to terminal 28.
Input from Therefore, the output of AND element 77 becomes logic 1, and a logic 1 signal is output from terminal 29 via OR element 99, thereby closing bias contact 52. At this time, since the bias contact 51 is already closed due to the operation of the No. 1 capacitor bank 10, the bias voltage setter 5 outputs a bias voltage of -2E, and the comparators 13, 23, 33, 43 output a bias voltage of -2E. The applied deviation voltage is also -2E, and the No. 1 and No. 2 capacitor banks 10
and 20 remain operational.

When a logic 1 signal is input from terminal 25, 2
If capacitor bank 20 is inactive,
As already mentioned, this logic 1 signal is transferred to the No. 3 capacitor bank 30 in the next operation order and operates the No. 3 capacitor bank 30. A logic 1 signal is input to the terminal 38,
Since the AND element 64 outputs logic 1,
The logic 1 signal output by AND element 78 is output by OR element 9
9 to terminal 29, and via OR element 100 to terminal 39, bias contacts 52 and 5
3 is closed, and bias contact 5 is already closed.
1 and the bias voltage setter 5 outputs a bias voltage of -3E. In other words, there are only two sets of capacitor banks No. 1 and No. 3 in operation, but the bias voltage is -3E, and if the voltage drop in the power system increases further, the No. 4 capacitor bank 40 will be able to continue operating. be.

〔Effect of the invention〕

According to this invention, the reactive power of the power system is controlled by a plurality of capacitor banks whose order of connection and disconnection to the power system is determined in advance in accordance with the magnitude of the deviation voltage between the voltage target value and the actual voltage value. In a compensating device, when a capacitor bank that is inactive has its turn to operate, this operation command signal is transferred to the next capacitor bank in the operating order to operate this capacitor bank, and at the same time, the capacitor bank that is inactive Since it is designed to generate a bias voltage corresponding to the capacitor bank and the capacitance of the capacitor bank operated by carrying forward,
Even if some capacitor banks are inactive, the necessary number of capacitor banks can be connected to the power system in response to fluctuations in the actual voltage value, so there is an advantage that the reactive power compensation operation can be performed smoothly.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional static var power compensator, FIG. 2 is a diagram showing the relationship between deviation voltage and the number of operating banks, FIG. 3 is a basic circuit diagram showing an embodiment of the present invention, and FIG. This figure is a first partial circuit diagram of the capacitor bank selection circuit of the basic circuit of FIG. 3, and FIG. 5 is a second partial circuit diagram of the capacitor bank selection circuit. 1...Power system, 2...Instrument transformer, 4...
System voltage setting device, 5...Bias voltage setting device, 7
... Voltage regulator, 9... Circuit breaker, 10... No. 1 capacitor bank, 20... No. 2 capacitor bank, 30... No. 3 capacitor bank, 40... 4
No. capacitor bank, 60... Capacitor bank selection circuit, 11, 21, 31, 41... Thyristor switch, 12, 22, 32, 42... Operating voltage setter, 13, 23, 33, 43... Comparator, 14 , 24, 34, 44... Pulse generator, 15, 25, 35, 45... Comparator signal input terminal, 16, 26, 36, 46... Bank suspension signal input terminal, 17, 27, 37, 47...
Pulse generator drive signal output terminal, 18, 28, 3
8, 48... Bank operation signal input terminal, 19, 2
9, 39, 49...Bias contact drive signal output terminal, 51-54...Bias contact, 55-58...
...Bias setting resistor, 59...Adder, 61-7
6...AND element, 77-80...AND element, 9
1 to 98...OR element, 99 to 101...OR element, 111 to 114...NOT element.

Claims (1)

[Scope of Claims] 1. When the deviation voltage between the actual voltage value and the voltage target value of the power system matches the operating voltage individually set for each of a plurality of capacitor banks whose operating order is determined in advance, this coincidence occurs. In the control device for a static reactive power compensator, the control device for a static var power compensator is configured to cause a capacitor bank corresponding to a voltage to be connected to or disconnected from the power system, and to add or subtract a bias voltage corresponding to a capacity of the operating capacitor bank to or from the deviation voltage. When the deviation voltage matches the operating voltage of a resting capacitor bank among the plurality of capacitor banks, a capacitor whose operating order is next to the resting capacitor bank based on the deviation voltage and a bank resting signal indicating the resting capacitor bank. a first partial circuit that transfers an operating signal to the bank; and a second partial circuit that adds a bias voltage corresponding to the capacity of the idle capacitor bank to the deviation voltage based on the deviation voltage and the operating signal. A control device for a static var power compensator, comprising: