JPH05505024A - Semiconductor cavity device with lead wires - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Semiconductor cavity device with lead wires The present invention provides an electrode in the cavity and a lead wire (electric 1e) into the cavity. A semiconductor hollow bag equipped with ad)! In detail, the semiconductor The present invention relates to a method for manufacturing a cavity device.

The background of the invention and the invention are illustrated in the accompanying drawings: Figure 1 is a cross-sectional view of the body cavity apparatus, with two layers removed for better clarity. Referring now to FIG. 2, which is a plan view of the device of FIG. 1 with some parts removed.

The device shown in the figure can be manufactured in a known manner or by an improved method according to the invention as described below. can do. The device includes a pressure sensor and an acceleration sensor, as described below. It is known to have a wide range of uses as a meter.

The semiconductor cavity device of FIGS. 1 and 2 has a nonconducting support 3 (typically A diaphragm (d iaphragm). The support 3 supports a metal electrode 5a, which is , arranged between the semiconductor 1 and the support 3, starting from there, the semiconductor 1 It ends at a point beyond the edge of the circuit and is connected to an external circuit. The electrode 5a is Placed in an evacuated and hermetically sealed circular cavity 7 between the support 3 and the silicon 1 This arrangement is common in capacitive pressure sensors, accelerometers, etc. Ru.

In some cases, pressure or acceleration forces may cause the silicon 1 diaphragm to press down. (Glass 3 is relatively hard). Connected to an external measurement circuit to measure this capacitance. electrical feedthrough or lead A metal electrode 5a with wire 5b must be attached to the glass. For example, fi Provide an etched tunnel for the wire through, and then add gold to the tunnel. semi-conductor, such as a diffused feedthrough that provides a conductive glass tunnel filled with Many attempts have been made to seal feedthroughs in conductor devices.

Common problems faced by these approaches include large series resistance, lack of electrical insulation, and gas leakage paths, and complex and costly process steps that are highly uncertain. This is a real problem, resulting in high defect rates during manufacturing and unusable units. This will further increase costs.

In British patent application GB 2208754A, semiconductors (e.g. silicon) Fabricate an electrically insulating layer (e.g. silicon nitride) on the first side and have a large area compared to the first side. each with a feedthrough on a non-conductive support (e.g. glass) occupying a fabricate one or more electrodes, each with a feedthrough extending beyond the first surface; The silicon nitride layer is placed in contact with the glass so that it spreads, and the semiconductor layer is placed on the support. to provide a hermetic seal around the feedthrough, thereby allowing the semiconductor layer to and the support. For semiconductor cavity devices, overcoming the above-mentioned problems by It is proposed to provide a method of sealing.

Preferably, the bonding step is often anodic bonding. , Mallory bonding, or electrostatic bonding Field assisted bonding method This is achieved using g process). In this method, semiconductor sort and support are electrostatically attracted together at a suitable high temperature, and both the support and the insulating layer are soft. , so it is poured around the field and deformed to form an insulating layer and support. It is required that a bond be created between the two. “Coupling” between the field and the insulating layer ” is considered to be purely physical, but is nevertheless sensitive to cavities. A hermetic seal is provided.

Although electrostatic bonding forces are advantageous in ensuring cavity integrity, Therefore, a new problem arises. Electric power is sometimes passed through an insulating layer 4 at the point of generation. force sufficient to destroy the feedthrough from the becomes. This is a further cause of defective products. At the end of the manufacturing process The more value you add to the product, the more value you add to the product and the more you pay for any defective product. It is easy to understand that it costs a lot of money.

Therefore, in any manufacturing process, it is beneficial to reduce the defective rate, but In this joining process, which is the final assembly of conductor devices (pressure sensors, accelerometers, etc.) It is considered particularly desirable to reduce the defective rate in the manufacturing process.

Therefore, the present invention involves depositing metal in the form of lead wires and electrodes onto a non-conductive support. , then if necessary, not on the metal of the electrodes (including on the metal of the leads) , in the shape of the boundary of the cavity, providing an annular insulating layer and further insulating (preferably in vacuum) A semiconductor device is formed on top of the edge layer to define the remainder of the cavity and supports A voltage is applied between the body and the semiconductor to promote capacitive coupling between the insulating layer and the semiconductor. an electrode located in the cavity and extending into the cavity in electrical continuity with the electrode; Provides a new and improved method for manufacturing semiconductor cavity devices with lead wires do.

Further, when manufactured by the above method, the present invention provides an electrode existing in the cavity and the electrode. A semiconductor cavity device having electrically continuous lead wires extending into the cavity. We also provide a location.

The support is generally glass (e.g. silicoborate glass), preferably The glass has a coefficient of thermal expansion that matches that of a semiconductor, usually single crystal silicon. has. A material other than glass that is inexpensive, consistent, and has good characteristics. There isn't. A suitable proprietary glass has a suitably high volume resistivity against electrostatic coupling. Also has Corning 7070, Schott 824g, and Corning 1729. Of the three glasses mentioned above The last one is expensive but can be bonded at high temperatures (e.g. 600°C) ( ) and has a coefficient of thermal expansion compatible with silicon up to the above temperature. (Other glasses are no longer compatible above 400°C). Metal deposition is usually microelectronic techniques such as sputtering or evaporation in conjunction with photolithography. By well-established methods in the industry, for example This is done in+agevise to a thickness of ron.

Each electrode and each lead wire is made of chromium nickel coated with one of, for example, gold (Au). It may have a two-layer structure of NiCr layers. However, other metal combinations It is also possible to use alloys such as chromium or molybdenum instead of NiCr.

NiCr or chromium adheres very well to glass supports, while gold has low resistance. Provides an electrical path of resistivity. If you wish, NiCr, Cr, ^1. Mo, Ti.

or other suitable metals may also be deposited on the underside of the glass (e.g. by sputtering or evaporation). (emitting) to improve field uniformity during capacitive coupling.

The insulating layer is generally made of silicon dioxide 5i applied to a depth of 1 μm. 02 or silicon nitride Si3N4. The two metals are glass As for the gold It (i.e. the electrode leads), it is well and evenly deposited.

Si3N4 has an expansion coefficient that matches glass much better than 5i02 Ru. Mo is more preferable than NiCr in the above paragraph.

The insulating layer must not be too thick for good capacitive coupling. . Aside from that, the thicker the insulation layer, the better the electrical isolation between the electrode and lead wire. and the parasitic capacitance is It gets lower. Furthermore, if the insulating layer is thick, mechanical damage to the lead wire during capacitive coupling may occur. protection will be strengthened.

This protection reduces the failure rate due to broken leads. Support as cathode The capacitive bond with the body (eg glass) is strong enough to hermetically seal the cavity. shadow The pole extracts cations from the bonding surface of the glass that provides the immobile 8102 skeleton. vinegar.

Therefore, the concentration distribution of cations is a feature of the present invention, and 1-4 bonds and 4-3 bonds is the relative strength of

The other component involved in the capacitive coupling is the semiconductor 1, typically silicon.

As already mentioned, it is one side of the circular cavity 7 with a diameter of 2.5 mm and a depth of 1 μm. It constitutes a diaphragm (generally 400 μm thick) that forms the Diaph A better way to define the ram is, optionally, 25 μm deep by 250 μm diameter (0 , 25 mm) into the silicon.

The grooves allow the diaphragm to move more evenly, reducing bending and further reducing stray capacitance. Notans decreases.

The present invention will be described in detail below with reference to Examples.

silicone processing Boron-doped (0.01 Ωcm) Using 7 recon wafers, 3 inches in diameter and (111)-oriented, each with 4 250 devices of mm2 are manufactured. High conductivity makes the final device electrically Minimize the electrical dissipation and (111 ) Select the orientation to have a low temperature coefficient of elastic modulus.

First, an entire silicon wafer is deposited using plasma-enhanced chemical vapor deposition to a thickness of 0. Coat with a layer of 5 μm silicon dioxide. Next, the exposed circle (which will be groove 8) (optional) and finally an exposure grid that makes it easier to separate the device and opens the lead wire 5b. positive photoresist The aforementioned oxide layer is preserved patternwise by protect Remove exposed oxides using 7:1 buffered hydrofluoric acid (BHF). The silicon under the oxide is scraped out from the surface. Plasma By anisotropically etching using the maninotching method, the side plates and grids are almost perpendicular to each other. Create a groove with a depth of 25 μm. Using a gas mixture of 5iC14 and C1□ , Desired conditions shown below: Support temperature: 20°C High frequency power 40 watts (13,5611Hz) (R, F, Power) Flow rate of SiC14 28 sec (28 sec = standard temperature and standard pressure) (mass per minute given by a flow rate of 28 Ill/min) C12 flow rate 12SCCva Pressure: 40 millitorr We obtain the desired distribution under .

Under the above conditions, the silicon etching selectivity for the 5in2 mask is 1 It becomes 01. That is, the silicon etching rate is 10. 7 7 nm/min, whereas it is 106.7 nm/min.

Once the groove etching is complete, use 7:1 BHF (which does not attack the silicon) to , remove the remaining 5102 masking layer and clean the wafer in preparation for bonding. do.

glass processing Corning glass type 7070 is used in the form of a 3 inch diameter disc.

Mirror finish with parallel surfaces within ±1 μm and thickness controlled to 3 mm ±1 μm (front Polish the surface to a roughness of 25 r, m, s, ).

Glass 3 was washed with ultra-high water using sequential cleaning agents, deionized water, and absolute alcohol. Clean with sonic agitation. Next, the imagewise positive photographic plate (imagewis 250 areas 5 by positive photoresist) Cover the glass with photoresist, except for a-5b. Next, the DC magnet Using Ron sputtering (D, C, magnetron sputtering) Then, the glass disks are coated in a two-step integrated batch. The first layer is that Serves as a keying layer for the next 30nm gold layer It is made of 10 nm nichrome. Using acetone and ultrasonic vibrations, Lift-off processing of photoresist L, yields the desired glass metal coating pattern 5a15b. gala The base was recleaned and the entire surface was coated with 1 μm silicon nitride using plasma enhanced chemical vapor deposition. Covering: Support temperature 300℃ Pressure 650 millitorr 2%5iT14/98%N2 flow rate 2000scc+aN11I3 flow rate 14 　secm High frequency power 20 (13.56MHz for 7 seconds, then 187.5k for 1.5 seconds Hz, this was repeated until the desired thickness was obtained) This switching technique allows optimization resulting in a low tensile stress of 9.378 x 10' Nm-2. 1μm Once a thick silicon nitride layer is created, a suitable pattern of photoresist is applied to the nitride layer. Apply to the ion layer and etch using 7:1 BHF. This etching is does not affect the metallization of the metallization, but leaves behind the silicon nitride coating that defines the cavity 7. vinegar.

Any steps to be performed at this time are replaced along the circumference from narrow 5a-5b, and a contact on a platform (described later) spaced from 5b. on the upper surface (free surface) of the insulating coating 4 which is extended to form a pad. In contrast, a further step is to provide a metallization (not shown).

The final processing step for the glass was performed using DC magnetron sputtering. A (transparent) nichrome layer covering the entire backside ensures uniform capacitive bonding. This is the process of turning it into something. The glass is now ready for bonding. Ru.

Noricon/Glass bond When manufacturing a pressure sensor, glue 1 and glass 3 are bonded together in a vacuum. It is necessary to ensure a pressure-free reference cavity. Therefore, pumping with a turbomolecular pump Bonding is carried out using a chamber with a pressure of <10-' mbar.

Connect the Noricon 1 to be connected to XYZIlz (all axes can be moved and Micromanipulator (all axes can be rotated around axis Z) Attached to the stage (micro+aanjpulator stage) Place it on the surface plate. Mounted on a surface plate fixed above the manipulator stage, The turn surface (i.e. the surface with metal 5 and nitride 4) is facing toward the far direction (that is, all are upside down compared to FIG. 1). fixed You can see the glass through the hole in the center of the board. A binocular entity above the viewpoint Place the microscope.

After stopping the pump, heat 2 until both silicon 1 and glass 3 reach a temperature of 400℃. Heat two surface plates. Next, when viewed through a binocular stereomicroscope, two patterns can be seen. Using an XY and θ2 manipulator, place the silicon wafer so that the Align with glass. Then, using Z control, we can move the two parts together. do.

Apply a voltage of 4 kV across the two plates so that the silicon becomes the cathode. . This begins the bonding process, which takes 15 minutes to complete.

The bonding assembly is removed from the bonding rig. (child If necessary, at the desired pressure, the diaphragm should be deflected in its actual size. Overlap and grind Norikon 1 until the desired thickness is reached. ) Directly connect the coupling assembly. Reinstall the flow magnetron sputtering system and sputter the back side of the silicon. coated with µm aluminum and further treated with dry nitrogen at 450 °C for 15 min. to provide ohmic contact for subsequent lead installation. . However, as mentioned above, this aluminum coating process Omitted if the free surface of layer 4 was metallized before application to the free surface of layer 1. be able to. You can now dice the bonded assemblies and place each one in the pressure Now you are ready to use it as a server. However, when diced into 4mm Before making pills, use a 0.125mm diamond saw to control the depth. Cut the silicone and stop it within 15 μm of the nitride layer 4. pressure sensor When separating each piece by canting along a grid line with a width of 0.125 mm, Cut the plant home 315b to connect it to the external circuit ( width 0.5 mm), ensuring that the bonding pad 5b on the glass surface is exposed.

The semiconductor cavity devices of FIGS. 1 and 2 can be improved. When making improvements, The width of the platform 315a protruding along one side of the recon 1 is 0°5m. Spread the glass support so that it is 5 mm instead of m. This newly created table A surface is used to make the metallization at 5b more elaborate. For details, see the table above. The surface has discrete components and integrated circuit chips in the form of a die that are added later, and having external leads bonded to appropriate pads on the lath platform. It can form part of a thin layer hybrid circuit.

Silicon 1 can also be improved. That is, the diaphragm cavity faces An optional metal coating can be deposited on the surface and the grooves 8 can be omitted. The metal coating The cover emerges towards the platform via the path between the Noricon 1 and the insulator 4. Make ohmic contact with metal coating 9 (if metal coating is omitted, Noricon 1 , making an ohmic contact). spurious capacitance effect In order to avoid were arranged at a distance from paths 5a-5b. Such an arrangement The length of the home makes it possible.

The circuit at the front end is integrated into the pressure sensor so that it is electrically connected to the sensor. No separate hybrid circuit is required for this purpose. Therefore, packaging costs are reduced .

Furthermore, there is no bonding line on the back of Noricon; this is also an issue in packaging. is an advantage. For example, a wafer shape with a hole that fits into a circular cavity in the noricon. The glass disk of Kanji, which was suitably pretreated using the array (as shown in Figure 1), was sea urchin) can be attached to the top of the sea urchin. The glass is then (diced) act as a bonding surface (after mounting) and hold the assembly together when measuring pressure. can be done. This glass disk isolates the silicon from packaging stresses. In addition to isolating the circuit 11 from the pressure medium.

Under ultra-high pressure, the glass 3 under the annular insulator 4 will be much weaker compared to that under the cavity 7. (tends to be compressed; thereby creating an inelastic and therefore undesirable additional cavanotance changes occur. For the above uses, after all the above steps, The inelastic effect mentioned above can be minimized by thinning from the bottom, and the glass is bonded to a resiliently compressible Noricon support wafer (not shown). can be done.

international search report abstract The present invention involves depositing metal in the form of leads and electrodes onto a non-conductive support, and then Cavities should be placed on the support, including on the metal of the leads, but not on the metal of the electrodes if necessary. providing an annular insulating layer in the shape of a border, and further (preferably in vacuum) forming the insulating layer. a support and a semiconductor device formed thereon to define the remainder of the cavity; Applying a voltage between the semiconductor and the insulating layer to promote electrostatic bonding between the insulating layer and the semiconductor. an electrode in the cavity, including an electrode extending into the cavity in electrical continuity with the electrode; A method of manufacturing a semiconductor cavity device comprising lead wires is provided.

international search report m---h+11++11m1la pr〒1+':Q Qn/n)n'IQ S^　43135

Claims (6)

[Claims] 1. On a non-conductive support, metal is deposited in the form of leads and electrodes, and then the required On the support, including on the metal of the lead wire, but not on the metal of the mule electrode, the boundary of the cavity providing an annular insulating layer in the form of a wire and further (preferably in vacuum) on top of the insulating layer; Place the formed semiconductor to define the remainder of the cavity and connect the support and semiconductor. It involves applying a voltage between the insulating layer and the semiconductor to promote capacitive coupling between the insulating layer and the semiconductor. an electrode in the cavity, and a link extending into the cavity that is electrically continuous with the electrode. A method of manufacturing a semiconductor cavity device comprising a wire and a wire. 2. A method according to claim 1, wherein the support is glass. 3. 3. The method according to claim 2, wherein the glass and the semiconductor are selected such that their coefficients of thermal expansion match. . 4. A method according to any preceding claim, wherein the semiconductor is single crystal silicon. 5. According to any preceding claim, the insulating layer is SiO2 or silicon nitride Si3N4. How to put it on. 6. When manufactured by the method according to any one of claims 1 to 5, the electrode existing in the cavity and the electrode A semiconductor cavity device having a pole and a lead wire extending into the cavity in electrical continuity. Place.