JPH0548469A - Parity error detection circuit - Google Patents

Abstract

PURPOSE:To realize the small sized inexpensive parity error detection circuit which outputs a parity error detection output of N channels in n-bit parallel as an NXn bit serial data altogether with respect to the parity error detection circuit for an N channel input data each receiving n-bit parallel data. CONSTITUTION:The detection circuit is provided with parity arithmetic operation circuits 11-1N calculating the parity for each bit of n-bit parallel input data, comparator circuits 21-2N comparing respectively the parity for each n-bit calculated by the parity arithmetic operation circuits 11-1N with each parity in n-bit written in an input data, and parallel/serial conversion circuits 31-3N converting the n-bit parallel data outputted from the comparator circuits 21-2N into a serial data and converting the N-channel n-bit serial data into an NXn bit serial data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity error detection circuit obtained from N-channel input data, one channel of which is n-bit parallel input.

With the progress of digital communication, the communication speed is increasing and the amount of data multiplexed therein is also increasing. FIG. 6 is a diagram for explaining an example of a frame format of digital communication, and SD recommended by CCITT.
The frame format of H (Synchronous Digital Hierarchy) is shown. One subframe consists of 90 bytes,
One multi-frame is composed of 9 sub-frames, and data is input / output in 8-bit parallel.

Further, the first 3 bits of each sub-frame is an overhead byte, and the parity calculation result obtained on the transmission side is written and transmitted at the position of B2 byte shown in the figure.

At the receiving side, the parity of the input data is obtained by the parity arithmetic circuit, and the parity arithmetic result obtained at the receiving side is compared with the parity arithmetic result obtained at the transmitting side which is written at the position of B2 byte to compare the parity error. Is being detected.

In the transmission of digital data, N pieces of data in a frame format as shown in FIG. 6 are transmitted in parallel to improve communication efficiency. It is required to realize such a parity error detection circuit for multiplexed digital data at a small size and at a low cost in order to downsize a communication device.

[0006]

2. Description of the Related Art FIG. 7 is a diagram for explaining a conventional example. The figure shows an example of detecting a parity error in data of 3 channels input in parallel for 1 channel of 8 bits.
11A to 13A in the figure are parity arithmetic circuits, and 21A to 2A.
3A is a comparison circuit, 31a to 33a are parallel / serial conversion circuits, and 40 is a multiplex circuit.

In the figure, parity operation circuits 11A to 13
Each A is composed of eight parity detection circuits (not shown), calculates the parity of 8-bit parallel data of channels (shown as CH in the figure) 1 to channel 3, and outputs one of the terminals of the comparison circuits 21A to 23A. Input in 8-bit parallel. 8-bit parallel data is input to the other terminal.

In the comparison circuits 21A to 23A, the input data is compared with the 8-bit parity calculation result obtained from the input data, and the comparison result is input to the parallel / serial conversion circuits 31a to 33a as 8-bit parallel data. ..

Parallel / serial conversion circuits 31a-33
In a, the comparison value of the B2 byte is extracted from the input 8-bit parallel data by the B2 timing pulse and the clock, and the data is converted into 8-bit serial data.

The multiplexing circuit 40 multiplexes 8-bit serial data of channels 1 to 3 and outputs it as 24-bit serial data.

[0011]

In the above-mentioned conventional example, the 8-bit parallel parity detection result is converted into 8-bit serial data, and then 3-channel serial data is multiplexed to obtain 1-channel serial data. There is.

Therefore, a circuit for generating and controlling a timing pulse for multiplexing 8-bit serial data for three channels and converting it into 24-bit serial data becomes complicated.

According to the present invention, a parity error detection of data input to 1-channel n-bit parallel data is performed in n-bit parallel, and N-channel error detection outputs are collectively output as N × n-bit serial data.
Attempts to realize an inexpensive parity error detection circuit.

[0014]

FIG. 1 is a block diagram for explaining the principle of the present invention. Reference numerals 11 to 1N in the figure denote parity calculation circuits for calculating the parity of parallel input data input in 1-channel n-bit parallel.
N is a comparison circuit that compares the n-bit parity calculated by the parity calculation circuits 11 to 1N with the input data.

Reference numerals 31 to 3N extract a comparison value from the n-bit parallel comparison output of the comparison circuits 21 to 2N at a predetermined timing pulse and convert it into serial data, and convert the converted N-channel n-bit serial data. N ×
It is a parallel / serial conversion circuit for converting and outputting to n-bit serial data.

[0016]

The parity of the input data input in 1-channel n-bit parallel is obtained by the parity operation circuits 11 to 1N and compared with the input data.

The comparison value of the parity is extracted from the comparison output which is output in n-bit parallel of the comparison result by a predetermined timing pulse, and the parallel / serial conversion circuits 31 to 3N.
By converting the n-bit parity error data of channel 1 to channel N as N × n-bit serial data, the multiplexing circuit 40 of the conventional example can be omitted and the timing control can be performed. Can be easy.

[0018]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
The figure shows an example of N = 3 and n = 8, and the parity operation circuits 11A to 13A and the comparison circuits 21A to 23A in the figure are the same components as described in the conventional example.

Parallel / serial conversion circuit 3 of this embodiment
Each of 1A to 33A is composed of eight flip-flop circuits (hereinafter referred to as FF circuits, not shown), and further eight FF circuits are serially connected to form a 24-stage shift register.

The operation of the embodiment will be described with reference to the drawings.
FIG. 3 is a time chart of the embodiment of the present invention. Here, channel 1 will be described as an example, but the operations of channels 2 and 3 are the same. Comparative values 1 to 8 in the figure are outputs obtained by comparing the parity obtained by the input data parity operation circuit 11A and the input data by the comparison circuit 21A, and are output in 8-bit parallel.

Here, the comparison circuit 21A uses an exclusive OR circuit, and outputs "L" when two data match and "H" when two data do not match, and is a parallel circuit composed of eight FF circuits. / Input to the serial conversion circuit 31A.

The B2 byte pulse is a pulse which becomes "H" when the B2 byte is input, and the rising edge of the clock (shown as CK in the figure) when the B2 byte pulse is "H" (indicated by an arrow in the figure). Holds the output of the comparison circuit 21A.

FIG. 4 is a diagram (1) for explaining the parallel / serial conversion of the embodiment of the present invention, in which the outputs of the FF circuits 1 to 8 are data holding the comparison values of FIG. The comparison values 1 to 8 in FIG. 3 are latched at the rising edge of the clock when the B2 byte pulse is “H”, and eight Fs are fed from the next clock.
The F circuits 1 to 8 are operated as shift registers. Therefore, the output of the FF circuit in the previous stage is shifted one after another, and F
The F circuit 8 outputs the 8-bit serial data shown in the figure.

FIG. 5 is a diagram (2) for explaining the parallel / serial conversion of the embodiment of the present invention, in which the FF of channel 1 is used.
The circuit 1 to 8, the channel 2 FF circuits 9 to 16 and the channel 3 FF circuits 17 to 24 are serially connected to operate as a 24-stage shift register.

Therefore, channel 1 to channel 3
The 8-bit parity detection result is output from the FF circuit 24 as 24-bit serial data. As described above, in the present embodiment, the conventional multiplexing circuit 40 is not required, and the control can be simplified.

[0026]

According to the present invention, a parity error of N-channel data input in 1-channel n-bit parallel is detected for each channel, and an N-bit n-bit parity error detection result of N × n bits is detected. It is possible to realize a small and inexpensive parity error detection circuit that can be converted into serial data and output.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a time chart of an example of the present invention.

FIG. 4 is a diagram (1) for explaining parallel / serial conversion according to the embodiment of the present invention.

FIG. 5 is a diagram (2) for explaining parallel / serial conversion according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a frame format of digital communication.

FIG. 7 is a diagram illustrating a conventional example.

[Explanation of symbols]

11-1N, 11A-13A Parity operation circuit 21-2N, 21A-23A Comparison circuit 31-3N, 31A-33A 31a-33a Parallel / serial conversion circuit 40 Multiplexing circuit

Claims (2)

[Claims] 1. A parity error detection circuit, wherein one channel is a parity error detection circuit obtained from N-channel input data input in n-bit parallel, and a parity operation circuit for calculating the parity of each bit of n-bit parallel input data. (11 to 1N)
And a comparison circuit (21-2N) for comparing the n-bit bit-by-bit parity calculated by the parity operation circuit (11-1N) with the n-bit-by-bit parity written in the input data. ) And parallel / serial for converting n-bit parallel data output from the comparison circuit (21 to 2N) into serial data and converting the converted N-channel n-bit serial data into N × n-bit serial data. A parity error detection circuit comprising a conversion circuit (31 to 3N). 2. The parallel / serial conversion circuit (31)
3N) are n flip-flop circuits (1
To n), the n flip-flop circuits (1 to n) are serially connected for N channels, and the n-channel output of the N channels of the comparison circuit (21 to 2N) is held by a clock. The parity error detection circuit according to claim 1, wherein the held data is then shifted by a clock to be converted into N × n bit serial data and output.