JPH0547902B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording medium speed detection device, and more particularly, to a recording medium speed detection device that cyclically sends a plurality of pilot signals having different frequencies to each recording track formed in sequence on a recording medium. It is suitable for application to an information recording device using an automatic tracking method (hereinafter referred to as the ATF method) in which the reproducing head is made to track each track using a pilot signal recorded together with information and reproduced by the reproducing head. be.

[Background technology and its problems]

An example of this type of information recording device is a video tape recorder (VTR). In a VTR, video information is recorded using a rotating head that rotates at a speed difference relative to the running magnetic tape as a recording medium. By recording obliquely on the magnetic tape and running the magnetic tape at the same speed as when recording, the reproducing head can correctly reproduce the video signals recorded on each video track.

However, in VTRs that can record in multiple modes with different tape speeds, the tape running speed must be automatically detected during playback and the tape running speed must match the tape running speed during recording. It is desirable to switch the running speed during playback so that the speeds match. Some conventional VTRs are capable of recording in two recording modes: normal recording at fast running speeds (this is called SP mode) and long-term recording at slow running speeds (this is called LP mode). CTL for speed control
In VTRs using the so-called control signal tracking method (CTL method), pulses are recorded in the running direction of the tape separately from the video track, the CTL pulses are reproduced by a fixed head, and the reproduced CTL pulses are used to perform tracking servo. teeth,
For example, the pitch of the reproduced CTL pulse is determined by a speed judgment circuit composed of a microcomputer, and the reproduction is performed.
A speed detection device was used to change the tape speed so that the frequency of the CTL pulses matched the recording frequency.

However, in the past, ATF type VTRs did not have an appropriate configuration as a tape speed detection device.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and
Recording in which it is possible to detect whether or not the running speed of a recording medium during playback matches the running speed during recording based on the pilot signal recorded on each track of the recording medium in an ATF type tracking control device. This paper attempts to propose a medium speed detection device.

[Summary of the invention]

To achieve this object, the present invention forms a periodic speed signal whose frequency changes according to the running speed of the recording medium based on a pilot signal included in the reproduction output, and determines the frequency of this speed signal. In particular, a mode determination signal corresponding to the type of running mode of the recording medium is obtained.

〔Example〕

The present invention will be described in detail below with reference to the drawings as an embodiment in which the present invention is applied to an ATF type two-head helical scanning VTR.

First, the operating principle of the ATF type tracking control device will be described with reference to FIGS. 1 to 3. That is, in this tracking control device, as shown in FIG. 1, a signal S1, which is a part of the playback output of a rotating video head as a playback head, is received by a pilot signal detection circuit 1 having a low-pass filter configuration, and is recorded on a magnetic tape as a recording medium. A reproduced pilot signal S2 having the reproduced output of the pilot signal as a component is generated, and this reproduced pilot signal S2 is supplied to the error signal forming circuit 3. The error signal forming circuit 3 sends out a tracking error signal S3 formed under the control of the lock point control circuit 4.

On the tape 5, as shown in FIG.
A set of four video tracks T1, _T2 , T3, and _{T4 on which f 1 , f 2 , f 3 , and f 4 are recorded} are formed diagonally and closely together so as to repeat in a cyclical manner.
The effective width of the video head constituting the playback head 6 is selected to be approximately equal to the width of the tracks T1 to T4, for example, so that the playback head 6 is currently scanning as shown by the solid line in FIG. When a track (this is referred to as a playback track) is correctly tracked, only one type of pilot frequency component is included in the playback output by playing back only the pilot signal recorded on the track. When the playback head 6 is shifted to the right or to the left with respect to the relevant track, as in the above example, the pilot signal recorded on the track adjacent to the right or left side of the relevant playback track is also reproduced and included in the playback output. There are two types of pilot frequency components, and the magnitude of each pilot frequency component is made to correspond to the opposing length of the reproducing head facing the corresponding track.

However, the frequencies f ₁ to _{f 4} of the four types of pilot signals f ₁ to f ₄ are selected as the lower band of the color component converted to a low frequency (600 to 700 [kHz]), and the four tracks T1 circulate. ~T4, for example, centering on the odd-numbered tracks T1 and T3, the frequency difference between the pilot signal of the right track is Δf _A , and the frequency difference between the pilot signal of the left track and the pilot signal is Δf _B. Along with being there,
The frequency difference between the even-numbered tracks T2 and T4 and the pilot signal of the right track is Δf _B
and the frequency difference between the left track and the pilot signal is Δf _A.

Therefore, head 6 is connected to odd-numbered tracks T1 and T.
3, if there is a signal component with a frequency difference of Δf _A as a frequency component of the pilot signal included in the reproduced signal, it can be seen that the head 6 is shifted to the right, and if there is a signal component with a frequency difference of Δf _B. If there is a signal component, it can be seen that the head 6 is shifted to the left, and if there is no signal component with the frequency difference Δf _A and Δf _B , it can be seen that tracking is being performed correctly.

Similarly, head 6 is an even-numbered track T.
2. When reproducing T4, if there is a signal component with a frequency difference of Δf _B as a frequency component of the pilot signal included in the reproduced signal, it is known that the head 6 is shifted to the right, and if the frequency difference is Δf _A If there is a signal component of , it can be seen that the head 6 is shifted to the left.

In this embodiment, the frequencies f 1 , f 2 , f 3 , f 4 assigned to the first, second, third, and fourth tracks _T1 , _T2 , _T3 , and _T4 are f ₁ =102 [ kHz], _f2
= 116 [kHz], f ₃ = 160 [kHz], f ₄ = 146 [kHz], therefore, the difference frequencies Δf _A and Δf _B are Δf _A = |f ₁ −f ₂ |= |f ₃ −f ₄ |=14 [kHz]
………(1) Δf _B =｜f ₂ −f ₃ ｜=｜f ₁ −f ₄ ｜=44 [kHz]
......(2) has been selected.

The reproduced signal S1 having such content obtained from the head 6 is given to a pilot signal detection circuit 1 having a low-pass filter configuration, and a reproduced pilot signal is obtained by extracting the pilot signals f ₁ to f ₄ contained in the reproduced signal S1. Signal S2 is applied to multiplier 14 as a first multiplication input. The reference pilot signal S11 of the lock point control circuit 4 is applied to the multiplier 14 as a second multiplication input.

The lock point control circuit 4 includes a pilot frequency generating circuit 16 that generates four types of pilot frequency outputs f1 _{to f4} , and a pilot frequency generating circuit 16 that generates four types of pilot frequency outputs f1 _{to f4} , and two video heads connected to a rotating drum (not shown). It has a switch circuit 17 which receives a head switching pulse RF-SW (FIG. 3A) which changes the logic level each time the head that scans the tape is switched. In this embodiment, the switch circuit 17 has a quaternary counter circuit that performs a counting operation every time the level of the head switching pulse RF-SW changes.
The gate signal corresponding to T4 is sequentially repeated, and the gates are opened by the gate signals of tracks T1 to T4, respectively, and the pilot frequency outputs _f1 to f of the pilot frequency generating circuit 16 are generated as shown in FIG. 3B. ₄ as the reference pilot signal S1
It is configured to be sent as 1.

Note that the reference pilot output S11 obtained at the output end of this switch circuit 17 is sent to the video head as a pilot signal via the signal line 18 during recording, so that the video head can control the first to fourth signals.
While the tracks T1 to T4 are being scanned, pilot signals of corresponding frequencies _f1 to _f4 are sequentially applied to the video heads to record on the respective tracks T1 to T4.

In this way, while the head 6 scans the first to fourth tracks T1 to T4, the reproduced pilot signal S2 obtained at the output terminal of the pilot signal detection circuit 1 is generated in synchronization with the reproduced track. By multiplying the reference pilot signal S11 by the frequency component included in the reproduced pilot signal S2 when there is a tracking error,
A multiplication output S1 comprising a difference frequency component having a frequency different from the frequency of the reference pilot signal S11.
2 (actually, the multiplication output S12 also includes other signal components such as the frequency component of the sum). This multiplication output S12 is transmitted to the first and second difference frequency detection circuits 20 each composed of a bandpass filter.
and 21. The first difference frequency detection circuit 20 extracts the signal component of the difference frequency Δf _A based on the above-mentioned equation (1) in the multiplication output S12 and converts it into a direct current using the direct current converting circuit 22 having a rectifier circuit configuration. The converted DC level first error detection signal S13
get. Similarly, when the multiplication output S12 includes a signal component of the difference frequency Δf _B based on the above equation (2), the second difference frequency detection circuit 21 extracts the signal component and sends it to the DC conversion circuit 23. An error detection signal S14 is obtained.

Here, when the head 6 is scanning the first, second, third and fourth tracks T1, T2, T3, T4 (therefore, the switch circuit 17 scans each track T1, T2 as shown in FIG. 3B). , T3, and T4), the reference pilot signal S11 with frequencies f ₁ , f ₂ , f ₃ , and f ₄ is sent out at timings corresponding to the signals S1, T3, and T4. The reproduced pilot signal S2 has frequencies f ₁ and f ₂ , f 2 and f ₃ , f ₃ and f ₄ , f _{4 and} f ₁ as shown in FIG. 3 C1.
_{By including the pilot signals of _ 3} ~
_f4 ),
A signal sequentially containing Δf _B (=f ₄ to _{f 1} ) is generated. On the other hand, when the head 6 is shifted to the left, the reproduced pilot signal S2 sequentially changes frequencies f ₄ and f ₁ , f 1 and f ₂ , f ₂ and _{f 3 ,} f ₃ and f , as shown in FIG. _Accordingly , the multiplication output S12 has a difference frequency Δf _B as shown in FIG. 3 D2.
(= _f4 ~ _f1 ), _ΔfA (= _f1 ~ _f2 ), _ΔfB (= _f2 ~ _f3 ),
Δf _A
(=f ₃ to f ₄ ) are sequentially included.

Thus, as shown in FIGS. 3E and F (for example, showing a right-shifted state), each time the head 6 switches tracks scanned, the DC level rises from 0.
And second error detection signals S13 and S14 can be obtained from the DC converting circuits 22 and 23.

First and second error detection signals S13 and S1
4 are given to the subtraction circuit 24 as an addition input and a subtraction input, respectively, thereby producing first and second error detection signals S13 and S1 as shown in FIG. 3G.
4 is obtained alternately, a subtraction output S15 that changes in an alternating current manner is obtained. This subtracted output S15 is applied to the first input terminal a1 of the direct changeover switch circuit 25, and its polarity is inverted in the inverting circuit 26 and applied to the second input terminal a2. The changeover switch circuit 25 switches the head 6, for example, to odd-numbered tracks T1 and T3 by the head changeover pulse RF-SW.
When scanning the first input terminal a1, the even numbered tracks T2 and T4 are switched to the first input terminal a1 side.
When the head 6 is being scanned, it is switched to the second input terminal a2, and thus, when the head 6 is shifted to the right as shown in FIG. (on the other hand, when there is a left shift state, the DC level output S16 has a magnitude corresponding to the left shift amount and becomes negative polarity), and this is the output amplification circuit 27 consisting of a DC amplifier.
The error signal S3 is sent out as an error signal S3. Incidentally, if the head 6 is shifted, for example, to the right, a signal component of the difference frequency Δf _A appears at the output terminal of the multiplier circuit 14 when the reproduced track is an odd numbered track T1 or T3. The output of is given to the subtraction circuit 24, and since the changeover switch circuit 25 is switched to the first input terminal a1 side at this time, an error signal S1 of a positive DC level is sent to the subtraction circuit 24.
Sends 7. On the other hand, when the reproduced tracks are even-numbered T2 and T4, a signal component of the difference frequency Δf _B appears at the output terminal of the multiplication circuit 14, so that the output from the second difference frequency detection circuit 21 is sent to the subtraction circuit 24. Moreover, at this time, the changeover switch circuit 25 is switched to the second input terminal a2 side, so the polarity of the negative output of the subtraction circuit 24 is inverted by the inverting circuit 26 and sent as an error signal S3 at a positive DC level. do.

Therefore, if this error signal S3 is used as a correction signal in the phase servo circuit of the capstan servo loop, and is corrected so that when it is positive, the tape running speed is made faster, and when it is negative, it is made slower, the video head and the playback track can be corrected. It is possible to correct the phase shift between the two and thus realize correct tracking servo.

In FIGS. 1 to 3, the principle has been described assuming that the width of the video head is approximately equal to the track width, but in reality the width of the video head is larger than the track width. Therefore, when the video head during playback is tracking correctly, the left and right portions also face the tracks on both sides of the playback track. However, the error signal components in the leftward and rightward directions generated based on the pilot signal obtained from this part have opposite polarities and equal magnitudes, so they cancel each other out.
In the end, the overall operation follows the above-mentioned operating principle.

Furthermore, in the configuration shown in FIG. 1, the difference frequencies Δf _A and Δf _B are obtained from each reproduced pilot signal, but
Even if the tracking error signal is obtained by comparing the amplitudes of the respective pilot signals, the same effect as described above can be obtained.

A recording medium speed detecting device 31 having the structure shown in FIG. 4 is provided for a VTR having a tracking control device having the above-described principle structure. In this embodiment, the "normal recording" SP mode records at twice the tape speed of the "long-term recording" LP mode.

As described above with reference to FIGS. 1 to 3, the reproduction signal S1 obtained from the reproduction head 6 has four frequencies.
It includes reproduced pilot signals of f ₁ , f ₂ , f ₃ and f ₄ , and a predetermined one of them, for example, the reproduced pilot signal of frequency f ₁ is used as an input signal to the speed signal forming circuit 32, for example, to a low-pass filter or a PLL circuit. The pilot signal is input to a pilot signal extracting circuit 33 composed of the following, is extracted by this extracting circuit 33, and is applied to a multiplication circuit 34 as a first multiplication input S31. The multiplier circuit 34 receives a reference pilot signal S32 having a frequency _f4 , for example, among the pilot signals generated from the pilot frequency generating circuit 16 shown in FIG.
As a result, a signal component having a difference frequency Δf _B (=f ₄ to _{f 1} ) between the frequencies f ₁ and f ₄ of the first and second multiplication inputs is generated at the output S33 of the multiplication circuit 34. Ru.

This difference frequency Δf _A of the output S33 of the multiplication circuit 34
The signal component is extracted by a difference frequency detection circuit 35 having a band-pass filter configuration, for example, and its output S34 is converted to DC by a DC converting circuit 36 having a rectifier circuit configuration, and thus a DC level speed signal S35 is sent to the speed signal forming circuit 32. is sent as the output of

The speed signal S35 obtained in this manner has the content obtained by peak detection of the signal component of the difference frequency Δf _B , and therefore changes in accordance with the change in the peak value of the reproduced pilot signal of the frequency f ₁ . Here, the way the peak value of the playback pilot signal changes is when a tape recorded in LP mode is played back in SP mode.
There is a clear difference between playing a tape recorded in SP mode and playing it in LP mode.

In other words, first, when a tape recorded in LP mode is played back in SP mode, the frequencies f ₁ , f ₂ , f ₃ , f ₄ are sequentially cyclically played in the order of the solid line in FIG. 5A. Tracks T1, T2, T3, and T4, which were recorded at a slow tape speed, are played back at twice the tape speed, so the playback head 6 moves at the arrow 3.
As shown by 7, the vehicle crosses two recording tracks indicated by dotted lines and travels along a trajectory approximately twice the width. However, in this embodiment, only the signal component corresponding to the reproduced pilot signal of frequency f ₁ having a difference frequency of Δf _B with respect to the frequency f ₄ of the reference pilot signal S 32 is extracted by the difference frequency detection circuit 35. The speed signal S35, as indicated by _diagonal lines in FIG. The level at each point in time will be changed to correspond to the change in . This means that when the playback head 6 is in the SP mode, as shown in FIG.
The reproducing head 6 is scanned during a period corresponding to the field (this period corresponds to the 1/2 period period W of the head switching pulse RF-SW as shown in FIG. 5B).
This means that the speed signal S35 has a waveform that has approximately the same shape as that of the portion facing the track T1.

Therefore, as can be seen from FIGS. 5A and 5C, the signal waveform of the speed signal S35 has periodicity, and is repeated as one period every time the reproducing head 6 scans two fields.

On the other hand, secondly, when a tape recorded in SP mode is played back in LP mode, the frequencies f ₁ , f ₂ , f ₃ ,
Tracks T1, T2, T3, and T4, which are recorded at twice the tape speed in sequence in the order of f ₄ , are
Since the tape is played back at double the tape speed, even though one track T1 has been completely scanned as shown by the dotted line, the playback head 6 receives the head switching signal RF-SW (Fig. 6B).
Continuous scanning is performed for an interval of 4 fields. After the reproducing head 6 scans the track T1, it does not face the track T1 while it scans the following four fields, so the DC level of the speed signal S35 of the DC conversion circuit 36 becomes 0.

Thus, the speed signal S35 has periodicity and the sixth
As shown in FIG.
The waveform has a shape that is almost the same as that of the part facing the .

Thirdly, however, if the tape speed during recording and the tape speed during playback are equal, the playback head 6 faces the track T1 every time it scans four fields, so that the speed signal S35 of the DC conversion circuit 36 The waveform is repeated with four fields in one cycle.

In practice, in the case of an NTSC VTR, playback head 6
is scanning at 60 [Hz] (that is, 60 [field/sec]), when "playing back a tape recorded in SP mode in LP mode", the speed signal S3
The frequency of 5 is 7.5 [Hz] (=60 [field/sec] ÷
8 [field]), and when the recording mode and playback mode are the same, the frequency of the speed signal S35 is 15 [Hz] (= 60 [field/sec] ÷ 4 [field]), and furthermore, when the recording mode and playback mode are the same, the frequency of the speed signal S35 is 15 [Hz] (= 60 [field/sec] ÷ 4 [field]), speed signal S when playing back a tape in SP mode.
The frequency of 35 is 30 [Hz] (=60 [field/sec]
÷2 [field]). Therefore, the speed signal S3
By determining which of these three states the frequency No. 5 is in, it is possible to detect the difference between the recording mode and the reproduction mode.

Therefore, the speed signal S35 obtained from the DC conversion circuit 36 in FIG. 4 is applied to the frequency discrimination circuit 39 via the waveform shaping circuit 38.

In this embodiment, the waveform shaping circuit 38 receives the speed signal S35 and outputs the message "The tape recorded in the LP mode".
When the tape recorded in the SP mode is played back, a mode changeover switch circuit 42 is provided which sends the tape directly from the terminal b1 side to the Schmitt circuit 41 having a positive feedback loop. If the speed signal S35 is to be reproduced by "playback", the speed signal S35 is sent to the sample hold circuit 43 via the terminal b2. The sample hold circuit 43 is
A sample pulse S3 is generated from a sample pulse generation circuit 44 having, for example, a mono-multivibrator configuration, which receives the head switching signal RF-SW and generates a sample pulse S36 at approximately the center position of its 1/2 period.
6, the value of the speed signal S35 (FIG. 6C) is sampled at approximately the center of each field section and this sampled value is held. This is done because, as shown in Figure 6C, when a tape recorded in SP mode is played back in LP mode, the waveform of speed signal S35 has a period of 8 fields, and the DC level rises during 4 fields. However, the waveform of the rising part changes sharply even during one field section, and especially there is a 0 level or 0 level in this rising waveform.
There is a part where the value falls to a value near the level. Therefore, in some cases, the frequency of the speed signal S35 may fall below the Schmitt level of the Schmitt circuit 41, causing the frequency of the speed signal S35 to be erroneously changed to a frequency other than 7.5 [Hz]. In order to reduce such a risk, the sample and hold circuit 43 prevents partial falls in the rising waveform, and thus the Schmitt circuit 41 reliably outputs the waveform-shaped signal into a waveform that rises every 8 field periods. It is used as input S37 to. According to experiments, by using such a sample and hold circuit 43, it was possible to prevent the Schmitt circuit 41 from malfunctioning in practice.

The Schmitt circuit 41 receives the input signal S37 at a frequency that has a predetermined amplitude and corresponds to the above-mentioned reproduction state.
The frequency signal S38 is shaped into a rectangular wave having frequencies of 7.5 [Hz], 15 [Hz], and 30 [Hz]. Therefore, a positive feedback path 45 is provided at the positive phase input end of the operational amplifier circuit 47, and a low pass filter 46 is provided at the negative phase input end, so that hysteresis operation is performed.

The frequency discrimination circuit 39 includes a frequency-voltage conversion circuit 50 that receives the frequency signal S38 from the Schmitt circuit 41 and generates a voltage output corresponding to the frequency. The frequency-voltage conversion circuit 50 receives the measurement period signal S39 obtained by frequency-dividing the head switching signal RF-SW by the 1/n frequency dividing circuit 51, and converts the head switching signal RF-SW into a Schmitt circuit during the n-period section of the head switching signal RF-SW. The number of cycles of the 41 frequency signal S38 is counted and the corresponding voltage value is sent out as the voltage signal S40 at the end of each n cycle. In this embodiment, the frequencies of the frequency signal S38 are 7.5 [Hz] and 15 [Hz], respectively.
[Hz], 30 [Hz], the voltage value of voltage signal S40 is
V _a , V _b , V _c (V _a < V _b < V _c ).

The voltage signals S40 are reference voltages _V1 and _V2 , respectively.
The reference voltages V ₁ and V 2 are given to voltage comparison circuits 52 and 53 having voltage values V a and _{V a} of the voltage signal S40, respectively.
The values are set to satisfy the relationship of _{V a <} V ₁ <V _b <V ₂ <V _c with respect to V b and V _c .

One of the voltage comparator circuits 53 becomes a logic level "H" when the voltage signal S40 becomes a voltage higher than the reference voltage _V2 (that is, _Vc ), and the reference voltage _V2
A comparison output S41 which becomes a logic level "L" when the voltage becomes lower (ie, V _b , V _a ) is sent out. Further, the other voltage comparison circuit 52 outputs the voltage signal S4.
0 becomes a logic level "H" when it becomes a voltage lower than the reference voltage V ₁ (i.e., V _a ), and becomes a logic level "L" when it becomes a voltage higher than the reference voltage V ₁ (i.e., V _b , V _c ). A comparison output S42 is sent out.

Comparison output S4 of the voltage comparison circuits 52 and 53
2 and S41 are respectively input to the set terminal S and reset terminal R of the mode switching signal forming circuit 54 having an R-S flip-flop circuit configuration, and its Q output is
The Q output is sent out as the SP mode discrimination signal KSP, and the Q output is sent out as the LP mode discrimination signal KLP.

Therefore, when the frequency of the frequency signal S38 is 30 [Hz] (that is, when "a tape recorded in the LP mode is played back in the SP mode"), the voltage signal S4
Since the voltage value of 0 is _Vc , the comparison outputs S41 and S42 become "H" and "L", and the mode switching signal forming circuit 54 is reset and sends out the LP mode discrimination signal KLP of logic level "H". .

Also, when the frequency of frequency signal S38 is 7.5 [Hz] (i.e., when a tape recorded in SP mode is
(when playing in LP mode), voltage signal S4
Since the voltage value of 0 is V _a , comparison outputs S41 and S42 become "L" and "H", and the mode switching signal forming circuit 54 is set to the logic level "H".
The SP mode determination signal KSP is sent.

Furthermore, when the frequency of the frequency signal S38 is 15 [Hz] (that is, when the tape speeds during recording and playback are the same), the voltage value of the voltage signal S40 is V _b , so the comparison outputs S41 and S42 are " The mode switching signal forming circuit 54 remains in the state before the comparison outputs S41 and S42 became "L" and "L", and the LP mode discrimination signal KLP is at the logic level "H". Alternatively, the state in which the SP mode discrimination signal KSP is sent is maintained.

The recording medium speed detection device 31 having the configuration shown in FIG. 4 operates as follows.

First, when playing back a tape recorded in LP mode in SP mode, the track T1 is repeatedly played every time the playback head 6 scans two fields.
(Fig. 5A), the signal component of the difference frequency Δf _B whose amplitude changes at 30 [Hz] is obtained from the difference frequency detection circuit 35, and the signal component with a DC level of 30 [Hz] is output from the DC conversion circuit 36. Changing speed signal S35
is sent out (Figure 5C). Therefore, the value of the voltage signal S40 of the frequency-voltage conversion circuit 50 becomes V _c ,
Comparison outputs S41 and S4 of comparison circuits 53 and 52
2 becomes logic "H" and "L", and the mode switching signal forming circuit 54 sends out the LP mode discrimination signal KLP.

This LP mode discrimination signal KLP is separately given to the tape running device of the VTR body as a speed designation signal, and switches the tape running speed from SP mode to LP mode, and at this time, the tape running speed is the same as the running speed during recording. become. Therefore, the change in the amplitude of the signal component of the difference frequency Δf _B of the difference frequency detection circuit 35 is
As a result, the value of the voltage signal S40 of the frequency-voltage conversion circuit 50 changes to V _b , and the comparison outputs S41 and S42 of the comparison circuits 53 and 52 become logic "L" and "L". Become. Therefore, the mode switching signal forming circuit 54 maintains the previous state, that is, the state in which the LP mode discrimination signal KLP is being sent out, thus maintaining the tape running device in the LP mode.

Next, if you are playing back a tape recorded in SP mode in LP mode, the track will be repeated every time the playback head 6 scans eight fields.
Since it faces T1 (Fig. 6A), the change in the amplitude of the signal component of the difference frequency Δf _B of the difference frequency detection circuit 35 is
The speed signal becomes 7.5 [Hz] and changes at that frequency.
S35 is sent out from the DC conversion circuit 36 (FIG. 6C). Therefore, the value of the voltage signal S40 of the frequency-voltage conversion circuit 50 becomes V _a , the comparison outputs S41 and S42 of the comparison circuits 53 and 52 become logic "L" and "H", and the value of the voltage signal S40 from the mode switching signal forming circuit 54 becomes SP mode determination signal KSP is sent.

This SP mode discrimination signal KSP is separately given to the tape running device of the VTR body as a speed command signal.
The tape running speed is switched from LP mode to SP mode, and at this time the tape running speed becomes the same as the running speed during recording. Therefore, the difference frequency detection circuit 3
5 The change in amplitude of the signal component of the difference frequency Δf _B is 15 [Hz]
As a result, the frequency-voltage conversion circuit 50
The value of the voltage signal S40 changes to V _b , and the comparator circuit 53
and 52 comparison outputs S41 and 42 are logic "L"
and becomes “L”. Therefore, the mode switching signal forming circuit 54 maintains the previous state, that is, the state in which the SP mode discrimination signal KSP is being sent, thus maintaining the tape running state in the SP mode.

As described above, according to the configuration shown in FIG. 4, when the tape running speed during recording and the tape running speed during playback are different, this is reliably detected and the tape running speed is automatically adjusted to the running speed during recording. You can change it to match.

Therefore, if the speed signal S35 is sampled and held in the sample-and-hold circuit 43 in the LP mode and its output is supplied to the Schmitt circuit 41, the accuracy of the frequency signal S38 can be improved.

In the above-mentioned embodiment, the sample and hold is taken at approximately the center of the field section, but the sample and hold is not limited to this, and the time at which the sample and hold is performed can be selected as appropriate.

Further, the sample hold may be performed not only in the LP mode but also in all cases, or conversely, the sample hold may not be performed at all. In this case, although the accuracy of the frequency output is somewhat reduced, it is possible to realize a recording medium speed detection device that operates based on the principles of the present invention.

In the case of Fig. 4, the reference pilot signal with frequency f ₄
For S32, changes in the reproducing pilot signal of frequency f ₁ were monitored, but for frequency f ₁
It is also possible to use f ₂ , f ₃ for f ₂ , _and f ₄ for f 3 .

Alternatively, the configuration shown in FIG. 7 may be used in which the reproduced pilot signal to be monitored has two frequencies. In the case of FIG. 7, as shown by attaching the same reference numerals to the parts corresponding to those in _FIG . In parallel with the system, a system including a difference frequency detection circuit 35B for extracting the difference frequency Δf _B , a direct current conversion circuit 36B, a mode changeover switch circuit 42B, and a sample hold circuit 43B is provided at the output end of the multiplication circuit 34. The output S50 of the system having the difference frequency Δf _A is applied to the negative phase input terminal of the Schmitt circuit 41, and the output S51 of the system having the difference frequency Δf _B is applied to the positive phase input terminal of the Schmitt circuit 41.

In this case, the signal component of the difference frequency Δf _B for the regenerated pilot signal of frequency f ₃ is:
"Playback a tape recorded in LP mode in SP mode"
In this case, as shown in FIG. 5D, the signal component of the difference frequency Δf _B (FIG. 5C) with respect to the reproduced pilot signal of frequency f ₁ is obtained with a phase delayed by one field but with the same waveform, and When "playing back a tape recorded in SP mode in LP mode", as shown in Figure 6D, 4 fields are generated for the signal component of the difference frequency _ΔfB (Figure 6C) with respect to the reproduction pilot signal of frequency _f1 . The same waveform can be obtained with a delayed phase.

Therefore, the Schmitt circuit 41 generates a frequency signal which rises in response to the speed signal S35 with respect to the frequency f ₁ and then falls in response to the speed signal S35 with respect to the frequency f ₃ .
Generates S38. Incidentally, when the tape speed during recording and playback is the same, the speed signals S35 and S51 for frequencies _f1 and _f3 are converted into the head switching signal RF-SW (Fig. 8A) as shown in Fig. 8B and C. As shown in FIG. 8D, the Schmitt circuit 41 has a phase difference of two fields.
A frequency output S38 having a frequency of 4 field periods, that is, 15 [Hz], which changes the logic level every time the field is scanned, is sent out.

If configured as shown in Fig. 7, the Schmitt circuit 4
It is not necessary to provide a low-pass filter circuit at the negative phase input terminal of 1, and the structure can be simplified compared to the structure of FIG. 4 to this extent.

FIG. 9 shows another embodiment of the invention, in this case the seventh
As shown by attaching the same reference numerals to the corresponding parts in the figure,
The reproduced pilot signal S31 is multiplied by reference pilot signals S55 and S56 of frequencies f ₄ and f ₃ in multiplication circuits 34X and 34Y, respectively, and the signal components of difference frequencies Δf _A and Δf _B are sent to difference frequency detection circuits 35XA, 35XB and 35XB, respectively. After being extracted by 35YA and 35YB, it is converted to DC by DC converting circuits 36XA, 36XB and 36YA, 36YB, and added by adding circuits 60X and 60Y. In this way, one of the adder circuits 60X obtains the addition output S53 (having the same frequency as the head switching signal RF-SW) of the peak waveform of frequency _f1 and the peak waveform of frequency _f3 , as shown in FIG. 10B. Further, as shown in FIG. 10C, the other adder circuit 60Y outputs the addition output of the peak waveform of frequency f ₂ and the peak waveform of frequency f ₄ (with a phase delay of one field with respect to the addition output S53). It will be done.

These addition outputs S53 and S54 are applied to the positive phase input terminal and the negative phase input terminal of the Schmitt circuit 41, respectively, and thus the Schmitt circuit 41 outputs the head switching signal RF-SW (FIG. 10A) as shown in FIG. 10D. frequency output with the same frequency as the frequency of
You can get S38. Comparing this frequency output S38 with the frequency output in the case of Fig. 8D, we get
The case in FIG. 10D has twice the frequency as the case in FIG. 8D, which means that the discrimination operation time of the frequency discrimination circuit 39 can be shortened.

In the above embodiment, the frequency signal S38 is converted into a voltage by the frequency-voltage conversion circuit 50 as the frequency discrimination circuit 39, and this is converted to the reference voltages _V1 and _V2 by the voltage comparison circuits 52 and 53. However, instead of this, the period of the frequency signal S38 is determined by a period determination circuit composed of, for example, a microcomputer or a reference pulse oscillator and a counter that counts its output pulses. Also good.

Furthermore, in the above description, the present invention is applied to a VTR that can perform "normal recording" (SP mode) and "long recording" (LP mode) at a tape speed ratio of 1:2. The tape speed ratio can be changed as necessary, and the number of modes is not limited to two, but may be three or more.

Further, the reference signals given to the multiplication circuits 34, 34X, and 34Y are not limited to f ₄ and f ₃ but may be f ₂ and f ₁ as well.

In addition, in the above, the NTSC signal format is
Although we have described the case where the present invention is applied to a VTR,
When applying to CCIR method, 1 field is 50
You can convert it as [Hz].

〔Effect of the invention〕

As described above, according to the present invention, focusing on the fact that the pilot signal included in the playback output has a periodicity determined depending on the running speed of the recording medium, recording is performed based on the period and the change in frequency. The running mode of the medium can be reliably determined, and thus even when the running speed of the recording medium is the same during recording and during playback, it can be reliably determined.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the principle configuration of an ATF type tracking control device, Fig. 2 is a schematic diagram showing a track pattern recorded on a tape, and Fig. 3 is a schematic diagram showing a track pattern recorded on a tape.
The figure is a signal waveform diagram showing the signals of each part in Figure 1.
The figure is a block diagram showing one embodiment of the recording medium speed detecting device according to the present invention, FIGS. 5 and 6 are signal waveform diagrams for explaining its operation, and FIG. 7 is a block diagram showing another embodiment of the present invention. 8 is a signal waveform diagram for explaining its operation, FIG. 9 is a block diagram showing still another embodiment of the present invention, and FIG. 10 is a signal waveform diagram for explaining its operation. 1... Pilot signal detection circuit, 3... Error signal forming circuit, 4... Lock point control circuit, 14, 34,
34X, 34Y... Multiplication circuit, 16... Pilot frequency generation circuit, 17... Switch circuit, 20, 2
1, 35, 35A, 35B, 35XA, 35XB,
35YA, 35YB...difference frequency detection circuit, 22,
23, 36, 36A, 36B, 36XA, 36
XB, 36YA, 36YB... DC conversion circuit, 24... Subtraction circuit, 25... Changeover switch circuit, 26... Inversion circuit, 31... Recording medium speed detection device, 32... Speed signal forming circuit, 33... Pilot signal extraction circuit, 3
8...Waveform shaping circuit, 39...Frequency discrimination circuit, 41
... Schmitt circuit, 43, 43A, 43B... Sample hold circuit, 50... Frequency-voltage conversion circuit, 52, 53... Voltage comparison circuit, 54... Mode switching signal forming circuit.

Claims (1)

[Scope of Claims] 1. A recording medium in which a plurality of pilot signals with different frequencies are recorded cyclically on each track, based on a reproduction pilot signal included in a reproduction output reproduced by a reproduction head. a speed signal forming circuit that forms a periodic speed signal whose frequency changes depending on the difference in running speed during recording and playback; and a speed signal forming circuit that compares the frequency of the speed signal with a predetermined reference value to determine the running speed during recording. In the recording medium speed detection device comprising a frequency discrimination circuit that outputs a discrimination signal, the speed signal forming circuit selects a predetermined one of the plurality of reference pilot signals.
a difference frequency component generation circuit that generates a difference frequency component between the two reference pilot signals and the reproduced pilot signal; and a difference frequency detection circuit that detects a predetermined difference frequency component among the difference frequency components generated by the difference frequency generation circuit. A recording medium speed detection device comprising: a circuit; and a direct current conversion circuit that detects the output amplitude of the difference frequency detection circuit and sends it as the periodic speed signal.