JPH0546550A - Access cycle controller - Google Patents

Abstract

PURPOSE:To secure an access time with no waste in accordance with the access speed of each controlled device and at the same time to minimize the hardware together with simplification of the processing than in regard of an access cycle controller which is connected to an asynchronous system bus and has an access to the optional one of controlled subjects of different access speeds. CONSTITUTION:Plural controlled devices are divided into groups 131-13n based on the same access cycles respectively. An access mode decoder 15 decides the access cycle number in parallel with the decoding operation of an address decoder 14. A timer 16 transmits a timer wait control signal with the access cycle number decided by the decoder 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access cycle control device, and more particularly to an access for accessing an arbitrary controlled device among controlled devices connected to an asynchronous system bus and having different access speeds. The present invention relates to a cycle control device.

A memory or an input / output device (I / O) is connected to a bus for asynchronously transferring data such as a VME bus or a multi-bus.
In a system such as a signal processing board to which controlled devices having different access speeds are connected, when a microprocessor unit (MPU) accesses any one controlled device, each controlled device The access cycle control method is required to minimize the hardware and simplify the processing procedure while it is necessary to make the access time lean to match the access speed of the above.

[0003]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional access cycle control device. In FIG, MPU 1 is an MPU with timer Wait control function, while being connected to the different devices from each other access speed, such as memory 3, I / O device 4 ₁ to 4 _n via the data bus 2, the bus 5 It is connected to the address decoder 6 via.

[0004] While the address decoder 6 is connected to the memory 3, I / O device 4 ₁ to 4 _n, timer 7, 8 ₁ to 8 _n
Connected to each. The timer 7 generates a timer wait control signal after a cycle time corresponding to the access speed of the memory 3. The timers 8 ₁ to 8 _n generate timer wait control signals after a cycle time corresponding to each access speed of the I / O devices 4 ₁ to 4 _n .

In the conventional device having such a configuration, the MPU1
Outputs an address signal and a strobe signal for specifying a device to be accessed via bus 5 to address decoder 6. At the same time the address decoder 6 selects the specified device among the access target device memory 3 and I / O device 4 ₁ to 4 _n based on an input address signal, a timer provided corresponding to the selected device to start.

For example, assuming that the memory 3 is selected by the address decoder 6, the timer 7 is started when the memory 3 is selected. According to this selection, the memory 3 writes the data from the MPU 1 via the data bus 2 or reads the data and outputs the data to the MPU 1.

After the timer 7 is activated, a timer wait control signal is output to the MPU 1 when a predetermined cycle time corresponding to the access speed of the memory 3 has elapsed. As a result, the MPU 1 ends the access sequence.

[0008]

However, in the above-mentioned conventional access cycle control device, the timers 7 and 8 ₁ to 8 _n are provided corresponding to the memories 3 and the I / O devices 4 ₁ to 4 _n , respectively. Although it is most efficient in terms of time because access cycle control is performed according to each object, it is disadvantageous in terms of cost and space because the hardware increases significantly.

It is also conceivable to control the number of cycles on the MPU 1 side according to each object, but this involves complicated processing such as the need for a command for switching the number of cycles.

The present invention has been made in view of the above points,
An object of the present invention is to provide an access cycle control device that solves the above-mentioned problems by dividing controlled objects into groups according to access cycles and performing access cycle control for each group.

[0011]

FIG. 1 is a block diagram showing the principle of the invention according to claim 1. As shown in the figure, according to the present invention, a plurality of controlled objects having different access speeds are connected to the asynchronous external bus 12 of the central processing unit 11 to access any controlled object from the central processing unit 11. group 13 in the access cycle controller, a plurality of the controlled object between the access cycles are the same shall be _1-13
Group into _n .

An address decoder 14 selects an arbitrary controlled object from a plurality of controlled objects based on an output signal of the central processing unit 11. In parallel with this address decoding operation, the access mode decoder 15 determines the number of access cycles. When the number of access cycles determined by the access mode decoder 15 is monitored by the timer 16 and reaches the determined number of access cycles, the timer 16 outputs a timer wait control signal to the central processing unit 11 to set the access sequence. To finish.

According to the second aspect of the invention, an address range of infinite access cycle is set in addition to the plurality of groups (12). Further, in the invention described in claim 3, when the access cycle infinity is selected, the timer 16 generates a timeout error signal after a set time based on the output of the access mode decoder 15.

[0014]

In the invention shown in FIG. 1, the access mode decoder 15 determines the number of cycles corresponding to each address while the normal address decoder 14 determines the access target (controlled object), and the timer 16 To notify. As a result, the timer 16 supplies the timer wait control signal to the central processing unit 11 when the determined access cycle number is reached, and terminates the access sequence.

Therefore, in the present invention, the access cycle number is not determined for each address, but the controlled objects having similar access speeds are grouped into one group for each address range and the access cycle number is determined.
Therefore, the load on the address decoder 14 and the timer control circuits 7, 8 ₁ , ... 8 _n for each controlled object can be reduced, and the timer 16 can be shared.

Further, in the second aspect of the invention, since the address range of infinite access cycle is set, the timer wait control signal can be output by the output of the controlled object.

Further, according to the third aspect of the present invention, when the access cycle is infinite, a time-out error signal is output after the set time, so that the hang-up can be prevented.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals.
2, the central processing unit (hereinafter referred to as MPU) 11 shown in FIG. 1 is omitted for convenience of illustration.

In FIG. 2, the memory 21 is set so as to belong to the group 13 ₁ having the access cycle number "3", and the I / O devices 22 and 23 belong to the group 13 ₂ having the access cycle number "5", respectively. It is set. This is because the memory 21 and the I / O devices 22 and 23 have different access speeds, and the memory 21 is
This is because the access speed is higher than those of Nos. 2 and 23, and the I / O devices 22 and 23 have the same access speed. The controlled object including the memory 21, the I / O devices 22 and 23 is connected to the MPU (not shown) via the data bus 24.

Address decoder 14a and decoder 14
b constitutes the address decoder 14. The address decoder 14a receives the strobe signal STB and the upper 8 bits A1 of the address signal via the control bus 25.
5 to 8 are input and the I / O select signal IOS * and the memory select signal MES * are output.

The decoder 14b has an I / O select signal IO.
S * and 16-bit address signal are input, and I / O
Select signal IO ₁ or I for selecting device 22 or 23
Outputs O ₂ . The access mode decoder 15 receives the strobe signal STB from the control bus 25 and the upper 8 bits A15 to A15 of the address signal from the address bus 26.
8 and 8 are input respectively, and 5 cycle mode control signal CYC
Either one of the 5,3 cycle mode control signal CYC3 and the access cycle infinity mode control signal CYC∞ is output.

The timer 16 comprises a 4-bit counter 28 for counting a clock (CK) and a bus control unit 27.
Based on the output count value of the bit counter 28 and the control signal from the access mode decoder 15, the bus control unit 27
Outputs the timer wait control signal RDY *.

The addresses of the memory 21 and the I / O devices 22 and 23 are set according to the address map shown in FIG. That is, the I / O devices 22 and 23 are shown in FIG.
In the address area indicated by I from "0000" to "00F
The address is set to any one of "F". Further, the memory 21 is "0100" in the address area indicated by II in FIG.
~ Address is set to "FEFF". Furthermore, FIG.
The address area indicated by III is not assigned to the controlled object, and is used as the address area for access cycle infinity mode control.

Next, the operation of this embodiment will be described.
Assuming that the memory 21 is accessed, the MPU outputs the strobe signal STB and the read / write signal r / w * via the control bus 25, respectively, and outputs the strobe signal STB and the read / write signal r / w * to the address bus 26 within the range of "0100" to "FEFF". Output address signal.

Then, the address decoder 14a determines the upper 8 bits A15-8 of the address signal and the strobe signal ST.
Based on B, it is determined that the upper 8 bits A15-8 are not in the range of "00" to "FF", and the memory select signal MES * is set to low level (active).

The memory select signal MES * is applied to the chip select terminal CS of the memory 21 and is applied to the memory 21.
Are made ready for reading / writing. As a result, the memory 21 reads the 16-bit data D15-0 or writes the data D15-0 to the data bus 24 according to the read / write signal r / w *.

On the other hand, the access mode decoder 15 determines that the upper 8 bits A15-8 are not in the range of "00" to "FF" based on the upper 8 bits A15-8 of the address signal and the strobe signal STB. Discriminate 3
The cycle mode control signal CYC3 is generated.

The above-mentioned 3-cycle mode control signal CYC3
Is input to the bus control unit 27. As a result, the bus control unit 27 generates a low-level timer wait control signal RDY * when the count value of the 4-bit counter 28 reaches "3", and the MP waits via the control bus 25.
Supply to U (not shown). This completes the access sequence.

Next, the case of accessing the I / O device 22 will be described. The I / O device 22 has the address "000
It is assumed to be assigned to "0". In this case MP
U (not shown) outputs the strobe signal STB via the control bus 25 and outputs the address signal “0000” to the address bus 26.

As a result, the address decoder 14a sets the I / O select signal IOS * to low level (active) based on the upper 8 bits A15-8 of the address signal and the strobe signal. As a result, the decoder 14b generates the select signal IO1 and selects the I / O device 22 because the lower 8 bits of the address signal are "00".

When the I / O devices 22 and 23 are digital input dedicated I / O devices or digital output dedicated I / O devices, the I / O device is selected by the read / write signal r / w. The read / write signal r / w is also input to 14b.

On the other hand, since the upper 8 bits A15-8 of the input address signal are "00", the access mode decoder 15 determines the 5-cycle mode as shown in FIG. 3, and sets the 5-cycle mode control signal CYC5 to the low level. The bus control unit 27 is notified as (active).

Then, the bus control unit 27 sends the control signal C
After inputting YC5, when the output count value of the 4-bit counter 28 becomes "5", the timer wait control signal RDY * is generated (set to low level) and is sent to the MPU (not shown) via the control bus 25. ).
This completes the access sequence to the I / O device 22.

As described above, according to the present embodiment, the access mode decoder 15 determines whether the 5-cycle mode control of the group 13 ₂ of the I / O devices 22 and 23 or the 3-cycle mode control of the memory 21 is performed. Therefore, the load on the address decoders 14a and 14b can be lightened, and efficient access can be performed, and the timer 16 can be shared, so that the hardware scale can be reduced as compared with the conventional method in which the number of access cycles is determined for each address. it can.

By the way, this embodiment can also realize the infinite access cycle mode. Next, the operation when the infinite access cycle mode is selected will be described. A /
The controlled object, such as the D / A conversion end signal, is the MPU.
This access cycle infinity mode is selected when it is desired to control In this case, the MPU (not shown) outputs the address signal of the address value in the address area III of "FF00" to "FFFF" together with the strobe signal.

As a result, the address decoder 14a receives the I / O because the input upper 8 bits of the address is "FF".
O select signal IOS * and memory select signal MES
Neither * is output, and the local control I / O select signal LIO * is selected instead. On the other hand, since the input upper 8 bits of the address is "FF", the access mode decoder 15 determines that the access cycle is infinity mode, and the access cycle infinity mode control signal CYC.
Generate ∞.

When the control signal CYC∞ is input, the bus controller 27 stops sending the timer wait control signal RDY * regardless of the output count value of the 4-bit counter 28.

In this state, when the dedicated bus controller 29 'of the local control I / O device 29 sends a timer wait control signal to the MPU, the access sequence is terminated.

In the access cycle infinity mode, if the I / O device 29 has some abnormality, the timer wait control signal is no longer sent to the MPU, so that the access sequence ends. It will disappear and hang up.

Therefore, in consideration of the above case, an 8-bit counter is provided instead of the 4-bit counter 28, and the bus control unit 27 makes the access cycle infinity mode control signal C.
When YC∞ is input, when the count value of the 8-bit counter reaches the maximum value, a timer wait control signal is forcibly generated and a time-out error is notified to the MPU. This can prevent hang-up.

[0041]

As described above, according to the first aspect of the present invention, the load on the address decoder can be lightened as compared with the prior art, so that efficient access can be realized and the timer can be shared, so that the controlled object can be controlled. The hardware can be greatly simplified as compared with a conventional device having a timer for each.

According to the invention described in claim 2, the access sequence can be terminated by the controlled object, and according to the invention described in claim 3, when the set time access cycle infinity mode continues. Has a feature that it is possible to prevent a hang-up because the timeout error notification is forcibly sent to the MPU.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing an example of an address map.

FIG. 4 is a configuration diagram of a conventional example.

[Explanation of Codes] 11 Central Processing Unit 12 Bus 13 _{1 to} 13 _n Controlled Group 14, 14a Address Decoder 14b Decoder 15 Access Mode Decoder 16 Timer 21 Memory 22, 23 I / O Device 27 Bus Control Unit 284 4-bit Counter 29 Local control I / O device (I / O of access timer infinity control, controlling access cycle and noise on each I / O side) 29 'Dedicated bus control circuit of local control I / O device

Claims (3)

[Claims] 1. A plurality of controlled objects having different access speeds are connected to an asynchronous external bus (12) of the central processing unit (11), and the controlled object is arbitrarily controlled by the central processing unit (11). in the access cycle controller for accessing a plurality of the controlled object, a plurality of groups access cycle is grouped together identical (13 ₁ to 1
3 _n ), an address decoder (14) for selecting any controlled object from the plurality of controlled objects based on the output signal of the central processing unit (11), and the central processing unit (11). An access mode decoder (15) that determines the number of access cycles in parallel with the decoding operation of the address decoder (14) based on the output signal, and monitors the number of access cycles determined by the access mode decoder (15). An access cycle control device, comprising: a timer (16) for outputting a timer wait control signal to the central processing unit (11) to terminate the access sequence when the determined access cycle number is reached. 2. The plurality of groups (13 _{1 to} 13 _n )
The access cycle control device according to claim 1, wherein an address range controlled by infinite access cycles is set in addition to the above. 3. The timer (16) outputs a time-out error signal after a lapse of a set time based on the output of the access mode decoder (15) when the access cycle infinity is selected. Item 2. The access cycle control device according to item 2.