JPH0545117Y2 - - Google Patents

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Publication number
JPH0545117Y2
JPH0545117Y2 JP16427288U JP16427288U JPH0545117Y2 JP H0545117 Y2 JPH0545117 Y2 JP H0545117Y2 JP 16427288 U JP16427288 U JP 16427288U JP 16427288 U JP16427288 U JP 16427288U JP H0545117 Y2 JPH0545117 Y2 JP H0545117Y2
Authority
JP
Japan
Prior art keywords
circuit
output
power supply
current
supply device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP16427288U
Other languages
Japanese (ja)
Other versions
JPH0288476U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16427288U priority Critical patent/JPH0545117Y2/ja
Publication of JPH0288476U publication Critical patent/JPH0288476U/ja
Application granted granted Critical
Publication of JPH0545117Y2 publication Critical patent/JPH0545117Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は直流電流をトランジスタでオン、オフ
して変換トランスの入力巻線に断続的に電流を流
し、出力巻線に生じた交流出力を整流平滑して直
流電力を負荷に供給する所謂スイツチング電源装
置の保護回路に関するものである。
[Detailed description of the invention] This invention turns DC current on and off using a transistor, causes the current to flow intermittently through the input winding of a conversion transformer, rectifies and smoothes the AC output generated in the output winding, and generates DC power. This invention relates to a protection circuit for a so-called switching power supply device that supplies a load.

以下図面により説明する。The following description will be given with reference to the drawings.

第1図は従来の電源装置の回路図、第2図はそ
の動作説明図、第3図は本案による電源装置の1
実施例である。図中、同一符号は同等部分を表わ
す。
Figure 1 is a circuit diagram of a conventional power supply device, Figure 2 is an explanatory diagram of its operation, and Figure 3 is a diagram of a power supply device according to the present invention.
This is an example. In the figures, the same symbols represent equivalent parts.

出力電圧の異なる複数の直流出力を得る場合の
従来の装置を第1図について説明する。
A conventional device for obtaining a plurality of DC outputs having different output voltages will be explained with reference to FIG.

Q1は主スイツチングトランジスタ、E1は電源、
T1は変換トランス、n21,n22は出力巻線、D1
D2はダイオード、L1は平滑インダクター、C2
平滑コンデンサー、L01,L02は負荷である。
Q 1 is the main switching transistor, E 1 is the power supply,
T 1 is a conversion transformer, n 21 , n 22 are output windings, D 1 ,
D 2 is a diode, L 1 is a smoothing inductor, C 2 is a smoothing capacitor, and L 01 and L 02 are loads.

この装置は大きく分けて2つの直流出力、A回
路、B回路と1次側制御回路より構成されてい
る。
This device is roughly divided into two DC outputs, an A circuit, a B circuit, and a primary side control circuit.

A回路は出力巻線21の出力を整流平滑して負
荷L01に供給するもので、出力電圧の検出値をパ
ルス巾制御回路PWMに加へ、主トランジスタQ1
のオン巾を制御して出力電圧V01を安定化するも
のである。
The A circuit rectifies and smoothes the output of the output winding 21 and supplies it to the load L01.The A circuit applies the detected value of the output voltage to the pulse width control circuit PWM, and outputs the output voltage from the main transistor Q1.
The output voltage V 01 is stabilized by controlling the on-width of the voltage V 01 .

B回路は出力巻線n22の出力に接続された整流
ダイオードD3,D4、平滑用インダクターL2、コ
ンデンサC3、可飽和インダクターL3、誤差増巾
器M1、トランジスタQ2よりなる制御回路G2と、
変流器CT2、ダイオードD8、抵抗R12、コンデン
サC12、誤差増巾器M3よりなる電流制限回路。
The B circuit consists of rectifier diodes D 3 and D 4 connected to the output of output winding n 22 , smoothing inductor L 2 , capacitor C 3 , saturable inductor L 3 , error amplifier M 1 , and transistor Q 2 control circuit G 2 ;
A current limiting circuit consisting of a current transformer CT 2 , a diode D 8 , a resistor R 12 , a capacitor C 12 , and an error amplifier M 3 .

CL2より構成される。又、1次側の電流制限検
出回路CL1は変流器CT1、ダイオードD7、抵抗
R11、コンデンサC11、誤差増巾器M2、電源ELよ
り構成されている。なお、PWMは主スイツチン
グトランジスタの制御回路、ERは電源である。
この回路動作は先ず負荷LO1、LO2の負荷電流は
それぞれ変流器CT1、又はCT2により検出され、
ダイオードD7又はD8を通り、抵抗R11、コンデン
サC11又は抵抗R12、コンデンサC12の両端に電圧
を生じ、誤差増巾器M2又はM3により増巾され、
制御回路PWMに入力され、主スイツチングトラ
ンジスタQ1のオン巾を制御して各出力回路の電
圧を垂下させる動作をする。係る従来回路におい
て出力回路Bは、変流器CT2により電流を検出し
誤差増巾器M3にて増巾し、スイツチングトラン
ジスタQ1のON巾を制限する方式では、第2図a
の如く主スイツチングトランジスタQ1のON巾t1
と第2図bの如く可飽和インダクターL3の導通
角t2との差t3の時間は、主スイツチングトランジ
スタQ1のON巾t1を減少しないと出力回路Bの出
力は低下出来ない。即ち負荷変動等により負荷
LO2に過電流が流れた場合、t3の時間がある為、
出力電圧を制御出来ない期間が生じる為、主スイ
ツチングトランジスタQ1は破損に至る場合が多
かつた。又、同時に主スイツチングトランジスタ
Q1に流れる電流を、変流器CT1で検出し、制御
回路PWMを通つてトランジスタQ1のベースに加
えられる信号ループ(CT1−D7−M2−PWM−
Q1−CT1)と、変流器2で検出され、制御回路
PWMを通つて、トランジスタQ1のベースにかけ
られる信号ループ(CT2−D8−M3−PWM−Q1
−T1−CT2)とではゲイン差がある為、過電流
による垂下動作の切り替り点で乱調を起し易いと
いう欠点があつた。
Consists of CL 2 . In addition, the current limit detection circuit CL 1 on the primary side includes a current transformer CT 1 , a diode D 7 , and a resistor.
It consists of R 11 , capacitor C 11 , error amplifier M 2 , and power supply EL. Note that PWM is the control circuit for the main switching transistor, and ER is the power supply.
In this circuit operation, first, the load currents of loads LO 1 and LO 2 are detected by current transformers CT 1 and CT 2 , respectively, and
A voltage is generated across the resistor R 11 , the capacitor C 11 or the resistor R 12 , and the capacitor C 12 through the diode D 7 or D 8 and is amplified by the error amplifier M 2 or M 3 ,
It is input to the control circuit PWM, which controls the on-width of the main switching transistor Q1 and causes the voltage of each output circuit to drop. In such a conventional circuit, the output circuit B detects the current with the current transformer CT2 , amplifies it with the error amplifier M3 , and limits the ON width of the switching transistor Q1 , as shown in Fig. 2a.
The ON width of the main switching transistor Q1 is as follows: t1
As shown in Figure 2b, the time difference t3 between the conduction angle t2 of the saturable inductor L3 is such that the output of the output circuit B cannot be reduced unless the ON width t1 of the main switching transistor Q1 is reduced. . In other words, load changes due to load fluctuations, etc.
If overcurrent flows to LO 2 , there is a time of t 3 , so
Since there is a period when the output voltage cannot be controlled, the main switching transistor Q1 is often damaged. At the same time, the main switching transistor
A signal loop (CT 1 −D 7 −M 2 −PWM−
Q 1 −CT 1 ) and detected by current transformer 2, the control circuit
The signal loop (CT 2 −D 8 −M 3 −PWM− Q 1
-T 1 -CT 2 ), there is a gain difference, so there is a drawback that disturbances are likely to occur at the switching point of drooping operation due to overcurrent.

本考案はかゝる点に鑑みなされたもので、第3
図にその1実施例を示す。本考案は磁気増巾器制
御型出力回路Bを出力巻線n22、可飽和インダク
ターL3、ダイオードD3,D4,D5、D9、誤差増巾
器M1、平滑用インダクターL2、平滑用コンデン
サーC3、制限電流検出用シヤント抵抗R13、及び
トランジスタQ2,Q6等により構成したことを特
徴とする。
The present invention was developed in view of these points, and the third
One example is shown in the figure. The present invention includes a magnetic amplifier controlled output circuit B including an output winding n 22 , a saturable inductor L 3 , diodes D 3 , D 4 , D 5 , D 9 , an error amplifier M 1 , and a smoothing inductor L 2 , a smoothing capacitor C 3 , a shunt resistor R 13 for limiting current detection, and transistors Q 2 and Q 6 .

次にその動作について述べる。今、負荷LO2
電流が増加した場合、シヤント抵抗R13の両端電
圧が上昇し、トランジスタQ6は導通し、コレク
タ電流はダイオードD9を通つて可飽和インダク
ターL3に加えられ、トランジスタQ1のオフ期間
の平滑用インダクターL2の誘起エネルギーを可
飽和インダクターL3のリセツト電流としてL2
Q2−L3−n22−D4−L2の経路で流し、電流制御を
するものである。
Next, we will discuss its operation. Now, if the current in the load LO 2 increases, the voltage across the shunt resistor R 13 increases, the transistor Q 6 becomes conductive, the collector current is applied to the saturable inductor L 3 through the diode D 9 , and the transistor Q The induced energy of the smoothing inductor L2 during the off period of 1 is expressed as the reset current of the saturable inductor L3 as L2
The current is controlled by flowing through the path Q 2 −L 3 −n 22 −D 4 −L 2 .

以上の如く本考案による回路を用いることによ
り、負荷の過電流を確実に制御出来る外、動作が
安定であり、変換効率も良く、回路は簡単で部品
点数も少なく、多巻線出力形スイツチング電源装
置の保護回路として、その実用性、効果は大き
い。
As described above, by using the circuit according to the present invention, the overcurrent of the load can be reliably controlled, the operation is stable, the conversion efficiency is good, the circuit is simple, the number of parts is small, and the multi-winding output type switching power supply Its practicality and effectiveness as a protection circuit for devices is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電源装置の回路図、第2図は動
作説明図、第3図は本案による電源装置の1実施
例である。 Q1……主スイツチングトランジスタ、Q2,Q3
……トランジスタ、E1……電源、T1……変換器、
n21,n22……出力巻線、CT1,CT2……変流器、
D1,D2,D3,D4,D5,D6,D7,D8……整流用
ダイオード、L1,L2……平滑インダクター、L3
……可飽和インダクター、C1,C2,C3,C4
C11,C12……平滑コンデンサー、L01,L02……負
荷、M1,M2,M3……誤差増巾器、PWM……制
御回路、R11,R12,R13……抵抗、EL,ER……
電源。
FIG. 1 is a circuit diagram of a conventional power supply device, FIG. 2 is an operation explanatory diagram, and FIG. 3 is an embodiment of the power supply device according to the present invention. Q 1 ... Main switching transistor, Q 2 , Q 3
...transistor, E 1 ... power supply, T 1 ... converter,
n 21 , n 22 ... Output winding, CT 1 , CT 2 ... Current transformer,
D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , D 8 ... Rectifying diode, L 1 , L 2 ... Smoothing inductor, L 3
...Saturable inductor, C 1 , C 2 , C 3 , C 4 ,
C 11 , C 12 ... Smoothing capacitor, L 01 , L 02 ... Load, M 1 , M 2 , M 3 ... Error amplifier, PWM ... Control circuit, R 11 , R 12 , R 13 ... Resistance, EL, ER...
power supply.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 2次側に直送出力回路と磁気増巾器制御型出力
回路を備えた多巻線出力型スイツチング電源装置
において、前記磁気増巾器制御型出力回路は、平
滑回路のインダクターとコンデンサーの間にシヤ
ント抵抗を設け、該シヤント抵抗を流れる電流の
検出信号により駆動するトランジスタにより磁気
増巾器回路をリセツトして、出力を垂下させるこ
とを特徴とした多巻線出力型スイツチング電源装
置。
In a multi-winding output switching power supply device having a direct output circuit and a magnetic amplifier-controlled output circuit on the secondary side, the magnetic amplifier-controlled output circuit has a shunt between the inductor and the capacitor of the smoothing circuit. 1. A multi-winding output type switching power supply device comprising a resistor and a transistor driven by a detection signal of a current flowing through the shunt resistor to reset a magnetic amplifier circuit and droop the output.
JP16427288U 1988-12-19 1988-12-19 Expired - Lifetime JPH0545117Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16427288U JPH0545117Y2 (en) 1988-12-19 1988-12-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16427288U JPH0545117Y2 (en) 1988-12-19 1988-12-19

Publications (2)

Publication Number Publication Date
JPH0288476U JPH0288476U (en) 1990-07-12
JPH0545117Y2 true JPH0545117Y2 (en) 1993-11-17

Family

ID=31449737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16427288U Expired - Lifetime JPH0545117Y2 (en) 1988-12-19 1988-12-19

Country Status (1)

Country Link
JP (1) JPH0545117Y2 (en)

Also Published As

Publication number Publication date
JPH0288476U (en) 1990-07-12

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