JPH0540703A - Microprocessor - Google Patents

Abstract

PURPOSE:To provide a microprocessor which can self-test an instrustion word in an instruction ROM as the arragement of bits and can test incorporated instruction ROM without the need for giving data for a test from outside. CONSTITUTION:The microprocessor is provided with a data compressor 19 or, furthermore, a register 18 storing the expected value of the output of the data compressor 19 and a comparator circuit 38 outputting a result by comparing the expected value with the output of the data compressor 19. An instruction to input the contents of one or plural instruction words in instruction ROM 11 to the data compressor 19 and to make the data compressor compress it when the data compressor can be used is stored in instruction ROM 11. Furthermore, the microprocessor is provided with a circuit 37 which executes a series of processing inputting the contents of the instruction words in instruction ROM 11 to the data compressor 19 and making the data compressor 19 compress it, and the series of processing outputting a compared result with the expecting value through by using the above-mentioned instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a built-in instruction ROM. More specifically, the instruction word stored in the instruction ROM is self-tested as a sequence of bits for self-diagnosis. The present invention relates to a microprocessor capable of effectively utilizing the capacity of an instruction ROM by using a general instruction word for a self test under a specific mode.

[0002]

2. Description of the Related Art As a conventional microprocessor having a self-test function, the applicant of the present application has previously disclosed Japanese Patent Laid-Open No. 2-1769.
In the invention of the microprocessor disclosed in Japanese Patent Laid-Open No. 43, a microprocessor having a self-test function of a storage means other than the instruction ROM, for example, a register, a RAM, etc., and an arithmetic unit, etc. is proposed.

Hereinafter, the above-mentioned Japanese Patent Laid-Open No. 2-1769 as a conventional example.
The microprocessor which is the invention disclosed in Japanese Patent No. 43 will be described with reference to the block diagram of FIG.

In FIG. 5, reference numeral 1 is an address computing unit (AAU), the input end of which will be described later, but the input end will be described later.
The output end is connected to the bus 23 and the built-in data RAM2. The internal data RAM2 has a bit length of 24 and a word length of 512 (24
It is a 2-port data RAM having a storage capacity of (bits × 512 words), has two ports for reading data, and is connected to the above-mentioned address arithmetic unit (AAU) 1 and the D bus 24 described later. There is.

Reference numeral 3 is a first arithmetic unit input register (R
0) and 4 are second arithmetic unit input registers (R1), each data read port of the built-in data RAM2 is connected to each input terminal, and those input / output terminals are also connected to the D bus 24. Further, their output terminals are also connected to the input terminals of the multiplier (FMPL) 5 and the arithmetic unit (FALU) 7. Multiplier
(FMPL) 5 will be described in detail later, but the output signals from the first arithmetic unit input register (R0) 3 and the second arithmetic unit input register (R1) 4 are input and multiplied to obtain the multiplier output register ( Output to MR) 6.

The multiplier output register (MR) 6 is a multiplier (FMPL)
Holds the result of multiplication by 5 and outputs it to the computing unit (FALU) 7. The arithmetic unit (FALU) 7 will be described later in detail, but the accumulator (AC
The output signals from C) 8, the first arithmetic unit input register (R0) 3, the second arithmetic unit input register (R1) 4 and the multiplier output register (MR) 6 are input. The accumulator (ACC) 8 mainly holds the calculation result by the arithmetic unit (FALU) 7, and is also connected to the D bus 24.

Reference numeral 9 is an 8-level stack,
Holds the value of the program counter (PC) 10 (program counter value) as necessary. Program counter (PC)
Reference numeral 10 sequentially counts addresses in an instruction memory of an instruction to be fetched next, specifically, an internal instruction ROM 11 and an internal shared RAM (CRAM) 12 described later. The output signal from this program counter (PC) 10 is built-in instruction ROM 11 and built-in shared
It is given to RAM (CRAM) 12.

The built-in instruction ROM 11 has a capacity of 32 bits × 4 k words, and outputs the instruction word stored in the address corresponding to the program counter value given from the program counter (PC) 10.

A built-in shared RAM (CRAM) 12 is a memory common to instructions and data and has a capacity of 32 bits × 64 words. The value stored in the internal shared RAM (CRAM) 12 can be used as a data word or an instruction word.

When the value stored in the internal shared RAM (CRAM) 12 is used as an instruction word, the instruction word stored at the address corresponding to the program counter value given from the program counter (PC) 10 is It is output or the value of the instruction register (IR) 13 is stored at that address.

On the other hand, when the value stored in the internal shared RAM (CRAM) 12 is used as a data word, the address corresponding to the address value given from the address arithmetic unit (AAU) 1 or the address input / output terminal 34. Upper 16 bits or lower 16 bits of the data word stored in the I bus
35 is output to the data register (DR) 18 or the data input / output terminal 30 through 35, or the data word is output from the data register (DR) 18 or the data input / output terminal 30 through the I bus 35 to the upper 16 bits or the lower 16 bits of the address. Stored in bits.

At this time, a distinction between upper 16 bits and lower 16 bits is made by a UWI (Upper Word of Instruction) described later.
In addition to being distinguishable by the logical level of the output signal from the signal output terminal 36, since it is reflected in a specific bit of the flag register (FR) 32, it can be determined by a program by a sequence instruction in the instruction set described later. The UWI signal output from the UWI signal output terminal 36 is generated by the control unit of the built-in shared RAM (CRAM) 12, though not shown. Further, the logical values of the specific bits of the UWI signal output terminal 36 and the flag register (FR) 32 are inverted each time the built-in shared RAM (CRAM) 12 is accessed once.

The instruction register (IR) 13 holds an instruction word to be executed next, which is read from the internal instruction ROM 11 or the internal shared RAM (CRAM) 12. The output signal from the instruction register (IR) 13 is the instruction decoder 14, the P bus 23 and the built-in shared RA.
It is given to M (CRAM) 12. The instruction decoder 14 decodes the instruction word held by the instruction register (IR) 13 and controls the operation of each part of the microprocessor based on the decoding result.

Reference numeral 15 is a control register for setting an operation mode inside the microprocessor.
When a reset signal is given from the outside, it is initialized by the reset process. The control register 15 receives an immediate value from the P bus 23, and can also input / output data via the D bus 24. Reference numeral 16 is a direct memory access controller (DMA), 17 is a serial I / O interface (SI / O), and 18 is a data register (DR).
Further, reference numeral 19 is a signature register, which performs pseudo random number generation and data compression.

Reference numeral 20 is an interrupt controller, 21 is a clock / reset signal generation circuit (CLK / RST), and 22 is a clock prescaler (CPR) for dividing an external clock.
Reference numeral 23 is a P bus for inputting an immediate value to a register by an instruction, and reference numeral 24 is each register (reference numerals 3, 4, 8, 15, 1
6, 17, 18, 19, 32), etc., or between the built-in data RAM 2 and program counter (PC) 10 to send and receive data.
The bus 25 is controlled by the direct memory access controller (DMA) 16 during direct memory access, and performs data transmission / reception between the serial I / O interface 17 and the external data memory (not shown) via the output terminal 30. It's a bus.

Reference numeral 26 is a first interrupt signal (INT1) input terminal, 27 is a second interrupt signal (INT2) input terminal, 28 is a test mode setting signal (TEST) input terminal, and 29 is an IIA (Inter) described later.
nalInstruction ROM / RAM Access) Mode setting signal (IIA)
Input terminals, and 34 are non-maskable interrupt signal (NMI) input terminals. Reference numeral 30 is a 24-bit data input / output terminal, which includes the data register (DR) 18, the signature register 19, the D bus 24, the S bus 25, the I bus 35 described later, and an external data memory (not shown). Used for data transfer to and from.

Reference numeral 31 is a reset signal (NRESET) input terminal, which is used to input a reset signal (NRESET) for resetting the entire microprocessor. Reference numeral 32 is a flag register (FR) that indicates the operation result of the operation unit (FALU) 7, the logic level of each input terminal or the internal operation mode of this microprocessor. The flag register (FR) 32 is initialized by the reset process when the above-mentioned reset signal (NRESET) is input.

Reference numeral 33 is a clock signal (CLK) input terminal, and the microprocessor of this conventional example operates in synchronization with the clock signal (CLK) input from the clock signal input terminal 33. Reference numeral 34 is an address input / output terminal having a 16-bit length, which outputs an address to be given to an external data memory (not shown), and outputs the address of the internal instruction ROM 11 and the internal shared RAM (CRAM) 12 in the IIA mode described later. Input from outside and specify.

Reference numeral 35 is an I bus used for transferring data between the built-in instruction ROM 11 or the built-in shared RAM (CRAM) 12 and the data register (DR) 18 or the data input / output terminal 30. It has a bit length of bits. Reference numeral 36 indicates UWI (Up) indicating whether the data transferred by the I bus 35 is for the upper 16 bits or the lower 16 bits of the internal instruction ROM 11 or the internal shared RAM (CRAM) 12.
per Word of Instruction) signal output terminal.

Next, the operation of the conventional microprocessor shown in FIG. 5 will be described.

In this conventional microprocessor, the instruction word has a bit length of 32 bits and the data word has a bit length of 24 bits.
It consists of memory block and clock generator functional blocks. The structure and operation of each functional block of the conventional microprocessor will be sequentially described below.

The address calculation unit is the address calculation unit (A
AU) 1 itself. The address arithmetic unit (AAU) 1 has an address mode set in advance by a predetermined instruction (hereinafter referred to as residual control). According to the set mode, the internal data RAM 2, the internal shared RAM (CRAM) 12 or An address for an external data RAM (not shown) is generated.

The operation of address generation by the address calculation unit (AAU) 1 will be described below. As a register for residual control, the address arithmetic unit (AAU) 1 has an address for the built-in data RAM 2 and a built-in shared RAM (CR
AM) 12 or an address register (A that gives the lower 9 bits of the address to an external data RAM not shown)
R0, AR1, AR2), built-in shared RAM (CRAM) 12 or page register (PGR) that gives the upper 7 bits of the address to an external data RAM (not shown), base value address register that gives the base value for generating the address (BA0, BA1,
BA2), increment value register (I0, I1, I2) that gives the added value when generating the address, modulo value or modulo value that gives the bit reverse width-bit reverse width register (ML0, ML1, ML2), at the time of loop instruction Delta base value address register to qualify the base address value
(DBA0), Delta increment value register (DI0) for modifying the increment value at loop instruction are included. The value of each of these registers is basically set by the mode instruction described below, but there is also a register that can be changed by an operation instruction.

The address calculation unit (AAU) 1 has three registers AR0, AR1 and AR2 as address registers,
Each register is controlled by an individual address arithmetic circuit. The lower 9 addresses of the address for one port 0 of the built-in data RAM 2 and the built-in shared RAM (CRAM) 12 or the address for the external data RAM not shown.
The bit is designated by the address register AR0 or AR1 and the address for the other port 1 of the built-in data RAM2 is designated by the address register AR2.

Regarding the register AR0, according to the contents of the register relating to the above-mentioned residual control, it is possible to perform increment, modulo, bit reverse and repeat 4
Addressing by mode is possible, and the base address value, increment value, modulo value, and bit reverse width can be set independently.

Further, in the registers AR1 and AR2, addressing in two modes of increment and modulo is possible, and the base address value, increment value, and modulo width can be set independently like the register AR0. Further, for the port 1 of the built-in data RAM2, direct addressing using an immediate value included in the instruction word as an address is also possible.

Next, the structure of the arithmetic unit will be described. The arithmetic unit is the first arithmetic unit input register shown in FIG.
(R0) 3 and second arithmetic unit input register (R1) 4, multiplier (F
It is composed of MPL) 5, multiplier output register (MR) 6, arithmetic unit (FALU) 7 and accumulator (ACC) 8.

The operation unit has three types of operation data for 24-bit floating point data of 16-bit mantissa and 8-bit exponent, 24-bit fixed-point data, and 24-bit logical data. Performs 31 types of calculations.

The multiplier (FMPL) 5 floats every machine cycle regardless of the instruction, depending on the values input to the first arithmetic unit input register (R0) 3 and the second arithmetic unit input register (R1) 4. The decimal point multiplication result is output to the multiplier output register (MR) 6. However, when the alu field of the operation instruction described later specifies an operation for fixed-point data, the first operation unit input register (R0) 3 and the second operation unit input register (R0)
It outputs the upper or lower 24 bits of the upper or lower 16-bit multiplication result (32 bits) of the operation unit input register (R1) 4 to the multiplier output register (MR) 6.

In the arithmetic unit (FALU) 7, the first arithmetic unit input register (R0) 3 or the accumulator (ACC) 8 is used as an input register for the x input which is one of the two inputs.
However, the other input, y input, is provided with the second arithmetic unit input register (R1) 4 or the multiplier output register (MR) 6, respectively.
The calculation is executed in the machine cycle and the calculation result is output to the accumulator (ACC) 8.

Next, an outline of the memory section will be described. The memory unit is a 2-port built-in data RAM 2 shown in FIG.
It consists of built-in instruction ROM 11 and built-in shared RAM (CRAM) 12.

An area of 4 k words is allocated as the instruction memory space, and a built-in instruction ROM 11 is incorporated therein. As a data memory space, an area of 512 words is allocated inside the microprocessor.
AM2 is incorporated. The built-in data RAM 2 can execute 2 data read using port 0 and port 1 and 1 data write using only one of the ports in one machine cycle. An area of 60 kwords is allocated as an extended data RAM space outside the microprocessor. Further, 4k words are allocated as a shared memory space between the instruction memory and the data memory, and a built-in shared RAM (CRAM) 12 of 64 words is incorporated in the microprocessor.

Next, the clock generator will be described.
The clock generation unit is composed of a clock / reset signal generation circuit (CLK / RST) 21 and a clock prescaler (CPR) 22 shown in FIG. The clock generation unit divides the external clock by the clock prescaler 22 according to the clock prescale value set in a clock prescale value register (not shown) by a predetermined instruction, generates a non-overlapping four-phase clock, and sends it to each unit of the microprocessor. We are supplying.

Clock / reset signal generation circuit (CLK / RS
The T) 21 normally resets the program counter (PC) 10 to a predetermined fixed address when the reset signal (NRESET) input from the reset signal (NRESET) input terminal 31 turns active. However, when the reset signal (NRESET) turns inactive, the first interrupt signal input terminal 26, the second interrupt signal input terminal 26,
If the first interrupt signal (INT1) and the second interrupt signal (INT2) input to the interrupt signal input terminal 27 are active, the contents of the data register (DR) 18 are transferred to the program counter (PC ) Transfer to 10. By using this function, if arbitrary data is externally written in the data register (DR) 18 in advance, a reset process for starting the program from an arbitrary address is possible.

Next, the instruction format in the microprocessor configured as described above will be described. The instruction word length is 32 bits, and the types of instructions are roughly classified into four types: sequence instruction group, mode instruction group, operation instruction group, and load instruction group.

In the sequence instruction group, there are mainly 8 kinds of instructions related to branch, in the mode instruction group there are 7 kinds of instructions for setting data to each register, in the operation instruction group there are 7 kinds of instructions related to operation, and in the load instruction group there are immediate values. There are two types of instructions to set in registers. Except for the load instruction group, the upper 5 bits (27th
Each instruction in the group is identified by the decoding result (bits to 31st bit), and the remaining 27 bits are assigned to each field shown below.

First, in the sequence instruction group, FIG.
The fields are assigned as shown in FIG.

FIG. 6 shows the bit arrangement of the sequence instruction. The 27th bit to the 29th bit are as shown in FIG.
This is a field that specifies the type of sequence. 23rd
Bits to 26th bit are fields for designating a change in the initial value of the loop counter or a change in the addressing modification at the time of looping, as shown in FIGS. 10, 11, 12, and 13. The 19th to 23rd bits are fields for setting the branch condition of the conditional jump as shown in FIG. The 0th bit to the 15th bit are fields for designating the jump destination address, and the 4th, 5th, and 6th bits of them are the contents held in the register as the jump destination address, as shown in FIG. This field is also used to specify the indirect jump register.

In the mode instruction group, FIGS.
The fields are assigned as shown in.

FIG. 14 shows the bit arrangement of the mode instruction. The 27th bit to the 29th bit are as shown in FIG.
This is a field for specifying the type of mode command. Of these, the WINCR instruction shown by the mnemonic in FIG. 15 is the WINCR instruction other than the ENDWC instruction shown by the mnemonic in FIG. 15 for the instruction word from the next address where this instruction word is located in the internal instruction ROM 11. Instruction register without executing
It is an instruction to write to the internal shared RAM (CRAM) 12 as it is after passing through the (IR) 13, and the start address of the write destination is shown in Fig. 14.
It is specified by the sum of the address specified by the mnemonic wa and the hexadecimal number F000. In addition, the processing by this instruction is performed by changing the addresses of the internal instruction ROM 11 and the internal shared RAM (CRAM) 12 until the ENDWC instruction shown by the mnemonic in FIG. 15, that is, the instruction to stop the execution of the WINCR instruction is executed. Both are continued while incrementing by "1".

The 26th bit uses the register AR0 for addressing the port 0 of the built-in data RAM2 under the residual control as shown in FIG.
This field indicates whether to use 1.

The 25th bit is a field indicating whether to use the register AR0 or the register AR1 for the lower 9 bits of the address designation of an external data RAM or a built-in shared RAM (CRAM) 12, which is not shown, as shown in FIG. is there. The upper 7 bits of the address designation are the address calculation unit (AA
It is specified by a page register (PGR) not shown in U) 1.

As shown in FIG. 18, the 0th bit to the 3rd bit are fields for selecting which register the value is set to. The immediate value to be set is the 4th bit shown in FIG. ~ Specified by the 22nd bit. Of this,
The second and third CR registers in the control register 15
The bit is the AC specified in the aco field of the operation instruction when the accumulator (ACC) 8 is specified as the source register for the bus transfer of the operation instruction described later.
These bits specify the method of selecting the register actually used as the source register for the C0, ACC1, ACC2, and ACC3 registers. After the reset processing, b3-b2 = "00" and the register specified by the aco field is used. However, when b3-b2 = "01", the register specified by the aco field + 1 is selected. In this case, specifically, if the ACC0 register is specified, the ACC1 register is used as the source register for the bus transfer.The ACC1 register specifies the ACC2 register, the ACC2 register specifies the ACC3 register, and the ACC3 register specifies the ACC0 register. Each register is used.

In the operation instruction group, FIG.
The fields are assigned as shown in FIG.

FIG. 19 shows the bit arrangement of the operation instruction. The 27th bit to the 29th bit are fields for designating the type of operation instruction, as shown in FIG.

The 26th bit is a field indicating whether or not direct addressing is performed. When direct addressing is performed, the D bus 24 is used as shown in FIG.
The source register and the destination register of the data transfer performed via are specified by the 5th to 7th bits, and for the port 1 of the internal data RAM2, the 5 bits specified by the mnemonic dadisp in FIG. 19 are immediate addresses. Is specified as.

The 23rd, 24th, and 25th bits are fields indicating whether or not the registers AR0, AR1, and AR2 are updated by residual control, respectively. The 22nd bit indicates whether to write the contents of the data register (DR) 18 to the external data RAM (not shown) or the internal shared RAM (CRAM) 12, and the 21st bit is the external data RAM or internal shared RAM (CRAM) not shown. This field controls whether to read data from 12 to the data register (DR) 18.

The 19th and 20th bits indicate the contents of the internal data RAM 2 written at the address indicated by the address register as the first bit.
This is a field for controlling whether or not to write to the arithmetic unit input register (R0) 3 and the second arithmetic unit input register (R1) 4. The 17th and 18th bits are a field for selecting an input register to the arithmetic unit (FALU) 7.

As shown in FIGS. 30 and 31, the 12th to 16th bits are fields for designating the operation of the operation unit (FALU) 7, and are particularly called alu fields. 10th, 1st
As shown in FIG. 22 and FIG. 23, 1 bit corresponds to a computing unit (FAL
(U) It is a field that specifies the accumulator to input the operation result of 7, and the NOP described later in the alu field.
Alternatively, it is also a field for further specifying the destination register of the data transfer performed via the D bus 24 when the accumulator (ACC) 8 is specified as the destination register.

As shown in FIGS. 24 and 25, the 8th and 9th bits are a field for designating an output accumulator, and when an accumulator (ACC) 8 is designated as a NOP or a source register in the alu field, D
It is also a field that further specifies the source register of the data transfer performed via the bus 24. 4th bit ~
The 7th bit is the D bus 24 as shown in FIGS.
Is a field indicating the source register of the data transfer performed via. The 0th bit to the 3rd bit are fields for designating the destination register of the data transfer performed via the D bus 24, as shown in FIGS. 28 and 29.

The alu field shown in FIGS. 30 and 31 will be described in more detail. In addition, arithmetic unit (FAL
Of the two inputs to U) 7, the first arithmetic unit input register (R0) 3
Or input from accumulator (ACC) 8 is x input, second
Arithmetic unit input register (R1) 4 or multiplier output register
The input from (MR) 6 is the y input, and the accumulator (ACC) 8
Let the output signal to z output be z output.

NOP is an instruction that the arithmetic unit (FALU) 7 does not calculate anything, and both the x input and the y input are arithmetic units (FALU).
It is not input to 7, so the z output does not change. INV
Is an instruction that regards x input data as floating point data and inverts its sign to output z. ABS is an instruction that regards x input data as floating point data and outputs its absolute value as z.

SGN regards x input data and y input data as floating point data, and multiplies the absolute value of x by the sign of y (1 is a positive number and -1 is a negative number) and z It is an instruction to output. ADD is an instruction that regards x input data and y input data as floating point data, adds them, and outputs z. SUB regards x input data and y input data as floating point data, subtracts y from x, and z
It is an instruction to output.

In MAX, the data of x input and the data of y input are regarded as floating point data and compared, and the larger one is z.
It is an instruction to output. MIN is an instruction for comparing the data of x input and the data of y input as floating point data and comparing them, and outputting the smaller one as z. THR is an instruction to output y input data to z as it is.

The XFT is an instruction that regards x input data as fixed point data, converts it into floating point data according to the mode set in the control register 15, and outputs z. FXT is an instruction that regards x input data as floating point data, converts it into fixed point data according to the mode set in the control register 15, and outputs z. SR1 is an instruction that regards x input data as logical data, shifts it to the right by 1 bit, and outputs z.

SL1 is an instruction for treating the data of x input as logical data, shifting left by 1 bit, and outputting z. SL
Reference numeral 2 is an instruction which regards x input data as logical data and shifts it to the left by 2 bits and outputs z. SL4 considers the data of x input as logical data and shifts to the left by 4 bits, and z
It is an instruction to output.

SL8 is an instruction that regards x input data as logical data, shifts it 8 bits to the left, and outputs z. In each of the SR1, SL1, SL2, SL4, and SL8 instructions, the data shifted in is 0.

AND is an instruction to regard the x-input data and the y-input data as logical data, perform a logical product, and output z. The OR is an instruction to regard the x-input data and the y-input data as logical data, perform a logical sum, and output z. The EOR is an instruction to regard the x-input data and the y-input data as logical data, perform an exclusive OR, and output z.

NOT is an instruction that regards x input data as logical data, performs logical NOT, and outputs z. MAD
Is an instruction that performs fixed point addition of the lower 16 bits of x input data and y input data and outputs z. However, the exponent part of the input data is ignored, and the upper 8 bits of z output are "0". Is output. The ESB is an instruction that performs fixed point subtraction on the upper 8 bits of the x input data and the y input data and outputs z. However, the mantissa part of the input data is ignored, and the lower 16 bits of the z output has 16 bits. The decimal number 8000 is output.

IMUL is an instruction that causes the multiplier (FMPL) 5 to perform fixed-point multiplication without performing anything to the arithmetic unit (FALU) 7. The IADD is an instruction that regards x input data and y input data as fixed point data, adds them, and outputs z. The ISUB is an instruction that regards x input data and y input data as fixed point data, subtracts y from x, and outputs z.

The IADC regards the data of the x input and the data of the y input as fixed point data, performs addition of these two numbers and the carry bit in the flag register (FR) 32, and z
It is an instruction to output. ISBB regards x input data and y input data as fixed-point data, subtracts y input data from x input data, and further, flag register (FR) 32
This is an instruction for subtracting the carry bit in the above and outputting z.

ASR1 is an instruction that regards x input data as fixed point data, shifts it right by 1 bit, and outputs z. ASR2 is an instruction that regards x-input data as fixed-point data, performs 2-bit right shift, and outputs z.

The ASR4 is an instruction that regards x input data as fixed point data, performs a 4-bit right shift, and outputs z. ASR8 is an instruction that regards x input data as fixed-point data, performs 8-bit right shift, and outputs z. The shift-in data in each of the ASR1, ASR2, ASR4, and ASR8 instructions is a sign bit (the most significant bit of x input).

In the load instruction group, the most significant 3 bits (29th, 30th, 31st bits) are used to divide into a load instruction and a long load instruction. Also, in the load instruction,
The fields are assigned as shown in FIGS. It should be noted that the load instruction can specify an immediate value of 18 bits in this conventional example, and the long load instruction can specify an immediate value of 24 bits which is a longer bit length.

FIG. 32 shows the bit arrangement of the load instruction. The 28th bit is a field for selecting whether to write the contents of the data register (DR) 18 to an external data RAM (not shown) or a built-in shared RAM (CRAM) 12, as shown in FIG. As shown in FIG. 34, the 26th and 27th bits are ACC0 to ACC0 (not shown) in the accumulator (ACC) 8 when the register for writing an immediate value is the accumulator (ACC) 8.
In addition to specifying which accumulator of ACC3,
Flag register (FR) 32, control register (CR, SR) 1
5, various registers in the address calculation unit (AAU) 1 (address register (AR0, AR1, AR2), base address value register (B
A0, BA1, BA2), increment value register (I0, I1, I
This is a field that specifies in which register of 2)) the immediate value is written.

The 23rd, 24th, and 25th bits are, as shown in FIG. 35, the address register (AR0, AR0,
This is a field for selecting whether to update the contents of (AR1, AR2). The 22nd bit is the D bus 24 as shown in FIG.
This is a field for selecting whether to write an immediate value to 18 bits on the MSB (23rd bit) side of the 24 bits of, or to write an immediate value to 18 bits on the LSB (0th bit) side.

The 4th to 21st bits are a field for designating an immediate value to be written in the register. 0th bit to 3rd
The bit is a field for designating a register for writing an immediate value, as shown in FIG.

Fields are allocated to the long load instruction as shown in FIGS. 38 and 39. FIG. 38 shows the bit arrangement of the long load instruction. The 28th bit is the external data not shown in the contents of the data register (DR) 18.
This field is used to select whether to write to RAM or built-in shared RAM (CRAM) 12. The 4th bit to the 27th bit are fields for specifying an immediate value. The 0th, 1st, 2nd and 3rd bits are, as shown in FIG. 39, a field for designating a register for writing an immediate value.

Next, the operation mode of the above conventional microprocessor will be described. In addition to the normal mode, the operation modes of this microprocessor include the following test modes.

First, there is a pin test mode in which the output state or output level of the data input / output terminal 30, the address input / output terminal 34, and an output terminal (not shown) can be set independently of the internal operation of the microprocessor. .. Next, in the second mode, the values of the D bus 24 and program counter (PC) 10 that are difficult to observe in the normal mode are changed to the data input / output terminal 30
And the PEEP mode in which the address input / output terminal 34 outputs to the outside.

Third, by executing the instruction, the data register
(DR) 18 or the serial input register (SI0, SI1) (not shown) in the serial I / O interface 17 is used in the signature register 19 instead of the source register for the bus transfer using the D bus 24. Use a pseudo random number generator (not shown) as a source register for bus transfer, or use a data register (DR) 18 or a serial output register (SO0, SO1) (not shown) in the serial I / O interface 17 as D. When used as a destination register for bus transfer using the bus 24, a self-test mode is used in which a data compressor (not shown) in the signature register 19 is used as a destination register for bus transfer instead.

Fourth, built-in instruction ROM 11 or built-in shared
The address of RAM (CRAM) 12 is input to the address input / output terminal 34 from the outside of the microprocessor and the contents of the internal instruction ROM 11 or internal shared RAM (CRAM) 12 is read from the data input / output terminal 30 or the data input / output terminal 13 IIA (Internal Instruction ROM / RAM) that can write data input from the built-in instruction ROM 11 or built-in shared RAM (CRAM) 12
Access) mode.

The pseudo random number generator and the data compressor (not shown) in the signature register 19 are independent of each other and are initialized by the reset process. Also,
The pseudo random number generator outputs a new random number each time it is accessed as a source register, and the data compressor performs signature compression of the data output from the source register each time it is accessed as a destination register.

The above-mentioned mode switching is performed by combining the logical levels of the input signals to the TEST mode setting signal input terminal 28 and the IIA mode setting signal input terminal 29. Next, a method of testing the arithmetic unit (FALU) 7 using the self-test mode among the above test modes will be described.

The test of the arithmetic unit (FALU) 7 is performed by executing an arithmetic operation with various input values for each arithmetic operation and examining the result. Also, for certain types of operations (such as IADC operations), the value of the flag register (FR) 32 set by the previously executed operation is used, so the history of operation execution becomes a problem. .. Therefore, the arithmetic unit (FAL
Consider the case where the random number output from the pseudo-random number generator is used for the input value of U) 7 and the calculation result is compressed by the data compressor.

Each time a data register (DR) 18 is designated by a command as a source register for bus transfer using the D bus 24, new pseudo random number data is obtained. By transferring this pseudo random number data to the first arithmetic unit input register (R0) 3 and the second arithmetic unit input register (R1) 4, various arithmetic input values for the arithmetic unit (FALU) 7 can be obtained. ..
Then, if the operation result of the operation unit (FALU) 7 is designated as the destination register, for example, the data register (DR) 18 is designated and is transferred to the bus using the D bus 24, the operation result is signature-compressed.

The above-mentioned operation can be realized by a few instructions, and by using a multiple loop, it is possible to test an arithmetic unit using a large number of pseudo random numbers with a small number of instructions. The test execution result is the final result after the test is completed.
By comparing with the final signature output by the microprocessor confirmed to operate normally, the final signature by computer simulation, or the like, it is possible to determine whether or not the operation is normal.

Next, an example of the self-test program of the arithmetic unit (FALU) 7 of the microprocessor having such a test function will be described with reference to FIGS. 40, 41, 42, 43 and 4.
4, FIG. 45, and FIG. 46 are flowcharts showing the processing procedure in FIGS. 47, 48, 49, and 50. As shown in FIG. 47, this self-test program is configured so that many tests can be performed with a smaller number of instructions by using a double loop.

FIG. 49 is a flow chart showing the processing procedure of the module 1. First of all, the signature register
From the pseudo random number generator in 19 to the first arithmetic unit input register (R
0) 3 and the second arithmetic unit input register (R1) 4 is set to a pseudo random number, the arithmetic unit (FALU) 7 is caused to execute the arithmetic operation, and the arithmetic result is transferred to the data compressor in the signature register 19. Simultaneously with compression, flag register (FR) for each operation
The contents of 32 are checked, and the conditional jump test according to the contents of the flag register (FR) 32 is also conducted by the module 3 shown in FIG. In this module, the number of steps in the test program is reduced by combining the one-input operation and the two-input operation.

FIG. 50 is a flow chart showing the processing procedure of the module 2. This module 2 is module 1
Is a module that receives the carry of the previous instruction stored in the flag register (FR) 32, performs an operation, and transfers the data to the data compressor in the signature register 19.

The operations shown in the flow charts of FIGS. 47 to 51 are applied to all the operations that can be executed by the operation unit (FALU) 7 in FIG. 5, that is, the alu field shown in FIGS. 19 to 31. Calculation of INV, ABS, SGN, ADD, SUB, MA
X, MIN, THR, XFT, FXT, SR1, SL1, SL2, SL4, SL8, AN
D, OR, EOR, NOT, MAD, ESB, IADD, ISUB, IADC, ISBB,
Performs ASR1, ASR2, ASR4, ASR8.

The program shown in FIGS. 40 to 46 is a combination of these modules and is expressed as one program. This program consists of as few as 120 words.

In the above example, the test of the arithmetic unit has been described as an example. However, in the test of the built-in data RAM 2 and the built-in shared RAM (CRAM) 12 in the memory unit, the address register is sequentially used by using the residual control. While changing the random number generated by the pseudo-random number generator, the built-in data RAM2 and built-in shared RAM (CR
This can be easily done by writing a program in (AM) 12, then reading it out and executing a program to compress it in the data compressor.

FIG. 52 is a schematic diagram showing how the self-test programs shown in FIGS. 40 to 46 are arranged in the instruction memory space of the internal instruction ROM 11 shown in FIG. By adopting such a memory space configuration, in the normal mode, the user program or the like having the hexadecimal address 0000 as the start address for the reset process is executed. However, when the self-test is executed, the self-test as described above is executed by utilizing the reset process capable of reset start from the above-mentioned arbitrary address.

Next, a method of testing the built-in instruction ROM 11 will be described. However, since the contents stored in the built-in instruction ROM 11 cannot be directly handled by instructions, the IIA mode described above is used.

In the IIA mode, when the address to be read in the internal instruction ROM 11 is input to the address input terminal 34,
The lower 16 bits or the upper 16 bits of the contents of the instruction word stored at the designated address are transferred through the I bus 35 and output from the data input / output terminal 30. Whether the output data is the lower 16 bits or the upper 16 bits of the contents stored in the built-in instruction ROM 11 can be distinguished by the logic level appearing at the UWI signal output terminal 36. Therefore, when testing the built-in instruction ROM 11, it is necessary to input a value that covers the entire address range of the built-in instruction ROM 11 from the outside of the microprocessor from the address input terminal 34, and to check the values that are sequentially output from the data input / output terminal 30. There is.

[0087]

In the conventional microprocessor as described above, the built-in instruction ROM 11 (4k words × 32 bits, that is, about 130,000 storage elements) is checked by the self-test that can be easily performed by the user. Since it is not performed, it is necessary to prepare the test data of the internal instruction ROM 11 externally and check it in IIA mode. Therefore, the test jig becomes complicated, and the user's acceptance test becomes complicated.

The present invention has been made in view of the above circumstances, and a built-in instruction ROM can be tested without the need for externally supplying test data, and a micro test with a fault detection rate improved by a simple test. The purpose is to provide a processor. Another object of the present invention is to provide a microprocessor capable of saving software by also using the instructions of a conventional microprocessor as instructions for testing a built-in ROM.

[0089]

According to a first aspect of the present invention, there is provided an instruction ROM in which a plurality of instructions constituting a program are stored, and a data compressor for compressing and outputting input data. , With an input terminal for inputting a signal that allows the use of a data compressor,
If the above signal is input to the input terminal, the instruction RO
A microprocessor in which instructions for inputting the contents of one or more instruction words in M to a data compressor for compression are stored in an instruction ROM, and further using the above-mentioned instructions, the instruction words in the instruction ROM It is characterized by comprising means for executing a series of processing for inputting and compressing contents into a data compressor.

The second aspect of the microprocessor of the present invention is to provide an instruction ROM storing a plurality of instructions forming a program, a data compressor for compressing and outputting input data, and a data compressor. An input terminal for inputting a signal that enables use, storage means for storing an expected value of an output signal from the data compressor, an expected value stored in the storage means and an output signal from the data compressor And a comparison means for outputting the result, and when the above-mentioned signal is inputted to the input terminal, the contents of one or more instruction words in the instruction ROM are inputted to the data compressor. A microprocessor in which instructions to be compressed are stored in an instruction ROM
It is characterized in that it comprises means for executing a series of processes for inputting the contents of the instruction word therein to the data compressor for compression and outputting the result of comparison by the means for comparing with the expected value.

Furthermore, a third invention of the microprocessor of the present invention comprises, in addition to the first invention, an instruction RAM for storing a plurality of instructions constituting a program, and the aforementioned signal is inputted to the aforementioned input terminal. If there is not, it has an instruction to store the contents of one or more instruction words in the instruction ROM into the instruction RAM. If this instruction has the above-mentioned signal input to the input terminal, it is regarded as the instruction of the first invention. It is characterized in that it is configured to function.

Furthermore, a fourth invention of the microprocessor of the present invention comprises, in addition to the second invention, an instruction RAM for storing a plurality of instructions constituting a program, and the above-mentioned signal is inputted to the above-mentioned input terminal. If there is not, it has an instruction to store the contents of one or more instruction words in the instruction ROM in the instruction RAM. If this instruction has the above-mentioned signal input to the input terminal, it is regarded as the instruction of the second invention. It is characterized in that it is configured to function.

Furthermore, a fifth invention of the microprocessor of the present invention comprises a data storage circuit in addition to the first invention, and data processed by a program when the aforementioned signal is not input to the aforementioned input terminal. In the case where there is an instruction to read one or more data of the data storage circuit for storing the data or an instruction to write one or more data to the data storage circuit, and this instruction is input to the above-mentioned signal at the input terminal. Is configured so as to function as the instruction of the first invention.

Furthermore, a sixth invention of the microprocessor of the present invention comprises a data storage circuit in addition to the second invention, and stores data to be processed by a program when the aforementioned signal is not input to the aforementioned input terminal. When there is an instruction to read one or more data of the data storage circuit to be stored or an instruction to write one or more data to the data storage circuit, and this instruction is applied when the aforementioned signal is input to the input terminal. Is configured to function as the instruction of the second invention.

[0095]

According to the first aspect of the microprocessor of the present invention, when the data compressor can be used, a series of processes using the instructions stored in the instruction ROM are executed, and the instruction RO
The contents of each instruction word in M are sequentially read and input to the data compressor for compression.

Further, in the second invention, the result of comparison between the result compressed by the data compressor and its expected value is output to the outside.

In the third aspect of the invention, when a predetermined signal is input to the input terminal, the instruction word which constitutes the normal program previously stored in the instruction ROM is once stored in the RAM, and this RAM is stored in this RAM. The stored instructions operate similarly to the first invention.

In the fourth aspect of the present invention, when a predetermined signal is input to the input terminal, the instruction word which constitutes the normal program previously stored in the instruction ROM is temporarily stored in the RAM, and this RAM is stored in the RAM. The stored instructions operate similarly to the second invention.

In the fifth aspect of the invention, when a predetermined signal is input to the input terminal, normally, the instruction word previously stored in the instruction ROM for inputting / outputting data to / from the data storage circuit. Is temporarily stored in the RAM, and the instruction stored in the RAM causes the same operation as in the first invention.

According to the sixth aspect of the invention, when a predetermined signal is input to the input terminal, normally, an instruction word stored in advance in the instruction ROM for inputting / outputting data to / from the data storage circuit. Is temporarily stored in the RAM, and the instruction stored in the RAM operates similarly to the second invention.

[0101]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. In each of the drawings referred to in the description of the present invention, the same reference numerals as those in the above-described drawings referred to in the description of the conventional example indicate the same or corresponding portions.

[Embodiment 1] First, a first embodiment of the microprocessor of the present invention will be described. In the first embodiment, the first to fourth embodiments described in claims 1 to 4 are described. Inventions are included. 1 is a block diagram showing a configuration example of a first embodiment of a microprocessor according to the present invention. In FIG. 1, reference numeral 1 is an address calculation unit.
(AAU), the input end is P bus 23
The output terminals are connected to the built-in data RAM2, respectively.

The built-in data RAM2 has a bit length of 24 and a word length of 51.
It is a 2-port data RAM with a storage capacity of 2 (24 bits x 512 words), has two ports for reading data, and has the above-mentioned address operation unit (AAU) 1 and the D bus 24 described later. It is connected. Reference numeral 3 is the first arithmetic unit input register (R0), and 4 is the second arithmetic unit input register
(R1), each data read port of the built-in data RAM2 is connected to each input end, the input / output ends are also connected to the D bus 24, and the output end thereof is a multiplier ( It is also connected to the input terminals of FMPL) 5 and arithmetic unit (FALU) 7.

The multiplier (FMPL) 5 will be described in detail later.
The output signals from the arithmetic unit input register (R0) 3 and the second arithmetic unit input register (R1) 4 are input, multiplied, and output to the multiplier output register (MR) 6. Multiplier output register (MR)
6 holds the multiplication result of the multiplier (FMPL) 5, and the arithmetic unit (FALU)
Output to 7. The arithmetic unit (FALU) 7 will be described in detail later, but the accumulator (ACC) 8 and the first arithmetic unit input register (R0)
3, output signals from the second arithmetic unit input register (R1) 4 and the multiplier output register (MR) 6 are input. The accumulator (ACC) 8 mainly holds the arithmetic result of the arithmetic unit (FALU) 7, and is also connected to the D bus 24.

Reference numeral 9 is an 8-level stack,
Holds the value of the program counter (PC) 10 (program counter value) as necessary. Program counter (PC)
Reference numeral 10 sequentially counts addresses in an instruction memory of an instruction to be fetched next, specifically, an internal instruction ROM 11 and an internal shared RAM (CRAM) 12 described later. The output signal from this program counter (PC) 10 is built-in instruction ROM 11 and built-in shared
It is given to RAM (CRAM) 12.

The built-in instruction ROM 11 has a capacity of 32 bits × 4 k words, and outputs the instruction word stored in the address corresponding to the program counter value given from the program counter (PC) 10. A built-in shared RAM (CRAM) 12 is a memory common to instructions and data, and has a capacity of 32 bits × 64 words. The value stored in the internal shared RAM (CRAM) 12 can be used as a data word or an instruction word.

When the value stored in the internal shared RAM (CRAM) 12 is used as the instruction word, the instruction word stored at the address corresponding to the program counter value given from the program counter (PC) 10 is It is output or the value of the instruction register (IR) 13 is stored at that address.

On the other hand, when the value stored in the built-in shared RAM (CRAM) 12 is used as a data word, the address corresponding to the address value given from the address arithmetic unit (AAU) 1 or the address input / output terminal 34. Upper 16 bits or lower 16 bits of the data word stored in the I bus
35 is output to the data register (DR) 18 or the data input / output terminal 30 through 35, or the data word is output from the data register (DR) 18 or the data input / output terminal 30 through the I bus 35 to the upper 16 bits or the lower 16 bits of the address. Stored in bits.

At this time, the distinction between the upper 16 bits and the lower 16 bits is made by UWI (Upper Word of Instruction) described later.
In addition to being distinguishable by the logical level of the output signal from the signal output terminal 36, since it is reflected in a specific bit of the flag register (FR) 32, it can be determined by a program by a sequence instruction in the instruction set described later. The UWI signal output from the UWI signal output terminal 36 is generated by the control unit of the built-in shared RAM (CRAM) 12, though not shown. Further, the logical values of the specific bits of the UWI signal output terminal 36 and the flag register (FR) 32 are inverted each time the built-in shared RAM (CRAM) 12 is accessed once.

The instruction register (IR) 13 holds the instruction word to be executed next, which is read from the internal instruction ROM 11 or the internal shared RAM (CRAM) 12. The output signal from the instruction register (IR) 13 is the instruction decoder 14, P bus 23 and built-in shared RAM.
(CRAM) 12 is given. The instruction decoder 14 decodes the instruction word held by the instruction register (IR) 13 and controls the operation of each part of the microprocessor based on the decoding result.

Reference numeral 15 is a control register for setting the operation mode inside the microprocessor.
It is initialized by the reset process. The control register 15 receives an immediate value from the P bus 23 and also has a D bus 24.
It is possible to input and output data via. Reference numeral 16 is a direct memory access controller (DMA), 17 is a serial I / O interface (SI / O), 18 is a data register (D
R). Reference numeral 19 is a signature register, which performs pseudo random number generation and data compression.

Reference numeral 20 is an interrupt controller, 21 is a clock / reset signal generation circuit (CLK / RST), and 22 is a clock prescaler (CPR). Reference numeral 23 is a P bus for inputting an immediate value to a register by an instruction, 24 is each register (reference numerals 3, 4, 8, 15, 16, 17, 18, 19, 32) or built-in data RAM 2 and program counter (PC) The D bus for transmitting and receiving data between 10 and 25 is controlled by the direct memory access controller (DMA) 16 during direct memory access, and transmits and receives data between the serial I / O interface 17 and an external data memory (not shown). It is S bus to do.

Reference numeral 26 is a first interrupt signal (INT1) input terminal, 27 is a second interrupt signal (INT2) input terminal, 28 is a test mode setting signal (TEST) input terminal, and 29 is an IIA mode setting signal (to be described later). IIA) Input terminal, 40 is non-maskable interrupt signal (N
MI) Input terminal. Reference numeral 30 is a 24-bit data input / output terminal, and includes the registers 18, 19, D bus 24,
It is used for data transfer between the S bus 25 and I bus 35 described later and an external data memory (not shown).

Reference numeral 31 is a reset signal (NRESET) input terminal, which is used to input a reset signal (NRESET) for resetting the entire microprocessor. Reference numeral 32 is a flag register (FR) that indicates the operation result of the operation unit (FALU) 7, the logic level of each input terminal or the internal operation mode of this microprocessor. The flag register (FR) 32 is initialized by the reset process when the above-mentioned reset signal (NRESET) is input.

Reference numeral 33 is a clock signal (CLK) input terminal, and the microprocessor of the present invention operates in synchronization with the clock signal (CLK) input from the clock signal input terminal 33. Reference numeral 34 is an address input / output terminal having a 16-bit length, which outputs the address of an external data memory (not shown), and the internal instruction RO in the IIA mode described later.
Addresses of M 11 and built-in shared RAM (CRAM) 12 are specified by external input.

Reference numeral 35 is an I bus used for transferring data between the built-in instruction ROM 11 or the built-in shared RAM (CRAM) 12 and the data register (DR) 18 or the data input / output terminal 30. It has a bit length of bits. Reference numeral 36 indicates UWI (Up) indicating whether the data transferred by the I bus 35 is for the upper 16 bits or the lower 16 bits of the internal instruction ROM 11 or the internal shared RAM (CRAM) 12.
per Word of Instruction) signal output terminal.

The above construction is basically the same as the invention of Japanese Patent Application Laid-Open No. 2-176943 filed by the applicant of the present application as a conventional example.

In the configuration of the first, second, third and fourth inventions of the microprocessor of the present invention, the above-mentioned Japanese Patent Laid-Open No. 2-1769 is used.
In addition to the configuration common to No. 43, a control circuit 37 is provided.

The control circuit 37 includes an instruction decoder 14 and a built-in shared RAM (CRAM) 1 when the WINCR instruction and ENDWC instruction described in the conventional example are executed in the self test mode.
2, program counter (PC) 10 and signature register 19
It is equipped to control. Therefore, the control circuit
The test mode setting signal input terminal 28, the IIA mode setting signal input terminal 29, and the reset signal input terminal 31 are connected to 37. Then, from the control circuit 37, a built-in instruction ROM test signal (ROMTEST) is given to the program counter (PC) 10, built-in shared RAM (CRAM) 12, instruction decoder 14 and signature register 19. It is also connected to the built-in instruction ROM 11 to receive the instruction word output from the built-in instruction ROM 11 via the instruction register (IR) 13, and further to the D bus.
It is also connected to the D bus 24 for sending the instruction word to the signature register 19 via 24.

Further, reference numeral 38 is a comparison circuit, which is connected to the P bus 23 and the signature register 19 and receives a CTRLSIG signal from the control circuit 37. This C
The TRLSIG signal is a signal for comparing the data compressed in the signature register 19 with the data previously written in the HALT instruction and outputting it from the output terminal 39.

In the first, second, third and fourth inventions of the microprocessor according to the present invention, among the above-mentioned respective constituent parts, the structure of each part having the same reference numeral as the above-mentioned conventional one, Operation, instruction format and operation unit (FALU) 7
Since the self-test program and the like are completely the same as those of the conventional example, the description thereof is omitted.

FIG. 2 is a block diagram showing the detailed structure of the control circuit 37 of the microprocessor shown in FIG. 1 and the structure of its peripheral portion.

The control circuit 37 includes an XOR circuit 371, a WINCR decoder 372, an ENDWC decoder 373, a 2-input AND gate 374, 3
75, 381, 3-input OR gate 376, inverter 377, 378, RS
It is composed of a flip-flop 379, a HALT decoder 380, and the like.

The input end of the XOR circuit 371 is the instruction register (IR) 1
3, the output terminals are connected to the D bus 24 respectively, and when the built-in instruction ROM test signal (ROMTEST) is active, the lower 24 bits (b0-b23) of the output signal from the instruction register (IR) 13 Difference (XOR) between the upper 24 bits (b8-b31)
The resulting 24-bit width signal is output to the D bus 24 as source data for bus transfer.

The input terminal of the WINCR decoder 372 is connected to the instruction register (IR) 13 and the output terminal thereof is connected to the AND gate 375. The output signal from the instruction register (IR) 13 is WINCR.
If it is an instruction, the output signal (XWI
NCR) to activate. The ENDWC decoder 373 has an input end connected to the instruction register (IR) 13 and an output end connected to the OR gate 376, and when the output signal from the instruction register (IR) 13 is the ENDWC instruction, it is connected to the OR gate 376. Activate the output signal (XENDWC) of.

The AND gate 374 has a test mode setting signal input terminal 28 and an IIA mode setting signal input terminal for both inputs.
29 are connected to each other, and the bit product of both input signals
AND the self-test mode signal (XSELF)
Outputs to gates 375, 381 and inverter 377. AN
The D gate 375 takes the bit product (AND) of the self test mode signal (XSELF) which is the output signal from the AND gate 374 and the XWINCR signal which is the output signal from the WINCR decoder 372, and sets the terminal S of the RS flip-flop 379. Giving to. The AND gate 381 outputs the self test mode signal (XSELF) output from the AND gate 374 and the HALT decoder 37.
Bit product (AND) with XHALT signal which is output signal from 2
Then, the CTRLSIG signal is given to the comparison circuit 38.

Output signals from both inverters 377 and 378 are applied to the other two inputs of the OR gate 376. The output signal from the inverter 377 is the inverted signal of the self-test mode signal (XSELF) which is the output signal from the AND gate 374, and the output signal from the inverter 378 is the inverted signal of the reset signal NRESET input from the reset signal input terminal 31. It is a signal. The output signal from the OR gate 376 is applied to the reset terminal R of the RS flip-flop 379.

The output signal from the output terminal Q of the RS flip-flop 379 is the built-in instruction ROM test signal (ROMTEST). As described above, the program counter (PC) 10 and built-in shared RA
It is provided to the M (CRAM) 12, the instruction decoder 14, and the signature register 19, and also controls each part of the control circuit 37 such as the XOR circuit 371.

The input terminal of the HALT decoder 380 is an instruction register
When the output terminal of (IR) 13 is connected to AND gate 381, and the output signal of instruction register (IR) 13 is HALT instruction, activate the output signal (XHALT) to AND gate 381. ..

The HALT instruction shown by a mnemonic in FIG. 15 is an instruction located at the end of the self-test program shown in FIGS. 40 to 46 and stopping the execution of the self-test. Normally it just stops the test program. However, as described above, when the self-test mode signal (XSELF) is active, the output signal (CTRLSIG) from the AND gate 381 becomes active, so that the comparison circuit 38 compares the data compressed in the signature register 19 with the instruction Register (IR) 13 to P bus
The lower 24 bits of the HALT instruction transferred to the comparison circuit 38 via 23 are compared, and it is detected whether all the bits match or even one bit does not match, and "1" or "0" is detected.
A 1-bit signal is output from output terminal 39.

The operation of the control circuit 37 as described above is as follows.

When the reset signal (NRESET) input to the reset signal input terminal 31 becomes active, it is inverted by the inverter 378 and given to the reset terminal of the RS flip-flop 379 through the OR gate 376. The internal instruction ROM test signal (ROMTEST), which is the output signal from, is fixed to inactive.

The reset signal (NRESET) becomes inactive, and the test mode setting signal (TEST) and IIA mode setting signal (IIA) given to the test mode setting signal input terminal 28 and the IIA mode setting signal input terminal 29 are changed. When both are active, the self-test mode signal (XSELF), which is the output signal from the AND gate 374, becomes active. At this time, when the instruction word of the WINCR instruction is output from the instruction register (IR) 13, the WINCR decoder 372 decodes it and activates the XWINCR signal to output it to the AND gate 375. As a result, the active XWINCR signal is given to the set terminal S of the RS flip-flop 379 to set the RS flip-flop 379, and the internal instruction ROM test signal (ROMTEST) which is the output signal from the RS flip-flop 379.
Is fixed active. As a result, the mode of the microprocessor becomes the test mode for testing the internal instruction ROM 11.

After that, when the instruction word of the ENDWC instruction is output from the instruction register (IR) 13, the ENDWC decoder 373 decodes it and activates the XENDWC instruction to output it to the OR gate 376. This makes the RS flip-flop 37
Active XENDWC is given to reset terminal R of 9
The RS flip-flop 379 is reset, and the internal instruction ROM test signal (ROMTEST), which is the output signal from the RS flip-flop 379, is fixed to inactive. Also, test mode setting signal (TEST) or IIA mode setting signal (IIA)
Even if any of the above becomes inactive, it is given to the reset terminal R of the RS flip-flop 379 through the AND gate 374, the inverter 377 and the OR gate 376.
The internal instruction ROM test signal (ROMTEST) is fixed to inactive. As a result, the test mode for testing the internal instruction ROM 11 is released.

Next, the internal instruction ROM test signal (ROMTEST)
The control contents when is activated will be described below.

The program counter (PC) 10 is a built-in instruction ROM
When the test signal (ROMTEST) is active, it is incremented by "1" for each machine cycle from the current address, but it does not exceed the address range of the built-in instruction ROM 11 and circulates within that range. In particular,
Program counter (PC) 10 count value is built-in instruction ROM
When the 11th highest address is reached, the next is returned to the lowest address.

The internal shared RAM (CRAM) 12 does not store the output signal from the instruction register (IR) 13 when the internal instruction ROM test signal (ROMTEST) is active. Instruction decoder
When the internal instruction ROM test signal (ROMTEST) is active, 14 does not decode the output signal from the instruction register (IR) 13 and therefore does not execute the instruction.

The signature register 19 uses the D bus 24 when the internal instruction ROM test signal (ROMTEST) is active.
Will be the destination of the bus transfer using. See also X
The OR circuit 371 also performs the above-described operation when the built-in instruction ROM test signal (ROMTEST) is active.

Therefore, the instruction word output from the internal instruction ROM 11 is the instruction register (IR) 13, the XOR circuit 371, and the D bus 24.
It is compressed in the signature register 19 via and is output from the data input / output terminal 30 to the outside of the microprocessor.

FIG. 3 is a schematic diagram showing an example of a program for testing the built-in instruction ROM 11, and FIG. 4 is a flow chart showing its processing procedure.

In FIG. 3, the label "ROM:" is a built-in instruction.
This is the starting address when testing ROM 11. The label "TEST:" is the execution start address of the normal self-test shown in the conventional example. In addition, WINCR in built-in instruction ROM 11
Since the signature is compressed between the instruction and the ENDCR instruction,
When the ENDWC instruction is placed as shown in Figure 3, most of the internal instruction ROM 11, specifically ENDWC, JP
Signature compression is applied to all parts except TEST and WINCR.

In step S1 of the flow chart of FIG. 4, a reset process for starting program execution from an arbitrary address is used to reset and start to the address (ROM :) in the built-in instruction ROM 11 where the WINCR instruction is described.

In step S2, the operation mode of the microprocessor is set to the self-test mode, and the contents of the instruction word in the internal instruction ROM 11 are changed to the signature register 19
The compression test is started.

In step S3, the test for compressing the contents of the instruction word in the internal instruction ROM 11 is continuously executed by the ENDWC instruction until the condition is reached. At this time, the program counter (PC) 10 circulates in the address range of the internal instruction ROM 11 and increments by "1".

At step S4, control is transferred to an entry address (TEST :) other than the built-in instruction ROM 11 used in the conventional example, which executes a self test.

In step S5, the same self test as in the conventional example is executed.

When the HALT instruction is decoded by the HALT decoder 380 when the operation mode of the microprocessor is set to the self-test mode, the comparison circuit 38 is operated as described above.
The CTRL SIG signal given to is activated. In this case, in the lower 24 bits of the HALT instruction, the data to be compared with the data compression result by the signature register 19 is written, and this data is sent to the comparison circuit 38 through the P bus 23. 38 compares the data compressed in the signature register 19 and outputs the comparison result from the output terminal 39.

[Embodiment 2] Next, a second embodiment of the microprocessor of the present invention will be described. In the first embodiment, the fifth and fifth embodiments described in claims 5 and 6 respectively are described. Six inventions are included. The second embodiment of the microprocessor of the present invention will be described below with reference to the block diagram of FIG. Second of the present invention
The configuration of this embodiment is basically the same as the configuration of the first embodiment shown in FIG. 1 described above, but only the portions described below are different. That is, in the second embodiment of the microprocessor of the present invention, the control circuit 37 of the first embodiment described above is used.
A control circuit having a configuration different from that shown in FIG.
41 are equipped. Then, along with this, the control circuit 41
The configuration of the peripheral part is also slightly different. Specifically, it is as follows.

The control circuit 41 is an external data RAM according to an instruction.
When data is read from or written to (not shown) in the self-test mode, the address operation unit (AAU) 1,
It is provided to control the built-in instruction ROM 11 and the data register (DR) 18. Therefore, the control circuit 41 is connected to the test mode setting signal input terminal 28, the IIA mode setting signal input terminal 29, and the reset signal input terminal 31 as in the control circuit 37 provided in the configuration of the first embodiment. Has been done. Then, from the control circuit 41, the built-in instruction ROM test signal (ROMTEST) outputs the address operation unit (AAU) 1, the built-in instruction RO.
It is provided to M 11 and the data register (DR) 18. The control circuit 41 is also connected to the instruction register (IR) 13 in order to receive the instruction word output from the internal instruction ROM 11 via the instruction register (IR) 13.

In the second embodiment of the microprocessor according to the present invention, among the above-mentioned respective constituent parts, the structure of each part having the same reference numeral as the structure of the above-mentioned conventional and first embodiments, Operation, instruction format and operation unit (FAL
The description of the U) 7 self-test program is omitted because it is the same except for the operation in the self-test mode described below.

In the self-test mode of the microprocessor operating modes, the serial input register (SIO, SI1) (not shown) in the serial I / O interface 17 is executed by the execution of an instruction by using the D bus 24. When used as a source register after transfer, a pseudo random number generator (not shown) in the signature register 19 can be used as a source register for bus transfer instead of these. In addition, the serial output registers (SOO, SO1) (not shown) in the serial I / O interface 17 are connected to the D bus.
When used as the destination register after the bus transfer using 24, the data compressor (not shown) in the signature register 19 can be used as the destination register for the bus transfer instead of these.

FIG. 54 is a block diagram showing the detailed structure of the control circuit 41 of the microprocessor shown in FIG. 53 and the structure of its peripheral portion.

The control circuit 41 has a 2-input AND gate 411, 41.
It is composed of a 2- and 2-input OR gate 413, inverters 414 and 415, an RS flip-flop 416, a HALT decoder 417 and the like.

AND gate 411 has a test mode setting signal input terminal 28 and an IIA mode setting signal input terminal for both inputs.
29 are connected to each other, and the bit product of both input signals
AND the self-test mode signal (XSELF)
Gate 412, inverter 414 and RS flip-flop 416
To the set terminal S of. AND gate 412 is the self test mode signal that is the output signal from AND gate 411.
(XSELF) and XHA which is the output signal from HALT decoder 417
The CTRLSIG signal, which is the bit product (AND) with the LT signal, is given to the comparison circuit 38.

Both inverters 41 are connected to both inputs of the OR gate 413.
Output signal from 4,415 is given. Inverter 414
The output signal from is the inverted signal of the self-test mode signal (XSELF) which is the output signal from AND gate 411.
The output signal from the inverter 415 is the reset signal input terminal.
It is an inverted signal of the reset signal NRESET input from 31. The output signal from the OR gate 413 is given to the reset terminal R of the RS flip-flop 416.

The output signal from the output terminal Q of the RS flip-flop 416 is the built-in instruction ROM test signal (ROMTEST), and as described above, the address operation unit (AAU) 1, the program counter (PC) 10, the built-in instruction ROM 11, It is provided to the built-in shared RAM (CRAM) 12 and the data register (DR) 18.

The input terminal of the HALT decoder 417 is the instruction register
If the output terminal of (IR) 13 is connected to AND gate 412 and the output signal from instruction register (IR) 13 is HALT instruction, the output signal to AND gate 412 (XHALT)
To activate.

The HALT instruction shown by the mnemonic in FIG. 15 is an instruction located at the end of the self-test program shown in FIGS. 55 to 62 and stopping the execution of the self-test. Normally it just stops the test program. However, as described above, when the self-test mode signal (XSELF) is active, the output signal (CTRLSIG) from the AND gate 412 becomes active, so that the comparison circuit 38 compares the compressed data in the signature register 19 with the instruction Register (IR) 13 to P bus
The lower 24 bits of the HALT instruction transferred to the comparison circuit 38 via 23 are compared, and it is detected whether all the bits match or even 1 bit does not match, and 1 bit of "1" or "0" is detected. The signal is output from the output terminal 39.

The operation of the control circuit 41 as described above is as follows.

When the reset signal (NRESET) input to the reset signal input terminal 31 becomes active, it is inverted by the inverter 415 and given to the reset terminal of the RS flip-flop 416 through the OR gate 413. The internal instruction ROM test signal (ROMTEST), which is the output signal from, is fixed to inactive.

The reset signal (NRESET) becomes inactive, and the test mode setting signal (TEST) and IIA mode setting signal (IIA) given to the test mode setting signal input terminal 28 and the IIA mode setting signal input terminal 29 are changed. When both are active, the self-test mode signal (XSELF), which is the output signal from the AND gate 411, becomes active. As a result, the RS flip-flop 416 is set, and the internal instruction ROM test signal (ROMTEST), which is the output signal from the RS flip-flop 416, is fixed to active. As a result, in the self-test mode, the microprocessor mode is always the test mode for testing the built-in instruction ROM 11.

After that, when either the test mode setting signal (TEST) or the IIA mode setting signal (IIA) becomes inactive, it resets the RS flip-flop 416 via the AND gate 411, the inverter 414 and the OR gate 413. It is given to the terminal R. As a result, the internal instruction ROM test signal (ROMTEST) is fixed to inactive. As a result,
The test mode for testing the internal instruction ROM 11 and the self-test mode are released.

Next, the internal instruction ROM test signal (ROMTEST)
The control contents when is activated will be described below.

When the internal instruction ROM test signal (ROMTEST) is active, the address operation unit (AAU) 1 executes a read instruction to the data register (DR) 18 from the external data RAM (not shown). If the address value given by the address calculation unit (AAU) 1 is within the address range of the internal instruction ROM 11, the upper 16 bits or the lower 16 bits of the instruction word of the internal instruction ROM 11 corresponding to the address value Read to register (DR) 18.

At this time, the upper 16 bits or the lower 16 bits can be distinguished by the logical level of the output signal from the UWI (Upper Word of Instruction) signal output terminal 36 and the flag register. Since it is reflected in a specific bit of (FR) 32, it can be determined by a program by a sequence instruction in an instruction set described later. Also UWI
The logic values of the specific bits of the signal output terminal 36 and the flag register (FR) 32 are inverted each time the internal instruction ROM 11 is accessed once.

FIG. 67 is a schematic diagram showing an example of a program for testing the internal instruction ROM 11, and FIG. 68 is a flow chart showing its processing procedure.

In FIG. 67, the label "ROM:" is the start address when the built-in instruction ROM 11 is tested. The label "ROM2:" is the page register (P
It is the start address of the subroutine that tests 512 words from the start address specified by GR). The label "TEST" is the execution start address of the normal self-test shown in the conventional example.

In step S11 of the flowchart shown in FIG. 68, a reset process is started from an arbitrary address to reset and start to the address (ROM :) in the built-in instruction ROM 11 where the WINCR instruction is described.

At step S12, the operation mode of the microprocessor is set to the self-test mode, and the contents of the instruction word in the internal instruction ROM 11 are set in the signature register.
The test to compress to 19 is started.

In step S13, the subroutine for compressing the contents of the instruction word of 512 words from the start address specified by the page register (PGR) in the internal instruction ROM 11 is called 8 times, and the internal instruction ROM of 4096 words in total is called.
11 A test is performed that compresses all instruction words.

In step S14, control is transferred to an entry address (TEST :) other than the built-in instruction ROM 11 used in the conventional example, which executes a self test.

In step S15, the same self test as in the conventional example is executed. An example of the self-test program in this case is shown in the schematic diagrams of FIGS. 55 to 62, and its processing procedure is shown in the flowcharts of FIGS. 47 to 51. The difference between the conventional example shown in each of these figures and the second embodiment of the present invention is that the portion designating the data register (DR) 18 in the bus transfer is included in the serial I / O interface 17. The specification is changed to the serial input register (SI0, SI1) or the serial output register (SO0, SO1) not shown, and the operation in the self-test mode is the same, so the description is omitted.

When the HALT instruction is decoded by the HALT decoder 417 when the operation mode of the microprocessor is set to the self-test mode, the comparison circuit 38 is operated as described above.
The CTRL SIG signal given to is activated. In this case, in the lower 24 bits of the HALT instruction, the data to be compared with the data compression result by the signature register 19 is written, and this data is sent to the comparison circuit 38 through the P bus 23. 38 compares the data compressed in the signature register 19 and outputs the comparison result from the output terminal 39.

[0174]

As described in detail above, according to the present invention, the self-test of the built-in instruction ROM of the microprocessor can be executed by the control circuit having a simple structure and the program of several words, and the failure detection rate of the microprocessor can be executed. Is improved and the acceptance test on the user side can be easily performed.
It has an excellent effect.

Further, in the first invention of the microprocessor of the present invention, when the data compressor can be used, the instruction RO
A series of processing using the instructions stored in M is executed,
The contents of each instruction word in the instruction ROM are sequentially read and input to the data compressor for compression. Therefore, the self-test of the built-in instruction ROM of the microprocessor can be easily executed.

In the second invention, the result of comparison between the result compressed by the data compressor and its expected value is output to the outside.
Therefore, the test result is quickly found.

According to the third aspect of the invention, when a predetermined signal is input to the input terminal, the instruction word which constitutes the normal program previously stored in the instruction ROM is once stored in the RAM, and this RAM is stored in the RAM. The stored instructions operate similarly to the first invention. Therefore, it is not necessary to use the capacity of the instruction ROM for the self test.

According to the fourth aspect of the invention, when a predetermined signal is input to the input terminal, the instruction word which constitutes the normal program previously stored in the instruction ROM is temporarily stored in the RAM, and this RAM is stored in the RAM. The stored instructions operate similarly to the second invention. Therefore, it is not necessary to use the capacity of the instruction ROM for the self test.

In the fifth invention, when a predetermined signal is input to the input terminal, normally, the instruction word stored in advance in the instruction ROM for inputting / outputting data to / from the data storage circuit. Is temporarily stored in the RAM, and the instruction stored in the RAM causes the same operation as in the first invention.
Therefore, it is not necessary to use the capacity of the instruction ROM for the self test.

According to the sixth aspect of the invention, when a predetermined signal is input to the input terminal, normally, an instruction word stored in advance in the instruction ROM for inputting / outputting data to / from the data storage circuit. Is temporarily stored in the RAM, and the instruction stored in the RAM operates similarly to the second invention.
Therefore, it is not necessary to use the capacity of the instruction ROM for the self test.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment showing a configuration example of first, second, third and fourth inventions of a microprocessor according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a control circuit of the microprocessor of FIG. 1 and its peripheral configuration.

FIG. 3 is a schematic diagram showing an example of a program for testing a built-in instruction ROM.

4 is a flowchart showing a processing procedure of the program example of FIG.

FIG. 5 is a block diagram showing a configuration example of a conventional microprocessor having a self-test function.

FIG. 6 is a schematic diagram showing field allocation of sequence instruction groups of conventional and present microprocessors.

FIG. 7 is a schematic diagram showing field allocation of sequence instruction groups of conventional and inventive microprocessors.

FIG. 8 is a schematic diagram showing field allocation of a sequence instruction group of a conventional microprocessor and a microprocessor of the present invention.

FIG. 9 is a schematic diagram showing field allocation of sequence instruction groups of conventional and present microprocessors.

FIG. 10 is a schematic diagram showing field allocation of sequence instruction groups of conventional and present microprocessors.

FIG. 11 is a schematic diagram showing field allocation of sequence instruction groups of conventional and present microprocessors.

FIG. 12 is a schematic diagram showing field allocation of sequence instruction groups of a conventional microprocessor and the present invention.

FIG. 13 is a schematic diagram showing field allocation of sequence instruction groups of the conventional microprocessor and the present invention.

FIG. 14 is a schematic diagram showing field allocation of mode instruction groups of a conventional microprocessor and the present invention.

FIG. 15 is a schematic diagram showing field allocation of mode instruction groups of conventional and present microprocessors.

FIG. 16 is a schematic diagram showing field allocation of mode instruction groups of the conventional microprocessor and the present invention.

FIG. 17 is a schematic diagram showing field allocation of mode instruction groups of the conventional microprocessor and the present invention.

FIG. 18 is a schematic diagram showing field allocation of mode instruction groups of the conventional microprocessor and the present invention.

FIG. 19 is a schematic diagram showing field allocation of operation instruction groups of a conventional microprocessor and the present invention.

FIG. 20 is a schematic diagram showing field allocation of operation instruction groups of a conventional microprocessor and the present invention.

FIG. 21 is a schematic diagram showing field allocation of operation instruction groups of a conventional microprocessor and the present invention.

FIG. 22 is a schematic diagram showing field allocation of an operation instruction group of a conventional microprocessor and the present invention.

FIG. 23 is a schematic diagram showing field allocation of operation instruction groups of a conventional microprocessor and the present invention.

FIG. 24 is a schematic diagram showing field allocation of operation instruction groups of a conventional microprocessor and the present invention.

FIG. 25 is a schematic diagram showing field allocation of operation instruction groups of the conventional microprocessor and the present invention.

FIG. 26 is a schematic diagram showing field allocation of operation instruction groups of conventional microprocessors and the present invention.

FIG. 27 is a schematic diagram showing field allocation of operation instruction groups of a conventional microprocessor and the present invention.

FIG. 28 is a schematic diagram showing field allocation of operation instruction groups of conventional microprocessors and the present invention.

FIG. 29 is a schematic diagram showing field allocation of operation instruction groups of a conventional microprocessor and the present invention.

FIG. 30 is a schematic diagram showing field allocation of an operation instruction group of a conventional microprocessor and a microprocessor of the present invention.

FIG. 31 is a schematic diagram showing the allocation of fields of operation instruction groups of the conventional microprocessor and the present invention.

FIG. 32 is a schematic diagram showing field assignment of load instruction groups of conventional and present microprocessors.

FIG. 33 is a schematic diagram showing field allocation of load instruction groups of conventional microprocessors and the present invention.

FIG. 34 is a schematic diagram showing field allocation of load instruction groups of conventional microprocessors and the present invention.

FIG. 35 is a schematic diagram showing field allocation of load instruction groups of conventional microprocessors and the present invention.

FIG. 36 is a schematic diagram showing field allocation of load instruction groups of conventional microprocessors and the present invention.

FIG. 37 is a schematic diagram showing field allocation of load instruction groups of conventional and inventive microprocessors.

FIG. 38 is a schematic diagram showing field allocation of a long load instruction group of a conventional microprocessor and the present invention.

FIG. 39 is a schematic diagram showing field allocation of a long load instruction group of a conventional microprocessor and the present invention.

FIG. 40 is a first of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 41 is a first microprocessor of the related art and the present invention;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 42 is a first microprocessor of the prior art and the present invention;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 43 is a first of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 44 is a first of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 45 is a first of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 46 is a first of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

[FIG. 47] A first conventional and inventive microprocessor
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 48 is a first conventional and conventional microprocessor;
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 49 is a first microprocessor of the prior art and the present invention;
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 50 is a first microprocessor of the prior art and the present invention;
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 51 is a first conventional and inventive microprocessor;
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

52 is a schematic diagram showing how the self-test program shown in FIGS. 40 to 46 is configured in the memory space of the internal instruction ROM shown in FIG. 5. FIG.

FIG. 53 is a block diagram of a second embodiment showing a configuration example of the fifth and sixth inventions of the microprocessor according to the present invention.

54 is a block diagram showing a detailed configuration of a control circuit of the microprocessor of FIG. 53 and its peripheral configuration.

FIG. 55 is a second conventional microprocessor and the present microprocessor.
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 56 shows a second conventional microprocessor and the present microprocessor.
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 57 is a second example of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for an arithmetic unit according to the embodiment of the invention.

FIG. 58 shows a second conventional microprocessor and the second microprocessor of the present invention.
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 59 is a second example of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 60 is a second conventional microprocessor and the present microprocessor.
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 61 is a second of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 62 is a second example of the conventional and inventive microprocessors;
FIG. 6 is a schematic diagram showing an example of a self-test program for a computing unit of the embodiment.

FIG. 63 is a second conventional and conventional microprocessor;
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 64 is a second of the conventional and inventive microprocessors;
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 65 is a second conventional and present microprocessor;
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 66 is a second conventional microprocessor and the present microprocessor.
5 is a flowchart showing a processing procedure of a self-test program of the arithmetic unit of the embodiment.

FIG. 67 is a schematic diagram showing an example of a program for testing the built-in instruction ROM of the second embodiment of the microprocessor of the present invention.

68 is a flowchart showing the processing procedure of the program example of FIG. 67. FIG.

[Explanation of symbols]

 11 Built-in instruction ROM 12 Built-in shared RAM (CRAM) 18 Data register (DR) 19 Signature register 28 TEST Mode setting signal input terminal 31 Reset signal input terminal 37 Control circuit 38 Comparison circuit 41 Control circuit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 16, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 5

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 6

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

The operation of address generation by the address calculation unit (AAU) 1 will be described below. As a register for residual control, the address arithmetic unit (AAU) 1 has an address for the built-in data RAM 2 and a built-in shared RAM (CR
AM) 12 or an address register (A that gives the lower 9 bits of the address to an external data RAM not shown)
R0, AR1, AR2), built-in shared RAM (CRAM) 12 or a page register (PGR) that gives the upper 7 bits of the address to an external data RAM (not shown), a base address value register that gives the base value for generating the address (BA0, BA1,
BA2), increment value register (I0, I1, I2) that gives the added value when generating the address, modulo value or modulo value that gives the bit reverse width-bit reverse width register (ML0, ML1, ML2), at the time of loop instruction Delta base address value register to qualify base address value
(DBA0), Delta increment value register (DI0) for modifying the increment value at loop instruction are included. The value of each of these registers is basically set by the mode instruction described below, but there is also a register that can be changed by an operation instruction.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0091

[Correction method] Change

[Correction content]

Furthermore, a third invention of the microprocessor of the present invention comprises, in addition to the first invention, an instruction RAM for storing a plurality of instructions constituting a program, and the aforementioned signal is inputted to the aforementioned input terminal. If there is no instruction, the contents of one or more instruction words in the instruction ROM are stored in the instruction RAM, and if the aforementioned signal is input to the input terminal ,
Contents of one or more instruction words in the instruction ROM for this instruction
This command is configured to function as the command of the first invention by using the function of reading out.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0092

[Correction method] Change

[Correction content]

Further, a fourth invention of the microprocessor of the present invention comprises, in addition to the second invention, an instruction RAM for storing a plurality of instructions constituting a program, and the above-mentioned signal is inputted to the above-mentioned input terminal. comprising instructions stored in the instruction RAM case to one or more of the contents of the instruction word in the instruction ROM no life of this instruction if the above signal is input
Function to read the contents of one or more instruction words in the instruction ROM
It is characterized in that the instruction is used to function as the instruction of the second invention.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0093

[Correction method] Change

[Correction content]

Furthermore, a fifth invention of the microprocessor of the present invention comprises a data storage circuit in addition to the first invention, and data processed by a program when the aforementioned signal is not input to the aforementioned input terminal. Has an instruction to read one or more data from the data storage circuit or an instruction to write one or more data to the data storage circuit, and these instructions when the above-mentioned signal is input.
Function to read one or more data of, or
These instructions are the first to use the ability to write multiple data .
It is configured so as to function as an instruction of the invention.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0094

[Correction method] Change

[Correction content]

Further, a sixth invention of the microprocessor of the present invention comprises a data storage circuit in addition to the second invention, and stores data to be processed by a program when the above-mentioned signal is not inputted to the above-mentioned input terminal. It has a writing instruction one or more data reading instruction or data storage circuit, one or more data storage to the data storage circuit, the aforementioned
If one of these commands is input,
Is a function to read multiple data, or one or more data.
It is characterized in that these instructions are configured to function as the instructions of the second invention by using the function of writing the data.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0097

[Correction method] Change

[Correction content]

In the third invention, when a predetermined signal is input to the input terminal, one or more instructions in the instruction ROM
An instruction having a function of reading the content of a word operates in the same manner as in the first aspect of the invention.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0098

[Correction method] Change

[Correction content]

In the fourth invention, when a predetermined signal is input to the input terminal, one or a plurality of instructions in the instruction ROM
The instruction having the function of reading the contents of the word operates in the same manner as the second invention.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0099

[Correction method] Change

[Correction content]

In the fifth invention, when a predetermined signal is input to the input terminal, one or a plurality of data are read out.
Function, or the function to write one or more data
The instruction operates to operate similarly to the first invention.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0100

[Correction method] Change

[Correction content]

In the sixth invention, when a predetermined signal is input to the input terminal, one or a plurality of data are read out.
Function, or the function to write one or more data
By the instruction to perform , the same operation as in the second invention is performed.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Name of item to be corrected] 0168

[Correction method] Change

[Correction content]

In step S11 of the flow chart of FIG. 68 , the address (ROM :) in the internal instruction ROM 11 is reset by the reset process which starts the execution of the program from an arbitrary address.
Reset to start.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0177

[Correction method] Change

[Correction content]

In the third invention, when a predetermined signal is input to the input terminal, the above-mentioned signal is the above-mentioned input terminal.
If one or more instructions in the instruction ROM are not input to
Command that stores the contents of the command word in the command RAM
The function of reading the contents of one or more instruction words in the ROM operates in the same manner as in the first invention. Therefore, self-test
Therefore, the number of circuits to be newly added is small.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0178

[Correction method] Change

[Correction content]

In the fourth invention, when a predetermined signal is input to the input terminal, the above-mentioned signal is the above-mentioned input terminal.
If one or more instructions in the instruction ROM are not input to
Command that stores the contents of the command word in the command RAM
The function of reading the contents of one or more instruction words in the ROM operates similarly to the second invention. Therefore, self-test
Therefore, the number of circuits to be newly added is small.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0179

[Correction method] Change

[Correction content]

In the fifth invention, when the predetermined signal is inputted to the input terminal, the above-mentioned signal becomes the above-mentioned input terminal.
Data to be processed by the program if it is not entered in
Read one or more data in a data storage circuit that stores
The instruction to issue or one or more data in the data storage circuit.
Read one or more data that the instruction to write the data has
The function or the function of writing one or more data operates in the same manner as in the first aspect of the invention. Therefore, the self-test
Therefore, the number of newly added circuits can be reduced.

[Procedure 16]

[Document name to be amended] Statement

[Correction target item name] 0180

[Correction method] Change

[Correction content]

In the sixth invention, when a predetermined signal is input to the input terminal, the above-mentioned signal is the above-mentioned input terminal.
Data to be processed by the program if it is not entered in
Read one or more data in a data storage circuit that stores
The instruction to issue or one or more data in the data storage circuit.
Read one or more data that the instruction to write the data has
With the function or the function of writing one or more data , the same operation as in the second invention is performed. Therefore, the self-test
Therefore, the number of newly added circuits can be reduced.

[Procedure Amendment 17]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 15

[Correction method] Change

[Correction content]

FIG. 15

[Procedure 18]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 25

[Correction method] Change

[Correction content]

FIG. 25

[Procedure Amendment 19]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 45

[Correction method] Change

[Correction content]

FIG. 45

[Procedure amendment 20]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 60

[Correction method] Change

[Correction content]

FIG. 60

Claims (6)

[Claims] 1. An instruction ROM that stores a plurality of instructions that form a program, a data compressor that compresses and outputs input data, and a signal that enables the use of the data compressor. An input terminal for performing inputting, and when the signal is input to the input terminal, an instruction to input and compress the contents of one or more instruction words in the instruction ROM to the data compressor A microprocessor stored in an instruction ROM, comprising means for executing a series of processing for inputting and compressing the contents of an instruction word in the instruction ROM into the data compressor using the instruction. Characteristic microprocessor. 2. An instruction ROM in which a plurality of instructions forming a program are stored, a data compressor for compressing and outputting input data, and a signal enabling the use of the data compressor. An input terminal for storing the expected value of the output of the data compressor, a comparison means for comparing the expected value stored in the storage means with the output of the data compressor, and outputting the result. Means for storing, in the instruction ROM, an instruction for inputting and compressing the contents of one or more instruction words in the instruction ROM to the data compressor when the signal is input to the input terminal. The microprocessor is configured to input the contents of the instruction word in the instruction ROM to the data compressor for compression by using the instruction, and output the comparison result by the comparison means with the expected value. Microprocessor, characterized in that it comprises means for executing a process of communicating. 3. An instruction ROM storing a plurality of instructions forming a program, and an instruction RAM storing a plurality of instructions forming a program.
A data compressor that compresses and outputs input data, and an input terminal for inputting a signal that enables the use of the data compressor, the signal being input to the input terminal. , The contents of one or more instruction words in the instruction ROM are input to the data compressor to be compressed, and if the signal is not input to the input terminal, Or, a microprocessor in which an instruction for storing the contents of a plurality of instruction words in the instruction RAM is stored in the instruction ROM, wherein when the signal is input to the input terminal, A microprocessor comprising means for executing a series of processes for inputting and compressing the contents of an instruction word in an instruction ROM into the data compressor. 4. An instruction ROM in which a plurality of instructions forming a program are stored, and an instruction RAM in which a plurality of instructions forming a program are stored.
A data compressor that compresses and outputs input data; an input terminal for inputting a signal that enables the data compressor to be used; and an expected value of the output of the data compressor. And a comparison means for comparing the expected value stored in the storage means with the output of the data compressor and outputting the result, when the signal is input to the input terminal. , The content of one or more instruction words in the instruction ROM is input to the data compressor for compression, and when the signal is not input to the input terminal, one or more instructions in the instruction ROM A microprocessor in which an instruction for storing the content of a word in the instruction RAM is stored in the instruction ROM, wherein when the signal is input to the input terminal, the instruction is used to store in the instruction ROM. Instruction The contents of the de is compressed is input to the data compressor, a microprocessor, characterized in that it comprises means for executing the series of processes to output the comparison result by the comparison means and its expected value. 5. An instruction ROM in which a plurality of instructions constituting a program are stored, a data storage circuit for storing data processed by the program, a data compressor for compressing and outputting input data, An input terminal for inputting a signal that enables the use of the data compressor, wherein when the signal is input to the input terminal, one or more instruction words in the instruction ROM When the content is input to the data compressor for compression and the signal is not input to the input terminal, 1 in the data storage circuit is input.
Alternatively, a plurality of instructions may be read, or 1 may be stored in the data storage circuit.
Alternatively, a microprocessor storing an instruction for writing a plurality of instructions in the instruction ROM, wherein when the signal is input to the input terminal, the instruction is used to write an instruction word in the instruction ROM. A microprocessor comprising means for executing a series of processing for inputting and compressing contents into the data compressor. 6. An instruction ROM in which a plurality of instructions forming a program are stored, a data storage circuit for storing data processed by the program, a data compressor for compressing and outputting input data, An input terminal for inputting a signal that enables the use of the data compressor, storage means for storing an expected value of the output of the data compressor, and the expected value and the data stored in the storage means. A comparator for comparing the output of the compressor and outputting the result, and when the signal is input to the input terminal, the contents of one or more instruction words in the instruction ROM are stored in the data. When the signal is input to the compressor for compression and the signal is not input to the input terminal, 1 in the data storage circuit is input.
Alternatively, a plurality of instructions may be read, or 1 may be stored in the data storage circuit.
Alternatively, a microprocessor storing an instruction for writing a plurality of instructions in the instruction ROM, wherein when the signal is input to the input terminal, the instruction is used to write an instruction word in the instruction ROM. A microprocessor comprising means for executing a series of processes for inputting contents into the data compressor for compression and outputting a result of comparison with the expected value by the comparing means.