JPH0540538A - Clock driver - Google Patents

Abstract

PURPOSE:To adjust the duty of the clock output signal of a clock driver from the outside. CONSTITUTION:The clock driver is constituted of an ECL circuit, and the multi- stage configuration is adopted in order to distribute many clock output signals. Usually, the reference potential of the switching transistor of the ECL circuit is supplied at a fixed level, but the reference potential of only the clock drivers 111, 121 of the final stage can be adjusted from the outside. This reference potential level is supplied from a circuit 130 capable of adjusting it up and down around the center of the middle potential of the amplitude of the clock output signal from the outside. Thus, when the time ratio (duty) of the high level and the low level of the clock output signal is out of 50%, it can be brought close to 50% by adjusting it from the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock driver, and more particularly, to an ECL (emitter coupled logic) circuit,
The present invention relates to a clock driver capable of adjusting a duty of a clock output.

[0002]

2. Description of the Related Art In general, a semiconductor integrated circuit is provided with a flip-flop circuit of a plurality of bits, and a clock signal of a constant cycle is supplied to operate these flip-flops. In order to operate the semiconductor integrated circuit in a stable manner, the cycle of the clock signal is kept constant, and in order to operate the flip-flop particularly in a high speed cycle, the high (High) level and the low (L) level of the clock signal are required.
ow) level time ratio (duty) as much as 50
It is necessary to approach%.

Usually, the supply of the clock signal is performed by distributing the signal output from the oscillator from a clock driver having a plurality of stages to a large number of integrated circuits.

Therefore, even if the duty of the signal output from the oscillator is 50%, the duty of the clock signal output from the clock driver at the final stage may deviate from 50% due to the influence of the waveform distortion of the clock driver. is there.

[0005]

As described above, the clock signal output from the conventional clock driver may deviate from the duty of 50%. Especially, the ratio increases as the number of stages of the clock driver increases. There was a drawback.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a clock driver capable of stably obtaining a clock signal with a duty of 50%.

[0007]

The structure of the present invention is based on ECL.
In a clock driver consisting of a multi-stage circuit,
It is characterized in that it is provided with a circuit capable of adjusting the reference potential of the switching section transistor of the ECL circuit constituting the final stage clock driver from the outside centering on the intermediate potential of the amplitude of the clock output signal.

[0008]

1 is a block diagram showing a clock driver according to an embodiment of the present invention.

Referring to FIG. 1, the clock driver of this embodiment has a plurality of clock drivers (NAND gates) to which an oscillation circuit section 100 for generating a highly accurate oscillation output 101 such as a crystal oscillator and the oscillation output 101 are input. 111
The clock distribution circuit section 110 of the first stage for outputting a plurality of clock distribution signals 112 and the clock distribution signal 112 of the preceding stage, and a plurality of clock drivers (A
ND gate) 121 allows a plurality of clock signals 122
The final stage clock distribution circuit section 120 for outputting
And a duty adjusting circuit 130 for generating the clock signal and supplying it to the final stage clock distribution circuit section 120.

FIG. 2 is a circuit diagram in which only the final stage clock distribution circuit section 120 and the adjusting circuit 130 are extracted from FIG.

In FIG. 2, the clock driver 121
Is a typical ECL including a switching unit including resistors R1 and R2 and transistors Q1 and Q2, and a constant current circuit unit including a transistor Q3 and resistor R3.
Circuit.

On the other hand, the duty adjusting circuit 130 is composed of resistors R4 to R6 and transistors Q4 and Q5. Among the circuit elements used in the clock driver 121 and the duty adjusting circuit 130, the transistors Q1 / Q2 / Q4, Q3 / Q5, and the resistors R1 / R are included.
2 / R4 / R5 and R3 / R6 are the same transistor and resistor.

The operation of the circuit shown in FIG. 2 will be described below.

When a constant potential of VCS is applied to the base of the transistor Q3 in the constant current circuit section of the clock driver 121, a constant current I0 flows through the resistor R3, as in a normal ECL circuit. The constant current I0 flows through one of the paths of the resistor R1 → transistor Q1 or the resistor R2 → transistor Q2, and which one is flowing is determined by the potential relationship between the clock distribution signal 112 and the duty adjustment output signal 132.

That is, when the clock distribution signal 112 is at a higher potential than the duty adjustment output signal 132,
Since the transistor Q1 is turned on and the transistor Q2 is turned off, all the current flows through the path of the resistor R1 → transistor Q1.

On the other hand, if the duty adjustment input signal 131 of the duty adjustment circuit 130 is set to the same potential as VCS, the resistor R6 has the same circuit constant as the resistor R3.
→ Transistor Q4 → Transistor Q5 → Flows through the resistor R6.

Further, since the same resistor as the resistors R1 and R2 is connected in parallel to the collector of the transistor Q4, the potential of the duty adjustment output signal 132 is the clock signal 12.
2 becomes an intermediate potential between the high level and the low level.

If the clock signal 122 and the clock distribution signal 112 have the same High and Low levels, the duty adjustment output signal 132 also becomes an intermediate potential of the clock distribution signal.

Therefore, the clock distribution signal 112 becomes High.
At the h level, the transistor Q1 turns on and the current I
0 flows through the path of the resistor R1 → transistor Q1, and the clock signal 122 becomes High level (GND level). On the contrary, when the clock distribution signal 112 is at the low level, the transistor Q2 is turned on, so that the level becomes the low level (-R1 · I0).

FIG. 3 is a characteristic diagram for explaining the duty adjusting operation of the clock signal 122 based on the waveforms of the respective parts of FIG.

In FIG. 3, the waveform of the clock distribution signal 112 is shown in the upper part, and the low level and the high level are shown.
The time ratio of the h level is TL <TH, which is outside the duty of 50%. In the middle and lower parts, the waveform of the clock signal 122 is shown, and the waveforms of two cases (case 1 and case 2) corresponding to the potential level of the duty adjustment output signal 132 are shown.

In case 1, the duty adjustment output signal 13
2 shows the case where 2 is set to the intermediate level of the clock distribution signal 112. When the circuit delay time of the clock driver 121 is Tpd, a waveform delayed from the clock distribution signal 112 by Tpd is output as the clock signal 122. Therefore, TL (1) = TL, TH
(1) = TH and the duty remains off 50%.

In case 2, the duty adjustment output signal 13
2 shows a case where 2 is shifted to the High side as compared with Case 1. As a result, the transistor Q
2 becomes High → Low faster, and L
The time from ow to High becomes late. Therefore, the low-level time of the clock signal 122, which is the collector output of the transistor Q2, is longer than in the case 1, and conversely H
The time of the high level becomes short. At this time, depending on the set level of the duty adjustment output signal 132, the duty of the clock signal 122 can be brought close to 50%.
It can be set that L (2) = TH (2).

The level of the duty adjustment output signal 132 is set by the duty adjustment input signal.
The case 1 corresponds to the case where the duty adjustment input signal is set to the VCS level, and the case 2 corresponds to the case where the potential level is set lower than the VCS.

Contrary to FIG. 3, when TL> TH,
If the duty adjustment input signal 131 is set to a level higher than VCS, it is possible to bring the duty close to 50%.

[0026]

As described above, the present invention has the effect that the duty of the clock signal can be adjusted from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock driver according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a clock distribution circuit unit and a duty adjustment circuit at a final stage of FIG.

FIG. 3 is a signal waveform diagram of each part for explaining the operation of FIG.

[Explanation of symbols]

 100 oscillation circuit unit 101 oscillation output 110 first stage clock distribution circuit unit 111, 121 clock driver 112 clock distribution signal 120 final stage clock distribution circuit unit 122 clock signal 130 duty adjustment circuit 131 duty adjustment input signal 132 duty adjustment output Signal R1, R2, R3, R4, R5, R6 Resistance Q1, Q2, Q3, Q4, Q5 Transistor

Claims (1)

[Claims] 1. A multi-stage clock driver composed of an ECL circuit, wherein a reference potential of a switching section transistor of an ECL circuit which constitutes a final stage clock driver of the multi-stage is set to an intermediate potential of an output amplitude of the clock driver. A clock driver characterized by adding a vertically adjustable circuit centering around.