JPH0537935A - Subscription broadcasting decoder - Google Patents

Abstract

PURPOSE:To obtain an inexpensive and high quality television(TV) subscription broadcasting decoder capable of using a MUSE signal obtained after descrambling subscription broadcasting as a normal non-scrambled MUSE signal. CONSTITUTION:This subscription broadcasting decoder has a sound/image descrambling unit 6, a scramble flag erasing/master frame discriminating flag bit shifting device 143, a MUSE sound re-encoding device and a multiplexing device 50 for encoding processing sound data with a video signal. In such constitution, a scrambled sound data bit stream is descrambled, a scramble flag is erased, a master frame discriminating flag bit is shifted to another sound frame, MUSE signal sound re-encoding processing is executed, and during the vertical blanking of a MUSE signal including a descrambled video signal, remultiplexing is executed, so that a MUSE signal obtained after descrambling subscription broadcasting can be used equivalently to a normal non-scrambled MUSE signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a high-definition television (MUSE system = Multiple Sub-Nyqu).
The present invention relates to a pay broadcasting decoder that enables scrambling only for contracted subscribers to watch a program in pay broadcasting in the broadcasting of istampling encoding (multiple sampling coding).

[0002]

2. Description of the Related Art In recent years, pay broadcasting has been put into practical use with the expansion of broadcasting satellites. In the pay broadcasting, unlike the conventional broadcasting format based on the advertisement fee and the receiving fee, it is necessary to deliver the program only to the contracted recipients, and therefore the program is normally electrically disturbed (scrambled) and broadcast. Therefore, to view a pay broadcast program, a pay broadcast decoder for descrambling and normally viewing the program is required.

Conventionally, multiple sampling coding (hereinafter referred to as M
As a pay broadcast decoder for a signal (referred to as USE), a method of incorporating it into a MUSE decoder as a pay broadcast unit is considered. On the other hand, for existing MUSE decoders, MUSE after descrambling pay broadcasts
A stand-alone MUSE pay-broadcast decoder has been considered in which the signal can be treated in the same way as a normal non-scrambled MUSE signal.

An example of the above-mentioned conventional stand-alone MUSE pay broadcast decoder will be described below with reference to the drawings. FIG. 6 shows an example of the configuration of a conventional MUSE pay broadcast decoder. In FIG. 6, reference numeral 2 denotes an analog MUSE signal input terminal to which a scrambled MUSE signal is normally input. An A / D converter 3 converts an analog MUSE signal into a digital MUSE signal. Reference numeral 4 is a clock / synchronization reproducing unit, which is a digital signal processing reference clock 16.2 MHz from the digital MUSE signal.
(Hereinafter referred to as VCK), a video horizontal synchronization signal (hereinafter referred to as HD) and a video frame synchronization signal (hereinafter referred to as VFRAM) required in each part of the stand-alone MUSE pay-broadcast decoder and reproduced in each part in the stand-alone MUSE pay-broadcast decoder Supply. An audio processing unit 5 reproduces an audio data bit stream (hereinafter referred to as DBS) after 16-bit deinterleaving at a rate of 1.35 MHz from a digital MUSE signal, and an audio frame synchronization signal (hereinafter referred to as FSY) and audio data. Reference clock 1.35M
Hz (hereinafter referred to as ACK) is supplied to the descramble unit. 6 is a descrambling unit, DBS1
3 to descramble the scrambled digital MUSE signal 19 based on this to output the descrambled MUSE signal 12 and to add the sum to descramble the scrambled audio data bitstream 13. To generate a pseudo random signal (hereinafter referred to as PN). Reference numeral 7 is an exclusive OR element, which outputs the descrambled DBS 15 by taking the exclusive OR of the DBS 13 and the PN signal 11 for descrambling. Four
Reference numeral 3 denotes a scramble related information bit erasing unit, which is a DBS15.
Erasing the information bits relating to the scrambling multiplexed inside. Reference numeral 41 is a bit interleaving unit that re-interleaves the 16-bit deinterleaving in the voice processing unit 5. 42 is a BCH (82, 74) error correction code addition device, which excludes the descrambled DBS 15 synchronization signal and control code bit, and corrects 8-bit error for 74 bits of information bits in each row of the bit interleave matrix. Add bits. Reference numeral 44 performs interleaving between 25 voice frames on the basis of the vertical blanking period in the MUSE signal multiplexed by the 25 voice frame interleaving unit. A time axis compression unit 45 converts voice data at a rate of 1.35 MHz into burst data for multiplexing in the vertical period of the MUSE signal. 46 is 2/3
The value conversion unit converts continuous binary 3 data into continuous 3 binary samples. Reference numeral 47 is a conversion filter, which performs frequency conversion to match the time-axis-compressed, binary / ternary-converted 12.15 MBaud audio data with a video signal sample rate of 16.2 M rate. Reference numeral 48 denotes an encoded audio signal delay circuit, which delay-adjusts the encoded audio signal to the timing of the vertical blanking period audio multiplex region of the video signal output from the descramble unit 6. An audio multiplex timing control unit 49 outputs a signal indicating an audio multiplex area of the vertical blanking period of the output MUSE signal from the descramble unit 6. Reference numeral 50 denotes a signal change-over switch, which switches between the output from the descramble unit 6 and the output of the audio data time base compression unit 47 according to the output signal of the audio multiplex timing control unit 49. 51 is a D / A converter, which is a digital M
Convert the USE signal to an analog MUSE signal. 52 is a MUSE signal output terminal for a MUSE decoder or MUSE
Connected to VTR.

The operation of the conventional MUSE pay broadcast decoder configured as described above will be described below (FIG. 6). The description will be given taking as an example the case where a scrambled MUSE signal is input for both video and audio. The input MUSE signal is digitally converted by the A / D converter 3, and is supplied to the descramble unit 6, the audio processing unit 5, the clock, and the synchronous reproduction unit 4. The descrambling process is performed as follows. First, the descramble unit 6 extracts and decodes the scramble-related information in the DBS 13 from the voice processing unit 5. The position of scramble-related information is shown in (FIG. 4). (FIG. 4) shows the bit allocation and the multiplexing position of scramble-related information when A-mode signals are multiplexed, and D.
It is a voice frame block diagram which shows the bit allocation of BS13 state. The scramble-related information bits are multiplexed in the control code, range bits, and the independent data area, as indicated by the diagonal lines in FIG.

Further, these multiplexed scramble-related information bits exist in a diagonal multiplex state in which they are present at a fixed position in a voice frame for each voice mode from the multiplexing position and in an independent data area whose area is changed for each voice mode. It is classified as something that does. The scramble-related information bits existing in the control code area and range bits exist in a fixed position for each voice mode. The respective bits and positions are shown below. Video scramble flag bit: control code 12th bit, scramble timing bit: control code 13th bit, audio scramble flag bit
.. r # is the 8-bit position. On the other hand, FIG. 5 shows how the scramble-related information is diagonally multiplexed in the independent data area whose area changes for each voice mode. (Fig. 5) shows 28 between 18 audio frames in A1 mode.
It is a diagonal multiplexing system figure which shows a mode of multiplexing of the scramble related information bit of 8 bits. As shown in (FIG. 5), the scramble-related information is diagonally multiplexed one bit for each row in the speech frame, and 18 speech frames, that is, 288 bits as one unit (hereinafter, these 18 speech frames are defined as superframes). I am trying.

The descramble unit 6 extracts and decodes these scramble-related information bits from the DBS 13, and the scramble digital MUS for the video signal.
The E signal 19 is descrambled and the digital descramble video signal 12 is output. For the audio signal, PN so that it can be descrambled by the exclusive OR element 7 in the subsequent stage.
Generate signal 11. In the voice processing unit 5, the digital MU
The audio data in the blanking period is extracted from the SE signal, and for descrambling, the audio signal format is returned to the scrambled position on the broadcasting station side, that is, to the state where PN addition is performed on the audio signal. Since the audio signal is scrambled immediately before bit interleaving, the receiving side returns the audio signal format to the audio frame format in this state, and the same PN signal 11 as that added to the DBS 13 at the time of scrambling is subjected to exclusive logic. The addition is performed by the summing element 7 to descramble the audio signal.

Next, the descrambled DBS 15 is input to the scramble related information bit erasing section 43.
The scramble-related information bit erasing unit 43 erases all scramble-related information in the descrambled data bit stream. This is because when the scramble-related information remains in the descrambled MUSE signal, the MUSE decoder in the subsequent stage scrambles the MUSE signal even though the MUSE signal is descrambled.
This is because the program cannot be viewed normally because it is recognized as a signal.

FIG. 7 shows an example of the circuit configuration of the scramble-related information bit erasing section. In FIG. 7, 15
Is a voice DBS to which the output of the exclusive OR element 7 is input. 62 is a voice frame synchronization signal (FSY), 63
Is the audio reference clock 1.35 MHz (ACK).
A voice bit counter 60 is reset for each voice frame and counts 0 to 1349 by ACK 63. A bit gate 69 indicates the timing of the related information bits among the scramble related information bits, such as the control code bit and the R # 8 bit, which exist at a fixed position in the audio frame depending on the audio mode. A data flip-flop 64 detects a control code first bit (hereinafter, control code first bit to 22nd bit is referred to as b # 1 to b # 22) indicating a voice A / B mode.

Reference numeral 68 denotes an oblique multiplex timing generation circuit, which detects a voice mode for obtaining an oblique multiplex position in the audio frame of the scramble-related information and outputs a pulse indicating the head timing of each line of the audio frame. 90 is DBS1
5, b # 1 detection pulse, 91 is a timing pulse for detecting b # 1 to b # 6 indicating a voice mode,
92 is a timing pulse for detecting 2 superframes, that is, b # 14 indicating the timing of the audio master frame transmitted every 36 audio frames, 93
Is a pulse signal indicating the beginning of each line in the audio frame.

Reference numeral 70 denotes a data flip-flop, which outputs 1 / b of timing pulses 91 of b # 1 to b # 6 indicating a voice mode.
Delay 2 clocks. Reference numeral 71 denotes a logical product device, which is a burst timing clock for detecting b # 1 to b # 6 indicating the audio mode of the data bit stream 15 by gating the audio reference clock ACK with the output of the data flip-flop 70. Generate. 72
Is a data flip-flop, and b of the data bit stream is generated by the burst clock from the AND device 71.
# 1 to b # 6 are detected. 73 is a shift register, 74
Is a data flip-flop, which outputs the output of the data flip-flop 72, that is, b # 1 to b # 6 in parallel. 75 is a data flip-flop, D
B # indicating audio master frame timing in BS15
No. 14 is detected, which is detected by the b # 14 detection timing pulse 92 output for each audio frame. Reference numeral 76 is a data flip-flop, and 78 is a logical product element. This combination differentiates the b # 14 detection signal output from the data flip-flop 75 into one clock width. 7
Reference numeral 9 is an audio frame row counter, which is a 288-ary counter which is reset every master frame, that is, every 36 audio frames.
87 is output as a count. A delay adjusting circuit 94 adjusts the timing so that the output of the logical product element 78 appropriately resets the audio frame row counter 79 which uses the line pulse 93 as a counter clock.

Reference numeral 80 is a bit position counter within a voice frame row, which is reset at every line pulse 93 to 0 to 81.
Is output as a count. Reference numeral 81 denotes a ROM which outputs the diagonal multiple bit position in each row of the scramble-related information bits from the output value of each audio mode of the data flip-flop 74 and the output value of the audio frame in-line counter 79. A comparator 82 generates a pulse when the output of the bit position counter 80 and the output of the ROM 81 are equal. A data bit stream delay adjustment circuit 96 adjusts the timing with the output of the bit gate 69 and the output of the comparator 82. Reference numeral 95 is a delay adjustment circuit for adjusting the timing of the output of the bit gate 69 and the data bit stream. Reference numeral 65 denotes a logical product element, which erases the output of the timing adjustment delay circuit 95 by forcibly setting the scramble-related information bit at a fixed position in the audio data bit stream to LOW.
Reference numeral 67 denotes a logical product element, which erases the diagonally multiplexed bits of the scramble-related information bits in the audio data bit stream by forcing LOW by the output of the comparator 82.

Hereinafter, the scramble related information bit erasing unit 4
The operation of No. 3 will be described with reference to (FIG. 7) and (FIG. 8). FIG. 8 is a signal waveform diagram showing a signal waveform of each part of the scramble-related information erasing part shown in (FIG. 7). (FIG. 8) Numbers 1 to 1350 shown in the waveform of DBS15 in FIG.
Indicates the transmission order of each bit in the audio frame in the DBS state. The FSY 62 is a voice frame synchronization signal indicating the start bit timing of the voice frame as shown in the figure.

First, at a fixed position for each voice mode,
Video scramble flag bit ... Control code 12th bit, scramble timing bit ... Control code 13th bit, audio scramble flag bit ... r #
The erase operation of the scramble-related information bit at the 8-bit position will be described. The b # 1 90 outputs a pulse at the timing of detecting the b # 1 as shown in (FIG. 8), and the detected b # 1 signal of the DBS 15, that is, the A / B of the voice.
The mode is connected to the bit gate 69 as in (FIG. 7). As a result, the bit gate 69 is located at a fixed position for each audio mode. The video scramble flag bit ... Control code 12th bit, scramble timing bit ... Control code 13th bit, audio scramble flag bit ... A pulse signal indicating the r # 8 bit position is output. The output of the delay adjustment circuit 95 shown in FIG. 8 is obtained by delay-adjusting this pulse signal, and this is used as a gate signal at the timing shown in FIG.
By forcibly setting the corresponding bit of 96 to LOW, the scramble-related information bit at a fixed position is erased for each voice mode. Next, the erasing operation of the scramble-related information bits diagonally multiplexed in the independent data area, which area changes depending on the audio mode, will be described with reference to FIGS. 7 and 8 in the same manner. The diagonally multiplexed scramble-related information bits are superframes (18
Audio frame) is configured as one unit. This one
The unit of 8 voice frames is detected on the receiving side with reference to the master frame head frame identification bit b # 14 transmitted every 36 voice frames. The output signal of the data flip-flop 75 shown in FIG. 8 is supplied to DBS1 by the b # 14 timing output 92 of the diagonal multiplexing timing generation circuit 68.
The result of detecting b # 14 in the 5 signals is shown.

In the example of FIG. 8, b # of this voice frame
14 indicates that the voice frame 14 is active, that is, the head voice frame of the master frame. This signal is connected to the data flip-flop 76, the logical product element 78, and the delay element 94 as shown in (FIG. 7) and differentiated so that the line counter 79 is reset at the timing of the line pulse 93 shown in (FIG. 8). , Delay adjusted. The output of the line counter 79 thus reset is as shown in (FIG. 8) for one super frame (18 audio frames).
The line pulse 93 is counted up from 0 to 287.

The in-line bit counter 80 is reset by the line pulse 93 as shown in FIG. 8 and outputs the bit positions 0 to 81 in the row of each audio frame.

On the other hand, the output of the data flip-flop 74 outputs b # 1 to b # 6 indicating various modes of voice to the ROM 81 at every timing of b # 14 as shown in FIG. The ROM 81 obtains an independent data area in the audio frame from the audio modes indicated by b # 1 to b # 6, and outputs the scramble-related information at the time of the corresponding diagonal multiplexing in the independent data area by the output of the line counter 79. The bit multiplex position is output for each row as shown in the output of the ROM 81 (FIG. 8). The comparator 82 is the ROM 81
Is compared with the output of the in-line counter 80, and when they match, a pulse signal is generated as shown in the output of the comparator 82 (FIG. 8).

The output signal of the comparator 82 is used as a gate signal, and the AND element 67 forces the diagonally multiplexed bits of the data bit stream to LOW, thereby erasing the diagonally multiplexed scramble-related information bits. As described above, all the scramble-related information bits in the DBS are erased and input to the bit interleaving unit 41 (FIG. 6).

The processing of the subsequent stage will be described below with reference to FIG. Bit interleave section 41,
BCH (82,74) processing device 42, 25 frame interleaving device 44, 2/3 value conversion device 46, 12.1
The 5 → 16.2 MHz conversion filter unit 47 is a MUSE audio encoding processing unit that re-encodes the MUSE audio processing decoded by the audio processing unit 5, but this is the same as the corresponding part of the normal MUSE audio encoding processing unit. Therefore, the description is omitted here.

The encoded audio signal delay circuit 48 delay-adjusts the encoded audio signal and adjusts it to the vertical blanking period of the video signal.

Next, the changeover switch 50 switches the output signal from the output of the audio / video delay circuit 48 to the audio signal side in the audio multiplex period according to the output signal of the audio timing control section 49.

As described above, after descrambling the audio signal portion of the scrambled MUSE signal, the multiplexed scramble-related information bits are erased, and after the re-MUSE audio encoding process, the video signal portion is descrambled. By re-multiplexing with, it is possible to output a descrambled signal in the regular MUSE signal format.

[0023]

However, the stand-alone MUSE pay-broadcast decoder having the above-described structure includes scramble-related information bits that are diagonally multiplexed in the independent data area in the audio data bit stream whose position is different depending on the audio mode. Since all of the scramble-related information bits are erased, there is a problem that the circuit scale of the scramble-related bit erasing section increases.

In order to solve the above problems, the present invention realizes a stand-alone MUSE pay broadcast decoder having a simple structure.

[0025]

In order to achieve the above object, a stand-alone MUSE pay broadcast decoder according to the present invention comprises a scrambled digital multiple sampling coded signal, 25 frame deinterleave and BCH (82,7).
4) A digital multiple sampling code in which the audio data bit stream after error correction is input, and the descrambling process is performed on the video signal part of the scrambled digital multiple sampling coded signal and the pseudo random signal for descramble of the audio data bit stream. A descramble unit device that outputs a scrambled signal, and an exclusive OR device that adds the pseudo-random signal output from the descramble unit device and the scrambled audio data bit stream and descrambles the audio data bit stream. , The descramble audio data bit stream is input, the multiplexed video scramble flag bit and audio scramble flag bit are erased, and the audio master frame identification flag bit is set to a regular audio frame. Scrambling flag erasing / audio master frame identification flag bit shift device for erasing from the audio data and adding to another audio frame, and multiple sampling encoding of the audio data bit stream output from the scrambling bit erasing / audio master frame identification flag bit shifting device. Bit interleave device for re-multiplexing into signal, BCH (82,74) error correction addition device, 25
Frame interleaver, time axis compressor, binary /
A voice re-multiplex encoder for a multi-sampling coded signal and a voice re-multiplex encoder for the multi-sampling coded signal, which comprises a ternary conversion device and a 12.15 MHz / 16.2 MHz resampling waveform shaping filter device. A delay device that delays the audio signal
A signal switching device that multiplexes the voice signal re-encoded into the descrambled multi-sampling coded signal into the voice independent data area of the output of the descramble unit device, and a timing control device that controls the signal switching device. Is adopted and combined.

[0026]

According to the present invention, the scrambled voice data bit stream is descrambled by the PN signal output from the descramble unit, the scramble flag is erased, the master frame identification bit flag position is shifted, and the 16-bit interleave, B
CH (82,74) error correction code addition, 25 frame interleaving, time axis compression, binary / ternary conversion, 12.15
After descrambling MUSE pay broadcasting by performing MUSE audio encoding processing of audio data rate conversion from MHz to 16.2 Mhz and re-multiplexing during vertical blanking of MUSE signal including descrambled video signal It is possible to provide a stand-alone MUSE pay-broadcast decoder having the same effect that the MUSE signal of No. 1 can be treated in the same manner as a normal non-scrambled MUSE signal, and the scramble-related information bits are all erased with a simple configuration. ..

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a MUSE pay broadcast decoder according to an embodiment of the present invention.

In FIG. 1, 2 is an analog MUSE.
The signal input terminal normally receives the scrambled MUSE signal. 3 is an A / D converter, an analog MUS
The E signal is converted into a digital MUSE signal. Reference numeral 4 denotes a clock / synchronization reproducing unit which converts a digital MUSE signal from a digital signal processing reference clock of 16.2 MHz (hereinafter referred to as VCK), a video horizontal synchronizing signal (hereinafter referred to as HD) and a video required in each unit of a stand-alone MUSE pay broadcast decoder. Reproduces a frame synchronization signal (hereinafter referred to as VFRAM) and is an independent M
Supply to each part in the USE pay broadcast decoder. An audio processing unit 5 reproduces an audio data bit stream (hereinafter referred to as DBS) after 16-bit deinterleaving at a rate of 1.35 MHz from a digital MUSE signal, and an audio frame synchronization signal (hereinafter referred to as FSY) audio data reference. A clock of 1.35 MHz (hereinafter referred to as ACK) is supplied to the descramble unit. A descramble unit 6 takes out scramble-related information from the DBS 13, and based on this, descrambles the scrambled digital MUSE signal 19 to output a descramble MUSE signal 12 and also adds the scrambled audio data bits. A pseudo-random signal (hereinafter referred to as PN) for descrambling the stream 13 is generated.

Reference numeral 7 is an exclusive OR element, which outputs the descrambled DBS 15 by taking the exclusive OR of the DBS 13 and the PN signal 11 for descrambling. A scrambling flag erasing / master frame identification flag bit shift unit 143 erases the video scrambling flag and the audio scrambling flag, and sets the master frame identification bit flag multiplexed in the first audio frame of the master frame of the audio data bit stream signal. Shift to the corresponding position of another audio frame within the same master frame period. Reference numeral 41 is a bit interleaving unit that re-interleaves the 16-bit deinterleaving in the voice processing unit 5. 42 is a BCH (82,74) error correction code addition device, which excludes the descrambled synchronization signal and control code bit of the DBS 15 with respect to 74 bits of information bits in each row of the bit interleave matrix,
Eight error correction bits are added. Reference numeral 44 performs interleaving between 25 voice frames on the basis of the vertical blanking period in the MUSE signal multiplexed by the 25 voice frame interleaving unit.

Reference numeral 45 is a time axis compression unit, which converts voice data at a rate of 1.35 MHz into burst data for multiplexing in the vertical period of the MUSE signal. 46 is a binary value
In the ternary conversion section, continuous binary 3 data is converted into continuous ternary 2
Convert to sample. Reference numeral 47 is a conversion filter, which performs frequency conversion to match the time-axis-compressed, binary / ternary-converted 12.15 MBaud audio data with a video signal sample rate of 16.2 M rate. Reference numeral 48 denotes an encoded audio signal delay circuit, which delay-adjusts the encoded audio signal at the timing of the vertical blanking period audio multiplex region of the video signal output from the descramble unit 6.

Reference numeral 49 is an audio multiplex timing control section for outputting a signal indicating an audio multiplex area of the vertical blanking period of the output MUSE signal from the descramble unit 6. Reference numeral 50 denotes a signal change-over switch, which switches between the output from the descramble unit 6 and the output of the audio data time base compression unit 45 by the output signal of the audio multiplex timing control unit 49. 5
A D / A converter 1 converts a digital MUSE signal into an analog MUSE signal. A MUSE signal output terminal 52 is connected to the MUSE decoder and MUSEVTR.
The operation of the MUSE pay broadcast decoder configured as above will be described below (FIG. 1). The description will be given taking as an example the case where a scrambled MUSE signal is input for both video and audio. The input MUSE signal is digitally converted by the A / D converter 3, and the descrambling unit 6, the audio processing unit 5, the clock / synchronization reproducing unit 4
Is supplied to. The descrambling process is performed as follows. First, the descramble unit 6 extracts and decodes the scramble-related information in the DBS 13 from the voice processing unit 5. The position of scramble-related information is shown in (FIG. 4). FIG. 4 is a voice frame configuration diagram showing bit allocation at the time of A-mode signal multiplexing, scrambling-related information multiplexing positions, and bit allocation in the DBS13 state. The scramble-related information bits are multiplexed in the control code, range bits, and the independent data area, as indicated by the diagonal lines in FIG.

Further, these multiplexed scramble-related information bits are present at a fixed position in the voice frame for each voice mode from the multiplexing position and in an independent data area whose area changes for each voice mode in a diagonal multiplex state. It is classified as something that does. The scramble-related information bits existing in the control code area and range bits exist in a fixed position for each voice mode. The respective bits and positions are shown below. Video scramble flag bit: control code 12th bit, scramble timing bit: control code 13th bit, audio scramble flag bit
..R # 8 bit position.

On the other hand, FIG. 5 shows how the scramble-related information is diagonally multiplexed in the independent data area, which area changes depending on the voice mode. (FIG. 5) is an oblique multiplexing scheme diagram showing how 288 bits of scramble-related information bits are multiplexed between 18 audio frames in the A1 mode. As shown in (FIG. 5), the diagonal multiplexing of the scramble-related information is performed by 1 bit for each row in the voice frame, and 18 voice frames, that is, 288 bits are set as 1 bit.
The unit (hereinafter, these 18 audio frames are defined as a super frame) is used.

The descramble unit 6 extracts and decodes these scramble-related information bits from the DBS 13, and the scramble digital MUS for the video signal.
The E signal 19 is descrambled and the digital descramble video signal 12 is output. For the audio signal, PN so that it can be descrambled by the exclusive OR element 7 in the subsequent stage.
Generate signal 11. In the voice processing unit 5, the digital MU
The audio data in the blanking period is extracted from the SE signal, and for descrambling, the audio signal format is returned to the scrambled position on the broadcasting station side, that is, to the state where PN addition is performed on the audio signal. Since the audio signal is scrambled immediately before bit interleaving, the receiving side returns the audio signal format to the audio frame format in this state, and the same PN signal 11 as that added to the DBS 13 at the time of scrambling is subjected to exclusive logic. The addition is performed by the summing element 7 to descramble the audio signal.

Next, the descrambled DBS 15 is input to the scramble flag erasing / master frame identification flag bit shifting section 143. Scramble flag erasing / master frame identification flag bit shift unit 143
Then, the video scramble flag (b # 12) and the audio scramble flag (r # 8) are erased, and the master frame identification bit flag multiplexed in the first audio frame of the master frame of the audio data bitstream signal is added to the master frame. Change to the corresponding position of another audio frame within the period. This is because if the scramble flag remains in the descrambled MUSE signal,
This is because the decoder cannot recognize the program normally because it is recognized as a scrambled MUSE signal despite the fact that the MUSE signal is descrambled, and if the master frame identification flag bit remains normally, the MUSE signal at the subsequent stage will not be displayed. This is because the scramble-related information acts on the descramble unit when the decoder is, for example, a descramble unit built-in type, so that an incorrect viewing fee or the like may be charged.

FIG. 2 shows an example of the circuit configuration of the scramble flag erasing / master frame identification flag bit shift section. In FIG. 2, reference numeral 15 is a voice DBS to which the output of the exclusive OR element 7 is input. Reference numeral 62 is a voice frame synchronization signal (FSY), and 63 is a voice reference clock 1.35 MHz (ACK). Reference numeral 60 is an audio bit counter, which is reset for each audio frame and ACK 63
To count 0 to 1349. Reference numeral 64 is a data flip-flop, which is a control code first indicating the A / B mode of voice.
The bits (hereinafter, control bits 1st to 22nd bits are referred to as b # 1 to b # 22, respectively) are detected. Reference numeral 168 denotes a timing generation circuit, which is a b # indicating a voice A / B mode.
A timing pulse for detecting the 1 flag and the master frame identification bit b # 14 indicating the master frame is output. A bit gate 69 outputs a timing pulse for detecting the video scramble flag b # 12 and the audio scramble flag R # 8 among the scramble-related information bits.

Reference numeral 90 is a pulse for detecting the b # 1 of the DBS 15, and reference numeral 92 is a timing pulse signal for detecting the b # 14 indicating the timing of the voice master frame transmitted every 2 superframes, that is, every 36 voice frames. ..

A data flip-flop 75 detects b # 14 in the DBS 15, that is, a voice master frame identification flag bit by the b # 14 detection timing pulse 92 output for each voice frame. Reference numeral 76 is a data flip-flop, and 78 is a logical product element. This combination differentiates the b # 14 detection signal output from the data flip-flop 75 into one clock width.

A logical sum element 100 outputs the logical sum of the output of the bit gate 69 and the logical product element 78.

A logical product element 165 is a logical sum element 100.
Is output, the video scramble flag b # 12 and the audio scramble flag r # in the audio data bit stream are output.
It erases by setting 8 bits and the regular master frame identification flag bit to LOW forcibly.

Reference numeral 194 is a delay adjustment circuit, which is a logical product element 78.
Is delayed until the master frame identification flag bit position of another audio frame within the same master frame period.

Reference numeral 167 is an OR element, which is a delay adjustment circuit 194.
When the output of is high, the data bit stream is forced high.

A data flip-flop 196 outputs a data bit stream at the timing of ACK 63.

The operation of the scramble-related information bit erasing section will be described below with reference to (FIG. 2) and (FIG. 3). FIG. 3 is a signal waveform diagram showing a signal waveform of each part of the scramble flag erasing / master frame identification flag bit position shifting part shown in FIG. (Figure 3) Medium DBS
Numbers 1 to 1350 shown in the waveform of 15 indicate the transmission order of each bit in the audio frame in the DBS state. The FSY 62 is a voice frame synchronization signal indicating the start bit timing of the voice frame as shown in the figure.

First, the operation of shifting the master frame identification flag bit will be described. Timing generation circuit 16
The output 92 of 8 outputs a pulse signal for detecting the b # 14 position, that is, the master frame identification flag bit position, as shown in FIG. Data flip-flop 7
5 is DBS1 by this b # 14 detection timing pulse.
B # 14 in 5, that is, the master frame identification flag bit is detected. The output signal of the data flip-flop 75 shown in FIG. 3 is an oblique multiplex timing generation circuit 168.
The b # 14 timing output 92 of No. 2 shows the result of detecting b # 14 in the DBS15 signal.

In the example of FIG. 3, b # of this voice frame
14 indicates High, that is, the head audio frame of the master frame. This signal is input to the data flip-flop 76 and the logical product element 78 as shown in FIG. 2 and differentially output as shown in the output of the logical product element 78 in FIG. The output of the logical product element 78 is connected to the logical sum element 100 and the delay adjusting unit 194.
The output signal of the logical sum element 100 is the logical product element 16
5, the b # 14 at the master frame identification flag bit position of the DBS 15 is forcedly set to Low, and the delay adjusting unit 194
Of the master frame identification bit flag position is shifted by forcibly setting the master frame identification flag bit after several audio frames, that is, b # 14, to a high level by the logical sum element 167. (FIG. 3) shows an example of shifting after one audio frame.

Next, the erase operation of the video scramble flag b # 12 and the audio scramble flag r # 8 bit will be described. The output 90 of the timing generation circuit 168 is a timing pulse for detecting b # 1 indicating the A / B mode of the voice of the DBS 15 as shown in (FIG. 3). The detection result is output to the bit gate 69 via the data flip-flop 64 as shown in FIG. In the bit gate 69, r # based on the timing pulse indicating the position of the video scramble bit b # 12 and the b # 1 detection result.
Output the pulse indicating the 8-bit position as shown in (Fig. 3),
D through the logical product element 165 through the logical sum element 100
The video scramble bit b # 12 and the audio scramble bit r # 8 of the BS 15 are forced to be Low. (FIG. 3) shows an example of the voice A mode.

As described above, the data bit stream in which the master frame identification bit flag position shift and the scramble bit flag have been erased are output by the data flip-flop 196 at the timing of ACK 63 as shown in FIG. ) Is input to the bit interleave section 41.

The processing of the subsequent stage will be described below with reference to FIG. Bit interleave section 41,
BCH (82,74) processing device 42, 25 frame interleaving device 44, 2/3 value conversion device 46, 12.1
The 5 → 16.2 MHz conversion filter unit 47 is a MUSE audio encoding processing unit that re-encodes the MUSE audio processing decoded by the audio processing unit 5, but this is the same as the corresponding part of the normal MUSE audio encoding processing unit. Therefore, the description is omitted here.

The encoded audio signal delay circuit 48 delay-adjusts the encoded audio signal and adjusts it to the vertical blanking period of the video signal.

Next, the changeover switch 50 switches the output signal from the output of the descramble unit 6 to the audio signal side in the audio multiplexing period according to the output signal of the audio timing control section 49. As described above, according to the present embodiment, the scrambled digital MUSE signal, the 25-frame deinterleaved voice data bit stream after BCH (82,74) error correction are input, and the voice data bit stream is descrambled. Pseudo-random signal (PN signal) and scrambled digital MUSE signal
A descramble unit device for outputting a USE signal,
An exclusive OR device that adds a PN signal output from the descramble unit device and a scrambled audio data bitstream and descrambles the audio data bitstream, and inputs the descrambled audio data bitstream, Scramble flag erasing / audio master frame identification flag bit shift device for erasing multiplexed video scramble flag bit and audio scramble flag bit, erasing audio master frame identification flag bit from regular audio frame and adding to other audio frame And the audio data bit stream output from the scramble flag erasing / audio master frame identification flag bit shifting device is re-Med.
A bit interleave device, a BCH (82,74) error correction addition device for USE audio encoding, 25
Frame interleaver, time axis compressor, binary /
Re-voice MUS comprising ternary conversion device and 12.15 MHz / 16.2 MHz resampling waveform shaping filter device
An E-encoding device, a delay device for delaying the audio signal output from the re-audio MUSE encoding device, and a re-audio MUSE encoding signal output from the delay device at the audio data signal position of the output of the descramble unit device. By providing a signal switching device for multiplexing and a timing control device for controlling the signal switching device, the scrambled M is formed with a simple configuration.
The USE signal can be descrambled, and the descramble signal can be output in a MUSE signal format that can be treated as a non-scrambled normal MUSE signal.

[0052]

As described above, according to the present invention, all the scramble-related information bits diagonally multiplexed in the independent data areas of different positions depending on the audio mode in the audio data bit stream as in the conventional example are included. Regardless of the method of erasing scramble-related information bits, the video frame scramble flag and audio scramble flag multiplexed in the descramble audio data bit stream are erased, and the master frame identification flag bit position is shifted. Since the identification flag bit position shift device is provided, it is possible to provide a stand-alone MUSE pay-broadcast decoder having a simple configuration and having the same effect as erasing all scramble-related information bits.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a pay broadcast decoder according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the present invention.

FIG. 3 is a timing chart for explaining the operation of the main part.

FIG. 4 is a MUS showing multiple positions of scramble-related information.
E audio signal frame configuration diagram

FIG. 5 is a scramble-related information multiplex system diagram showing a diagonal multiplex system of scramble-related signals to independent data areas.

FIG. 6 is a block diagram showing a configuration of a conventional pay broadcast decoder.

FIG. 7 is a block diagram showing a configuration of a main part of a conventional pay broadcast decoder.

FIG. 8 is a timing chart for explaining the operation of the main part.

[Explanation of symbols]

6 descramble unit device 7 exclusive OR device 143 scramble flag erasure / master frame identification flag bit shift device 41 bit interleave device 42 BCH (82,74) error correction code addition device 44 25 frame interleave device 45 time base compression device 46 Binary / ternary converter 47 12.15 / 16.2 MHZ resampling waveform shaping filter device 48 delay device 50 signal switching device 49 timing control device

Claims (1)

Claim: What is claimed is: 1. A scrambled digital multiple sampling coded signal and a voice data bit stream after 25-frame deinterleaving and BCH (82,74) error correction are input, and a voice data bit stream A descramble unit device for outputting a digital multiple sampling coded signal obtained by performing a descramble process on a video signal portion of a pseudo random signal for scrambling and a scrambled digital multiple sampling coded signal, and output from the descramble unit device An exclusive OR device that adds a pseudo-random signal and a scrambled audio data bitstream and descrambles the audio data bitstream, and the descrambled audio data bitstream as inputs, A scramble flag erasing / audio master frame identification flag bit shift device that erases the video scramble flag bit and the audio scramble flag bit that are stored, erases the audio master frame identification flag bit from the regular audio frame, and adds it to another audio frame. , A bit interleaving device for re-multiplexing the audio data bit stream output from the scramble bit erasing / audio master frame identification flag bit shift device into a multi-sampling coded signal, BCH (82,74) error correction adding device, 25 Frame interleaver, time axis compressor, binary / ternary converter, 12.15MHz
/16.2MHz re-sampling waveform shaping filter device for voice re-multiplex encoder for multiple sampling coded signal and delay device for delaying voice signal output from voice re-multiplex encoder for multiple sampling coded signal And a signal switching device that multiplexes the voice signal re-encoded into the descrambled multi-sampling coded signal into the voice independent data area of the output of the descramble unit device, and the timing for controlling the signal switching device. A pay broadcast decoder characterized in that it comprises a controller; descrambles the scrambled multiple sampling coded signal and outputs the descramble signal in the multiple sampling coded signal format.