JPH0537480A - Multiplexer - Google Patents

Abstract

PURPOSE:To obtain the multiplexer which dynamically executes control concerning the priority order of bus arbitration so as to most efficiently execute multiplexing at all times at the multiplexer to multiplex information according to a statistical multiplexing system. CONSTITUTION:The information generated variables (traffic amounts) of plural respective bus requesters 1a-1c are measured and recorded and based on the recorded value of this traffic amount, the priority orders of the respective bus requesters 1a-1c are controlled so as to be dynamically changed. As the method for utilizing the traffic amount, for example, a method is adopted to increase the priority order of the bus requester in the order of the large traffic amount in the same time zone of a previous day. By executing a statistical processing or the like to the recorded values of the plural traffic amounts, further optimum bus arbitration is executed. Thus, the priority orders of the plural respective bus requesters can be optimumly controlled with high probability at all times, and extremely efficient multiplexing can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer for multiplexing information by a statistical multiplexing method.

[0002]

2. Description of the Related Art As a multiplexing system in communication, there are a time division multiplexing system such as circuit switching and a statistical multiplexing system in which information is asynchronously multiplexed at an arbitrary timing. Examples of statistical multiplexing methods include packet multiplexing and ATM (Asynch).
ronous Transfer Mode) There is cell multiplexing, and this method has the advantage that it is efficient because it uses the line only when information is generated. However, since each of them tries to output information asynchronously, the request (bus request signal)
A bus arbiter that arbitrates (arbitration) is required.

The concept of bus arbitration is to "arbitrate for a plurality of bus requesters to acquire and request a common bus." One is "C in the CPU (central processing unit) board (block).
The PU bus is connected to the CPU or DMAC (Direct Memory Access C
ontroller) are the ones that compete, "in this case CP
U and DMAC are bus requesters. The other is that each board shares a common external bus that connects each board.
In this case, each board which is going to send information becomes a bus requester. Here, the latter will be described.

FIG. 8 is a block diagram showing the structure of a conventional multiplexer. In the figure, reference numerals 1a to 1c denote a plurality of bus requesters for outputting information, and 2 denotes each bus requester 1a to.
A bus arbiter for arbitrating bus requests from 1c, 3 is a multiplexer for multiplexing information, and 4 is each bus requester 1a-1c.
Common to all bus requesters 1a, 5a-5c
Bus request signals from the bus arbiter 2 to the bus arbiter 2 and 6a to 6c are bus grant signals from the bus arbiter 2 to the bus requesters 1a to 1c.

FIG. 9 is a block diagram showing a main structure of the bus requester of FIG. In the figure, 1 is a bus requester, 4 is a multiplex bus, 5 is a bus request signal, 6 is a bus grant signal, 10 is a memory for temporarily accumulating information to be transmitted and absorbing instantaneous congestion on the multiplex bus 4, Reference numeral 11 denotes a memory control unit that controls the memory 10. The memory control unit 11 turns on / off the bus request signal 5 based on the amount of information stored in the memory 10, and also sends information to the multiplex bus 4 based on the bus grant signal 6. Control delivery.

FIG. 10 is a detailed configuration diagram showing a conventional bus arbiter disclosed in, for example, a local bus arbiter (SAB82200) manufactured by Siemens. In the figure, 5a to 5c are bus request signals, and 6a to 6c.
Is a bus grant signal, 24a to 24f are gates, and 25a
25f are D-type flip-flops.

Next, the operation of the above-mentioned conventional multiplexer will be described. As shown in FIGS. 8 and 9, for example, the information input to the bus requester 1a is first stored in the memory 10
Accumulated in. When the memory control unit 11 recognizes that the information for the transmission unit to the multiplex bus 4 is stored in the memory 10, it turns on the bus request signal 5a which is a bus request signal to the bus arbiter 2. Since the multiplex bus 4 can occupy only one of the bus requesters, for example, the bus requester 1a, the bus arbiter 2 confirms that the other bus requesters 1b and 1c do not occupy the multiplex bus 4, and then the bus grant signal. Turn on 6a. The memory control unit 11 of the bus requester 1a receives the turn-on of the bus grant signal 6a and instructs the memory 10 to send the information to the multiplex bus 4. The information thus sent to the multiplex bus 4 is sent to the line via the multiplex unit 3.

In the bus arbiter 2 shown in FIG.
Arbitration of the multiplex bus 4 is performed. In this example,
An example of a fixed priority system is shown in which the bus requester 1a has the highest priority, the bus requester 1b is the second, and the bus requester 1c is the last.

As a function of the bus arbiter 2 shown in FIG. 10, the bus request signal 5 is suppressed by the gates 24d to 24f so that the bus grant signal 6 is returned to only one of the bus requesters 1. Further, in order to give priority when a plurality of bus request signals 5 are turned on at the same time, the bus request signal 5a suppresses the bus request signal 5b and the bus request signal 5c, and the bus request signal 5b controls the bus request signal 5c. I try to keep it down.

When a large amount of information is input to each of the bus requesters 1a to 1c at the same time, the information is temporarily stored in the memory 10, and the bus requester 1a is set at the head according to the fixed priority, and then the bus requester 1b, 1
It is sent to the multiplex bus 4 in the order of c. Even when a large amount of information is input only to the bus requester 1c having the lowest priority, the bus requesters 1a, 1b, and
It is sent to the multiplex bus 4 in the order of 1c.

[0011]

Since the above-mentioned conventional multiplexer is configured as described above, the priority order of the bus arbitration is a fixed priority method which is always fixed, and a plurality of bus requesters are provided. Since it is not possible to flexibly deal with fluctuations in the amount of generated information, it is not possible to multiplex efficiently, and a large amount of information is discarded by the low-priority bus requester, and delays increase. was there.

The present invention has been made in order to solve the above-mentioned problems, and can flexibly cope with the fluctuation of the information generation amount of each of a plurality of bus requesters and perform efficient multiplexing. The purpose is to obtain a multiplexer.

[0013]

SUMMARY OF THE INVENTION A multiplexing device according to the present invention comprises a traffic amount measuring unit for measuring the information generation amount of each of a plurality of bus requesters, and a bus requester based on the measured value of the traffic amount measuring unit. A bus arbiter that controls the priority and performs bus arbitration is provided, and the priority of the bus arbitration is dynamically changed.

[0014]

In the multiplexer according to the present invention, a traffic amount measuring unit and a priority control unit in the bus arbiter are provided to dynamically change the priority order of the bus arbitration according to the information generation amount of each of the plurality of bus requesters. Therefore, the priority of the bus requesters can be appropriately controlled in each of the plurality of bus requesters.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a multiplexing device according to an embodiment of the present invention. As the multiplexer shown in FIG. 1, the case where an ATM cell multiplexer is used is illustrated. In the figure, 1a to 1c are a plurality of bus requesters that output information, 2 is a bus arbiter that arbitrates bus requests from the bus requesters 1a to 1c, 3 is a multiplexing unit that multiplexes information, and 4 is each bus requester 1a ... Multiple buses common to 1c, 5a to 5c are bus requesters 1a to 1c
Request signal from the bus arbiter 2 to the bus arbiter 2, 6a to 6c are bus grant signals meaning "bus request permission" from the bus arbiter 2 to each of the bus requesters 1a to 1c, and 7a to 7c are each bus The cell generation signals from the requesters 1a to 1c, and the cell generation signals 7a to 7c are turned on each time a cell arrives at each of the bus requesters 1a to 1c. Reference numeral 8 denotes a traffic amount measuring unit for measuring the traffic amount based on the cell generation signals 7a to 7c output from the bus requesters 1a to 1c, and 9a.
9c are traffic volume information measured by the traffic volume measuring unit 8.

FIG. 2 is a block diagram showing the construction of the essential parts of the bus requester of FIG. In the figure, 1 is a bus requester, 4 is a multiplex bus, 5 is a bus request signal, 6 is a bus grant signal, 7 is a cell generation signal, 10 is a memory, 11
Is a memory control unit for controlling the memory 10. The cell generation signal 7 is output from the memory control unit 11 every time a cell arrives at the bus requester 1, and the memory control unit 11 has accumulated the information of the transmission unit (cell) based on the information storage amount of the memory 10. When the bus request signal 5 is recognized, the bus request signal 5 is turned on at the same time as the conventional device.

FIG. 3 is a block diagram showing the construction of the main parts of the traffic amount measuring unit and the bus arbiter of FIG. In the figure, 2 is a bus arbiter, 5a to 5c are bus request signals, 6a to 6c are bus grant signals, 7a to 7c are cell generation signals, 8 is a traffic amount measuring unit, 9a to 9c are traffic amount information, and 12a to 12c are A counter that counts up when it is detected that the cell generation signals 7a to 7c are turned on. Reference numeral 13 indicates a counter 1 by the priority control unit 14.
2a to 12c, a timer that defines the time to read the traffic volume information 9a to 9c, and 14 is the traffic volume information 9a.
9c is a priority control unit that determines the priority order of the bus requesters 1a to 1c.
Outputs a 6-bit priority control signal 15a to 15f and a reset signal 17 to reset the counters 12a to 12c in the traffic amount measuring unit 8 based on the determination. 16 is a bus grant signal 6a based on the priority control signals 15a to 15f and the bus request signals 5a to 5c.
It is a bus grant generation part which produces | generates-6c.

FIG. 4 is a block diagram showing a main configuration of the priority control section shown in FIG. In the figure, 9a to 9c are traffic volume information, 13 is a timer, 14 is a priority control unit, and 15a to
15f is a priority control signal, 17 is a reset signal, 18 is C
PU (Central Processing Unit), 19 is a buffer for reading the traffic amount information 9a to 9c from the traffic amount measuring unit 8, 20 is a driver for the reset signal 17, 21 is a driver for the priority control signals 15a to 15f, Reference numeral 22 is a memory for recording the traffic amount information 9a to 9c, and 23 is a bus.

FIG. 5 is a detailed block diagram showing the bus grant generating section of FIG. In the figure, 5a to 5c are bus request signals, 6a to 6c are bus grant signals, and 15a to 1
5f is a priority control unit, 24a to 24l are gates, and 25a to
25f is a D-type flip-flop.

FIG. 6 is a flow chart for explaining the operation of the counter of FIG. 3, and FIG. 7 is a flow chart for explaining the operation of the priority control section of FIG. In the figure, S
1 to S11 are processing steps showing an operation process.

Next, the operation of the multiplexer according to the embodiment of the present invention will be described. In this embodiment, the traffic amount is measured every hour, and the bus requesters 1a to 1c are controlled so that the bus requesters 1a to 1c are prioritized in the descending order of the traffic amount in the same time zone on the previous day.

Bus requesters 1a to 1c at power-on
Is determined by setting the initial values of the priority control signals 15a to 15f (processing step S5). In this state, the device of the present invention is the same as the above conventional device. The difference between the device of the present invention and the conventional device is that
Appears when more than a day has passed.

First, the counters 12a to 1 shown in FIG.
The operation of 2c will be described. Counter 1 after power on
2a to 12c are reset (processing step S1).
After that, when it is detected that the cell generation signals 7a to 7c are turned on (processing step S3), the values of the counters 12a to 12c are incremented (incremented) by 1 (processing step S4).
This operation continues until the reset signal 17 is turned on by the priority control unit 14 (processing step S2).

Next, the operation of the priority control section 14 shown in FIGS. 3 and 4 will be described. First, after the power is turned on, the initial values of the priority control signals 15a to 15f are set (processing step S5). The order of priority may be any order. For example, if the bus requester 1a has the highest priority, the bus requester 1b has the second highest priority, and the bus requester 1c has the lowest priority. , The binary codes of the priority control signals 15a to 15f are 0, 0, 1, 0, 1, 1 respectively. When one hour, which is the set time of the timer 13, has elapsed (processing step S
6), the priority control unit 14 reads the counter values of the counters 12a to 12c and records them in the memory 22 in the priority control unit 14 (processing step S7). Then, the counter 12a-
The reset signal 17 of 12c is turned on (processing step S
8), reset the counters 12a to 12c. After that, if one day has not passed since the power was turned on, nothing is done until the time set by the timer 13 elapses again. If more than one day has passed since the power was turned on (processing step S
9) The recorded values of the traffic volume in the same time zone as the previous day are read from the memory 22 (processing step S10), and the priority of the bus requesters 1a to 1c is increased in the order of the recorded value, that is, in the order of the large traffic volume. The codes of the priority control signals 15a to 15f that are to be executed are determined and output (processing step S11).

For example, the recorded value of the traffic amount read from the memory 22 is the bus requesters 1a, 1b, 1c.
, The binary code of the priority control signals 15a to 15f in this case is 0, 1, 1, 1, 0, 0.
Becomes

Next, the operation of the bus grant generator 16 shown in FIGS. 3 and 5 will be described. The bus grant generation unit 16 receives the input priority control signals 15a to 15f.
And the bus request signals 5a to 5c and the current bus grant signals 6a to 6c, the gates 24a to 24l.
The following bus grant signals 6a to 6c controlled by are output. For example, when the bus requesters 1a, 1b, 1c are arranged in order from the highest priority, the priority control signals 15a to 15f are 0, 1, 1, 1, 0, 0 as described above.
Is input to turn on the gates 24h, 24i, and 24j, so that the bus grant signals 6a to 6c are preferentially turned on in the order of the bus requesters 1c, 1a, and 1b. As described above, in the present embodiment, the bus requesters 1a to 1c are controlled so that the bus requesters 1a to 1c are prioritized in the descending order of the cell generation amount (traffic amount) in the same time zone one day before.

In the above embodiment, the case where the number of bus requesters is three has been described, but any number of bus requesters may be used.

Although the ATM cell multiplexer has been described in the above embodiment, any multiplexer may be used as long as it statistically multiplexes asynchronously generated information.

In the above embodiment, the traffic volume is measured and recorded every hour, and the priority of the bus requester is controlled by using the traffic volume in the same time zone one day before. The setting conditions may be changed. For example, it is conceivable to use the traffic volume in the same time zone on the same day one week ago.

In the above embodiment, the case where the information of one time zone is selected and used from the recorded traffic volume information has been described, but the average of the information of a plurality of time zones is used or statistical processing is performed. The processing result may be used.

[0031]

As described above, according to the multiplexer of the present invention, the traffic amount measuring unit for measuring the information generation amount of each of the plurality of bus requesters, and the bus based on the measured value of the traffic amount measuring unit. A bus arbiter that controls the priority of the requester and performs bus arbitration is provided, and the priority of the bus arbitration is dynamically changed.The bus arbitration is based on the past traffic volume record value of each bus requester. Since it is performed dynamically, the priority of each bus requester can be controlled optimally with a high probability at all times, and an excellent effect is achieved in that extremely efficient multiplexing can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multiplexing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main configuration of the bus requester of FIG.

FIG. 3 is a block diagram showing a main configuration of a traffic amount measuring unit and a bus arbiter of FIG.

FIG. 4 is a block diagram showing a main configuration of a priority control unit shown in FIG.

FIG. 5 is a detailed configuration diagram showing a bus grant generation unit in FIG.

6 is a flowchart for explaining the operation of the counter of FIG.

FIG. 7 is a flowchart for explaining the operation of the priority control unit of FIG.

FIG. 8 is a block diagram showing a configuration of a conventional multiplexing device.

9 is a block diagram showing a main configuration of the bus requester of FIG.

FIG. 10 is a detailed configuration diagram showing a conventional bus arbiter.

[Explanation of symbols]

 1,1a to 1c Bus requester 2 Bus arbiter 3 Multiplexing unit 4 Multiplexing bus 5,5a to 5c Bus request signal 6,6a to 6c Bus grant signal 7,7a to 7c Cell generation signal 8 Traffic amount measuring unit 9a to 9c Traffic amount information 10, 22 memory 11 memory control unit 12a to 12c counter 13 timer 14 priority control unit 15a to 15f priority control signal 16 bus grant generation unit 17 reset signal 18 CPU (central processing unit) 19 buffer 20, 21 driver 23 bus 24a to 24l Gates 25a to 25f D-type flip-flops S1 to S11 Processing steps

[Procedure amendment]

[Submission date] December 3, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

FIG. 2 is a block diagram showing the construction of the essential parts of the bus requester of FIG. In the figure, 1 is a bus requester, 4 is a multiplex bus, 5 is a bus request signal, 6 is a bus grant signal, 7 is a cell generation signal, 10 is a memory, 11
Is a memory control unit for controlling the memory 10. The cell generation signal 7 is output from the memory control unit 11 every time a cell arrives at the bus requester 1, and the memory control unit 11 has accumulated the information of the transmission unit (cell) based on the information storage amount of the memory 10. when recognizing, to turn on the bus request signal 5 of the above conventional device the same way.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

For example, the recorded value of the traffic amount read from the memory 22 is the bus requesters 1c, 1a, 1b.
, The binary code of the priority control signals 15a to 15f in this case is 0, 1, 1, 1, 0, 0.
Becomes

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

Next, the operation of the bus grant generator 16 shown in FIGS. 3 and 5 will be described. The bus grant generation unit 16 receives the input priority control signals 15a to 15f.
And the bus request signals 5a to 5c and the current bus grant signals 6a to 6c, the gates 24a to 24l.
The following bus grant signals 6a to 6c controlled by are output. For example, when the bus requesters 1c, 1a and 1b are arranged in order from the highest priority, the priority control signals 15a to 15f are 0 , 1, 1, 1, 0 , 0 as described above.
Is input to turn on the gates 24h, 24i, and 24j, so that the bus grant signals 6a to 6c are preferentially turned on in the order of the bus requesters 1c, 1a, and 1b. As described above, in the present embodiment, the bus requesters 1a to 1c are controlled so that the bus requesters 1a to 1c are prioritized in the descending order of the cell generation amount (traffic amount) in the same time zone one day before.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shin Miura 5-1-1, Ofuna, Kamakura-shi, Kanagawa Mitsubishi Electric Corporation Communication Systems Laboratory

Claims (1)

Claim: What is claimed is: 1. A plurality of bus requesters comprising: a memory for temporarily storing information to be sent to a common bus; and a memory control section for outputting a bus request signal based on the information storage amount of the memory. In the multiplexing device that is provided with, arbitrates the bus request signal output from each bus requester according to the priority, and outputs the bus grant signal to the bus requester with the highest priority, the information generation amount of each bus requester described above. A traffic volume measurement unit that measures the traffic volume and a measurement value of this traffic volume measurement unit are recorded, and a bus arbiter that dynamically controls the priority of the bus requester based on the recorded past traffic volume. A multiplexing device characterized by being provided.