JPH0537383A - Digital sigma type a/d conversion circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of a noise in a specific frequency decided by both a sampling frequency and an input voltage by operating a D/A conversion by a single voltage source and a single feedback capacitor. CONSTITUTION:Switches 32 and 26 are connected in parallel with an input capacitor 20 by clock pulses phi2 and phi2A, and a voltage is inputted to the input of an arithmetic amplifier circuit 25. Then, a voltage obtained by adding a voltage -VR to an input voltage VIN is stored in an integration capacitor 26. Also, when a switch 34 is turned ON in the timing of a clock pulse phi2B, the terminal (a) of a feedback capacitor 30 is connected with the voltage -VR, so that a voltage VR can be added to the input voltage VIN charged in the input capacitor 20, and this voltage can be stored in the integration capacitor 26. Thus, two kinds of voltages obtained by D/A converting the output of a delay circuit 28 by the single voltage -VR and the single feedback capacitor 30, can be outputted, and subtracted from the input voltage VIN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a switched capacitor to convert an analog signal into a digital signal.
The present invention relates to a D conversion circuit, and more particularly to a delta-sigma type AD conversion circuit.

[0002]

2. Description of the Related Art There is known a so-called oversampling delta-sigma AD conversion circuit in which a sampling frequency is increased in order to reduce sampling noise and aliasing noise.

FIG. 3 shows a conventional delta-sigma AD conversion circuit using a switched capacitor, which includes an input capacitor 1, switches 2 and 3 which are turned on at the timing of a clock pulse φ, and an inverted signal * φ of the clock pulse φ. Switches 4 and 5, which are turned on at timing, an integrating capacitor 6 and an operational amplifier circuit 7 which form an integrator circuit, and outputs "0" or "1" depending on the magnitude of the output voltage of the operational amplifier circuit 7 and the ground voltage. The circuit 8, the delay circuit 9 for delaying the digital output of the comparison circuit 8 for one sample period, and the voltage sources V _R , -V forming a 1-bit DA conversion circuit for converting the digital signal of the delay circuit 9 into an analog voltage. _R and the switches 10 and 11, the feedback capacitor 12 for subtracting the DA converted voltage from the input signal, and the timing of the clock pulse φ. Switches 13 and 14 that turn on, and a switch 15 that turns on at the timing of clock pulse * φ
And 16.

In FIG. 3, when the clock pulse φ becomes H level, the switches 2 and 3 are turned on and the input voltage V _IN is charged in the input capacitor 1. Meanwhile, in order to turn on the switch 13 and 14 also by the clock pulse phi, voltage V _R or -V _R selected by the switch 11 and 12 is charged in the feedback capacitor 12. That is, the delay circuit 9
When the output of "1" is charged with a voltage -V _R,
The voltage V _R is charged when the output of the delay circuit 9 is "0". Next, when the clock pulse * φ becomes H level, the switches 4 and 5 are turned on, and the switches 14 and 15 are turned on. As a result, the input capacitor 1 and the feedback capacitor 12 are connected in parallel, and the charge charged in the input capacitor 1 and the charge charged in the feedback capacitor 12 are added. The addition result is applied to the operational amplifier circuit 7, accumulated in the integrating capacitor 6, and output to the comparison circuit 8. Therefore, a digital signal is output from the comparison circuit 8 depending on whether the voltage charged in the integrating capacitor 6 is positive or negative.

[0005]

In the delta sigma type AD converter shown in FIG. 3 [0007], in the DA converter circuit for feeding back the step voltage, using the two voltage sources of voltage V _R and a voltage -V _R Therefore, there may be a difference between the absolute values of the voltage V _R and the voltage −V _R. This difference has a drawback that noise is generated at a specific frequency determined by the sampling frequency and the input signal. Further, it is considered that two feedback capacitors are provided with one voltage source, but there is a drawback that noise is generated similarly when the capacitances of the feedback capacitors are different.

[0006]

The present invention has been made in view of the above-mentioned points, and includes an adding circuit, an integrating circuit, and a decoding circuit, an input capacitor charged by an input signal, and a step. A feedback capacitor charged by a single voltage source corresponding to the voltage, a switch means for selectively connecting one end of the feedback capacitor to the voltage source and the ground potential based on the digital output of the delay circuit, an input capacitor and a feedback capacitor. Is a delta-sigma type AD conversion circuit composed of an amplifier circuit to which the sum of the charge amounts of is applied and an integrating capacitor connected between the input and output of the amplifier circuit,
The switch means applies a voltage source to one end of the feedback capacitor and grounds the other end, and then grounds one end of the feedback capacitor and connects the other end to the amplifier circuit, and after grounding both ends of the feedback capacitor. , An operation of connecting one end of the feedback capacitor to a voltage source and connecting the other end to the amplifier circuit,
Selection is controlled by the output of the delay circuit.

[0007]

According to the above means, when performing 1-bit DA conversion, one feedback capacitor is charged from a single voltage source to obtain a converted voltage to be added to the input, and both ends of the feedback capacitor are After grounding and emptying the charge, one end of the feedback capacitor is connected to a single voltage source to obtain the converted voltage. Therefore, since conversion can be performed with a single voltage source and a single feedback capacitor, there is no difference between the two converted voltage values.

[0008]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, which is a delta-sigma type A using a switched capacitor.
It is a D conversion circuit. The input capacitor 20 has switches 21 and 22 which are turned on at the timing of the clock pulse φ _1.
And switches 23 and 24 that are turned on at the timing of the clock pulse φ ₂ are connected, and the input capacitor 20 is the operational amplifier circuit 2 in which the integration capacitor 26 is connected between the input and the output.
5 input via switch 24. The output of the operational amplification circuit 25 is applied to the input of the comparison circuit 27, and the voltage accumulated in the integration capacitor 26 is compared with the ground voltage. The output of the comparison circuit 27 is output as a digital signal and is delayed by the delay circuit 28 for one sample period. The delay circuit 28 is composed of, for example, a D-FF having a sampling clock as a clock input.
The switch control circuit 29 is a circuit that distributes and outputs the clock pulses φ ₁ and φ ₂ based on the output of the delay circuit 28. Specifically, when the output of the delay circuit 28 is “1”, the clock is controlled. Clock pulse φ ₁ and φ _2
1A and φ _2A are output, and the output of the delay circuit 28 is “0”.
In this case, the clock pulses φ ₁ and φ ₂ are output as clock pulses φ _1B and φ _2B .

On the other hand, the feedback capacitor 30 has a clock
Pulse φ_1ASwitch 31 that turns on at the timing of
Lock pulse φ_2ASwitch 32 that turns on at the timing
And clock pulse φ_1BSwitch that turns on at the timing
33 and clock pulse φ _2BTurn on at
Switch 34 and clock pulse φ₁At the timing of
Switch 35 and clock pulse φ₂Thymin
The switch 36 that is turned on by the switch is connected. here
Therefore, the switches 31 and 34 have a single voltage source -V._RConnected to
The feedback capacitor 30 is operated via the switch 36
It is connected to the input of the amplifier circuit 25.

Next, referring to FIG. 2, the Dell shown in FIG.
The operation of the Tasigma type AD conversion circuit will be described. Figure 2 Smell
Clock pulse φ₁And φ₂The H levels of
The timing has been adjusted so that First,
Lock pulse φ₁Switch becomes H level, switch 21
And 22 are turned on and the input voltage V is applied to the input capacitor 20. _IN
Are charged, and clock pulse φ₁Switch by
35 is turned on and the terminal a of the feedback capacitor 30 is grounded.
It

At this time, when the output of the delay circuit 28 is "1", the switch control circuit 29 is controlled so that the clock pulses φ _1A and φ _2A are output. Therefore, since the switch 31 is turned on at the timing of the clock pulse φ _1A , the voltage −V _R is applied to the terminal of the feedback capacitor 30. Next, when the clock pulse φ ₂ becomes H level, the switches 23 and 24 are turned on, and the voltage charged in the input capacitor 20 is supplied to the input of the operational amplifier circuit 25.
Further, since the switches 32 and 36 are connected in parallel with the input capacitor 20 by the clock pulse φ ₂ and the clock pulse φ _2A and are applied to the input of the operational amplifier circuit 25,
The voltage obtained by adding the voltage −V _R to the input voltage V _IN is accumulated in the integrating capacitor 26.

Meanwhile, when the output of the delay circuit 28 is "0", the switch control circuit 29 so that the clock pulses phi _1B and phi _2B are output is controlled, is output at the same timing as clock pulses phi ₁ Clock pulse φ
_The switch 33 is turned on by _1B . Therefore, both ends a and b of the feedback capacitor 30 are grounded, and the feedback capacitor 30 is completely discharged. Next, when the switch 34 is turned on at the timing of the clock pulse φ _2B , the terminal a of the feedback capacitor 30 is connected to the voltage −V _R , so that the voltage V _R is added to the input voltage V _IN charged in the input capacitor 20. This voltage is stored in the integrating capacitor 26.

As described above, the output of the delay circuit 28 is DA by the single voltage -V _R and the single feedback capacitor 30.
Two types of converted voltages can be generated and subtracted from the input voltage V _IN .

[0014]

As described above, according to the present invention, since the same voltage source and the same feedback capacitor are used to perform 1-bit DA conversion, there is no difference in the step voltage added to the input voltage, and sampling is performed. Generation of noise at a specific frequency determined by the frequency and the input voltage is prevented, and a delta-sigma AD conversion circuit with a high S / N ratio can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

20 Input Capacitors 21, 22, 23, 24 Switch 25 Operational Amplifier Circuit 26 Integrating Capacitor 27 Comparison Circuit 28 Delay Circuit 29 Switch Control Circuit 30 Feedback Capacitors 31, 32, 33, 34, 35, 36 Switches

Claims (2)

[Claims] 1. An adding circuit for adding an input signal and a feedback signal based on delayed data, an integrating circuit for integrating an added output of the adding circuit, and comparing an integrated output signal of the integrating circuit with a predetermined voltage. A quantizer circuit for converting the digital signal by a delay circuit for delaying the digital signal;
In a delta-sigma AD conversion circuit including a decoding circuit that generates the feedback signal based on the digital output of the delay circuit, the addition circuit, the integration circuit, and the decoding circuit are charged by the input signal. An input capacitor, a feedback capacitor charged by a single voltage source corresponding to a step voltage, and switch means for selectively connecting one end of the feedback capacitor to the voltage source and the ground potential based on the digital output of the delay circuit. A delta-sigma type A comprising: an amplifier circuit to which the sum of the charge amounts of the input capacitor and the feedback capacitor is applied; and an integrating capacitor connected between the input and output of the amplifier circuit.
D conversion circuit. 2. The operation of the switch means for applying a voltage source to one end of a feedback capacitor and grounding the other end, and then grounding one end of the feedback capacitor and connecting the other end to the amplifier circuit; The operation of connecting one end of a feedback capacitor to a voltage source and connecting the other end to the amplifier circuit after grounding both ends is selectively controlled by the output of the delay circuit. Type A
D conversion circuit.