JPH0536599A - Formation method of pattern - Google Patents

Formation method of pattern

Info

Publication number
JPH0536599A
JPH0536599A JP21132191A JP21132191A JPH0536599A JP H0536599 A JPH0536599 A JP H0536599A JP 21132191 A JP21132191 A JP 21132191A JP 21132191 A JP21132191 A JP 21132191A JP H0536599 A JPH0536599 A JP H0536599A
Authority
JP
Japan
Prior art keywords
layer
pattern
intermediate layer
resist
upper layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21132191A
Other languages
Japanese (ja)
Inventor
Isao Sato
功 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP21132191A priority Critical patent/JPH0536599A/en
Publication of JPH0536599A publication Critical patent/JPH0536599A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance the dimensional accuracy and the dimensional controllability of the title method and to simplify the process of the title method by a method wherein a three-layer-structure resist which is composed of an upper layer, an intermediate layer and a lower layer is formed on a substrate, the intermediate layer is exposed, the image-reversed pattern is formed on the intermediate layer and a reactive ion etching operation is executed. CONSTITUTION:A three-layer-structure resist which is composed of a lower layer 2 by a photoresist, an intermediate layer 3 by a negative resist containing Si and an upper layer 4 by a negative resist is formed on a substrate 1 in this order. Then, the negative resist for the upper layer 4 is patterned by an ordinary light exposure operation and an ordinary developing operation; after that, the intermediate layer 3 which exposes the whole surface collectively is exposed by making use of an upper-layer pattern 4' as a mask. Then, the intermediate layer 3 is developed; the upper-layer pattern 4' is removed; the image-reversed pattern of the upper-layer pattern 4' is formed on the intermediate layer 3. After that, a reactive ion etching(RIE) operation by means of oxygen is executed to the whole surface by making use of an intermediate pattern 3' as a mask.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子製造に際して
のパターン形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】半導体素子の微細化に対する要求には著
しいものがあり、かかる微細化の達成のためのパターン
形成方法に関しいろいろな検討がなされている。従来広
く行われている3層パターン形成方法はその一つであ
り、例えば文献、ジャーナル バキューム サイエンス
テクノロジー; J.Vac.Sci.Technol.B,Vol.1.No.4.Oc
t.Dec.1983,「Multilayer resist technique for submi
cron opt-ical lithography」
2. Description of the Related Art There is a great demand for miniaturization of semiconductor elements, and various studies have been made on a pattern forming method for achieving such miniaturization. The three-layer pattern forming method that has been widely used in the past is one of them, for example, literature, journal vacuum science technology; J.Vac.Sci.Technol.B, Vol.1.No.4.Oc.
t.Dec.1983, `` Multilayer resist technique for submi
cron opt-ical lithography "

【0003】以下図2を用いてこの3層パターン形成方
法の概略を説明する。図2aにおいて、10は基板で該
基板10上に回転塗布法によって商品名、AZ−140
5J(ヘキスト社)を用い200〜250℃で30分間
ハードベークを行い、下層ホトレジスト層11を2.0
μm厚に形成する。次にその上に同様の方法で0.15μ
m厚のスピンオングラス層(SOG層)による中間層1
2を形成し、更に同様の回転塗布法により0.45μm
に商品名、AZ−1450B(ヘキスト社)による上層
レジスト13を形成する。
The outline of this three-layer pattern forming method will be described below with reference to FIG. In FIG. 2a, reference numeral 10 is a substrate, which is manufactured by a spin coating method on the substrate 10 under the trade name of AZ-140.
5J (Hoechst) is used for hard baking at 200 to 250 ° C. for 30 minutes to make the lower photoresist layer 11 2.0.
It is formed to a thickness of μm. Then on top of it in the same way 0.15μ
Intermediate layer 1 with m-thick spin-on-glass layer (SOG layer)
No. 2 is formed, and 0.45 μm is formed by the same spin coating method.
Then, an upper layer resist 13 having a trade name of AZ-1450B (Hoechst) is formed.

【0004】まず上層レジスト13を、光露光及び現像
することにより、図2bに示すように上層パターン1
3′を形成する。その後、該上層パターン13′をマス
クとして中間層12のSOG層をCF4 系の反応ガスに
よりドライエッチングしてパターンニングし中間層パタ
ーン12′を得る(図2c)。更に図2dのように、前
記中間層パターン12′をマスクとして下層レジスト1
1を酸素による反応性イオンエッチング(RIE)を行
いパターンニングして、下層パターン11′を得るので
ある。
First, the upper layer resist 13 is exposed to light and developed to form the upper layer pattern 1 as shown in FIG. 2b.
3'is formed. After that, the SOG layer of the intermediate layer 12 is patterned by dry etching with a CF 4 -based reaction gas using the upper layer pattern 13 ′ as a mask to obtain an intermediate layer pattern 12 ′ (FIG. 2 c). Further, as shown in FIG. 2d, the lower layer resist 1 is formed by using the intermediate layer pattern 12 'as a mask.
1 is patterned by performing reactive ion etching (RIE) with oxygen to obtain a lower layer pattern 11 '.

【0005】[0005]

【発明が解決しようとする課題】しかし、上述したよう
な3層レジストによるパターン形成方法では次のような
問題が避けられなかった。即ち上述の上層から中間層、
及び中間層から下層へのパターン転写をエッチングによ
って行う為、寸法シフトが発生し易く寸法制御性が低下
する。又中間層をエッチングしてパターン転写を行う
為、専用のエッチング装置が必要であり、更に上層レジ
ストに、中間層のエッチングに耐える高いドライエッチ
ング耐性が要求され、しかも全体の工程が複雑化しスル
ープットの低下が免れなかった。
However, the following problems cannot be avoided by the pattern forming method using the three-layer resist as described above. That is, from the upper layer to the intermediate layer,
Also, since pattern transfer from the intermediate layer to the lower layer is performed by etching, dimensional shift easily occurs and dimensional controllability deteriorates. Further, since the intermediate layer is etched to transfer the pattern, a dedicated etching device is required, and further, the upper layer resist is required to have high dry etching resistance to withstand the etching of the intermediate layer, and moreover, the whole process is complicated and throughput is increased. The decline was unavoidable.

【0006】本発明は、以上述べた従来の3層レジスト
法のようにパターン転写を繰り返して、寸法精度、及び
寸法制御性を低下させ、更にエッチングによるパターン
転写を2回も繰り返すことにより工程が複雑になるとい
う問題点を解決するパターン形成法を提供することを目
的とする。
According to the present invention, the pattern transfer is repeated as in the conventional three-layer resist method described above to reduce the dimensional accuracy and the dimensional controllability, and further the pattern transfer by etching is repeated twice. It is an object of the present invention to provide a pattern forming method that solves the problem of complexity.

【0007】[0007]

【課題を解決するための手段】本発明は、微細パターン
形成方法において、基板上に、被エッチング体による下
層、Si含有ネガレジストによる中間層、及びネガ型レ
ジストによる上層からなる3層構造レジストをこの順に
形成する工程と、前記上層のネガ型レジストを通常の光
露光及び現像によりパターンニングした後、該上層パタ
ーンをマスクとして全面を一括露光する中間層の露光工
程と、該中間層を現像することにより上層パターンを除
去すると共に中間層に上層パターンのイメージ反転パタ
ーンを形成する工程と、その後該中間層パターンをマス
クとして全面を酸素による反応性イオンエッチング(R
IE)を行う工程とを含むものである。
According to the present invention, in a method for forming a fine pattern, a three-layer structure resist consisting of a lower layer of an object to be etched, an intermediate layer of a Si-containing negative resist, and an upper layer of a negative resist is formed on a substrate. The steps of forming in this order, the step of patterning the negative resist of the upper layer by ordinary photoexposure and development, and then the step of exposing the intermediate layer to the entire surface with the upper layer pattern as a mask, and developing the intermediate layer Thereby removing the upper layer pattern and forming an image reversal pattern of the upper layer pattern on the intermediate layer, and then using the intermediate layer pattern as a mask, reactive ion etching (R
IE) is included.

【0008】[0008]

【作用】本発明は、パターン形成にあたって上述の如き
諸工程を導入したものであり、従って、上層から中間層
へのパターン転写を光による一括露光によって行ってい
る為、上層レジストの特性として必ずしも高耐ドライエ
ッチング性を必要とせず、又中間層の一括露光の際にイ
メージ反転され、上層パターンのイメージと反転した中
間層パターンを得ることになり、エッチングによるパタ
ーン転写を下層のO2 RIEの一回しか行わない為、高
スループットかつ高寸法制御性となる。
According to the present invention, the above-mentioned steps are introduced in the pattern formation. Therefore, since the pattern transfer from the upper layer to the intermediate layer is performed by batch exposure with light, the characteristics of the upper layer resist are not necessarily high. without requiring resistance to dry etching, and is image reversal during full field exposure of the intermediate layer, will get an intermediate layer pattern obtained by inverting the upper pattern image, the pattern transfer due to etching of the underlying O 2 RIE one Since it is performed only once, it has high throughput and high dimensional controllability.

【0009】[0009]

【実施例】以下図1によりこの発明の一実施例を説明す
る。図1aに示すように、まず下地基板1上に、下層2
としてホトレジスト、例えばノボラック系ホトレジスト
を回転塗布法により1.0μmの厚さに形成し高温、実
際には200〜250℃以上でベークを行う。次に該下
層2上に、中間層3としてSi含有ネガ型レジスト、例
えばポリアリルシルセスキオキサン(PACS)を同様
に回転塗布法により0.2μm厚に薄く形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. As shown in FIG. 1a, first, a lower layer 2 is formed on a base substrate 1.
As a photoresist, for example, a novolac photoresist is formed to a thickness of 1.0 μm by a spin coating method, and baking is performed at a high temperature, actually 200 to 250 ° C. or higher. Next, a negative Si-containing resist, such as polyallylsilsesquioxane (PACS), is similarly formed as the intermediate layer 3 on the lower layer 2 by the spin coating method to a thin thickness of 0.2 μm.

【0010】次に該中間層3上に、上層4レジストとし
てネガ型レジストを回転塗布法によって0.5μmの厚
さに形成する。次に図1bのように、上層レジスト4を
常法により光露光、及び現像して上層パターン4′を得
る。
Next, a negative resist is formed as the upper layer 4 resist on the intermediate layer 3 by a spin coating method to a thickness of 0.5 μm. Next, as shown in FIG. 1b, the upper layer resist 4 is exposed to light and developed by a conventional method to obtain an upper layer pattern 4 '.

【0011】ここで前記上層レジストとしてDUV光用
レジストである(商品名)SAL−601(シップレー
社)を用いた場合は、露光量として100mJ/cm2 程、
露光後ベーク(PEB)として120℃,1min 程が適
当である。そして現像液としては、下地である中間層3
のPACSへのダメージの殆どないテトラメチルアンモ
ニウムハイドロオキサイド(TMAH)水溶液等の有機
アルカリ現像液が好適である。
When a DUV light resist (trade name) SAL-601 (Shipley Company) is used as the upper layer resist, the exposure dose is about 100 mJ / cm 2 .
A post exposure bake (PEB) of 120 ° C. for about 1 min is suitable. As the developing solution, the intermediate layer 3 which is the base
An organic alkali developing solution such as an aqueous solution of tetramethylammonium hydroxide (TMAH), which causes almost no damage to PACS, is suitable.

【0012】次に全面をArFエキシマレーザ光で一括
照射することにより、上層パターン4′をマスクとして
中間層3のPACSを一括露光し、現像を行い、図1cに
示したように上層パターン4′のイメージとはポジネガ
反転した中間層パターン3′を得る。このPACSのA
rF露光においては、露光量として200mJ/cm2 程が
適当であり、更に現像に際しての現像液としてジメチル
イソブチルケトン(DIBK)を用いたスプレー現像が
好適である。又この現像時に前述の上層パターン4′が
除去され、該上層パターン4′の下地部、つまりArF
エキシマレーザ光が照射されなかった部分は溶解除去さ
れ、中間層パターン3′が形成される。
Next, the entire surface is collectively irradiated with ArF excimer laser light to collectively expose the PACS of the intermediate layer 3 by using the upper layer pattern 4'as a mask and develop the upper layer pattern 4 ', as shown in FIG. 1c. An intermediate layer pattern 3'having a positive / negative reversal with the image of FIG. A of this PACS
In the rF exposure, an exposure dose of about 200 mJ / cm 2 is suitable, and spray development using dimethyl isobutyl ketone (DIBK) as a developing solution is suitable. Further, during the development, the above-mentioned upper layer pattern 4'is removed, and the underlayer of the upper layer pattern 4 ', that is, ArF
The portion not irradiated with the excimer laser light is dissolved and removed, and the intermediate layer pattern 3'is formed.

【0013】その後図1dのように、全面をO2 RIE
することにより、該中間層パターン3′をO2 RIEの
マスクにして下層にパターン転写を行い、下層パターン
2′を得ることができる。上記実施例では、上層をDU
V光、中間層をArFエキシマレーザ光で露光する場合
について説明したが、本発明はこれらに必ずしも限定さ
れるものではない。また、本実施例では下層の被エッチ
ング体としてノボラック系ホトレジストを用いたがこれ
に限定されるものでもない。
Then, as shown in FIG. 1d, the entire surface is O 2 RIE.
By doing so, the intermediate layer pattern 3'can be used as a mask for O 2 RIE to perform pattern transfer to the lower layer to obtain the lower layer pattern 2 '. In the above embodiment, the upper layer is DU
The case of exposing the V light and the intermediate layer with the ArF excimer laser light has been described, but the present invention is not necessarily limited to these. Further, in this embodiment, the novolac photoresist is used as the lower layer to be etched, but the present invention is not limited to this.

【0014】[0014]

【発明の効果】本発明は以上詳細に説明したように、3
層レジスト法において前記上層のネガ型レジストを通常
の光露光及び現像によりパターンニングした後、該上層
パターンをマスクとして全面を一括露光する中間層の露
光工程と、該中間層を現像することにより上層パターン
を除去すると共に中間層に上層パターンのイメージ反転
パターンを形成する工程と、その後該中間層パターンを
マスクとして全面を酸素により反応性イオンエッチング
(RIE)を行う工程とを含むものである。従って、上
層から中間層へのパターン転写を光による一括露光によ
って行っている為、上層レジストの特性として必ずしも
高耐ドライエッチング性を必要とせず、又中間層の一括
露光の際にイメージ反転され、上層パターンのイメージ
と反転した下層パターンを得ることになり、エッチング
によるパターン転写を下層のO2 RIEの一回しか行わ
ない為、高スルートップかつ高寸法制御性となるなど上
記問題を解消し得る。
As described above in detail, the present invention has three advantages.
In the layer resist method, after patterning the upper negative resist by ordinary light exposure and development, an exposure step of an intermediate layer in which the entire surface is collectively exposed using the upper layer pattern as a mask, and the upper layer is developed by developing the intermediate layer. The process includes removing the pattern and forming an image reversal pattern of the upper layer pattern on the intermediate layer, and then performing reactive ion etching (RIE) with oxygen on the entire surface using the intermediate layer pattern as a mask. Therefore, since the pattern transfer from the upper layer to the intermediate layer is performed by collective exposure with light, high dry etching resistance is not necessarily required as the characteristics of the upper layer resist, and the image is inverted when the intermediate layer is collectively exposed. Since the lower layer pattern that is the reverse of the image of the upper layer pattern is obtained and the pattern transfer by etching is performed only once in the lower layer O 2 RIE, the above problems such as high through top and high dimensional controllability can be solved. ..

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例の工程図。FIG. 1 is a process drawing of an example of the present invention.

【図2】従来例の工程図。FIG. 2 is a process diagram of a conventional example.

【符号の説明】[Explanation of symbols]

1 基板 2 下層 2′ 下層パターン 3 中間層 3′ 中間層パターン 4 上層 4′ 上層パターン 1 substrate 2 lower layer 2'lower layer pattern 3 intermediate layer 3'intermediate layer pattern 4 upper layer 4'upper layer pattern

Claims (1)

【特許請求の範囲】 【請求項1】 基板上に、被エッチング体による下層、
Si含有ネガレジストによる中間層、及びネガ型レジス
トによる上層からなる3層構造レジストをこの順に形成
する工程と、 前記上層のネガ型レジストを通常の光露光及び現像によ
りパターンニングした後、該上層パターンをマスクとし
て全面を一括露光する中間層の露光工程と、 該中間層を現像することにより上層パターンを除去する
と共に中間層に上層パターンのイメージ反転パターンを
形成する工程と、 その後該中間層パターンをマスクとして前記被エッチン
グ体を酸素による反応性イオンエッチング(RIE)を
行う工程とを含むパターン形成方法。
Claim: What is claimed is: 1. A lower layer formed of an object to be etched on a substrate,
A step of forming a three-layer structure resist consisting of an intermediate layer of a Si-containing negative resist and an upper layer of a negative resist in this order; and after patterning the upper negative resist by ordinary light exposure and development, the upper layer pattern Exposing the entire surface with the mask as a mask, a step of removing the upper layer pattern by developing the intermediate layer and forming an image reversal pattern of the upper layer pattern on the intermediate layer, and then forming the intermediate layer pattern. A step of performing reactive ion etching (RIE) using oxygen on the object to be etched as a mask.
JP21132191A 1991-07-30 1991-07-30 Formation method of pattern Pending JPH0536599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21132191A JPH0536599A (en) 1991-07-30 1991-07-30 Formation method of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21132191A JPH0536599A (en) 1991-07-30 1991-07-30 Formation method of pattern

Publications (1)

Publication Number Publication Date
JPH0536599A true JPH0536599A (en) 1993-02-12

Family

ID=16604017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21132191A Pending JPH0536599A (en) 1991-07-30 1991-07-30 Formation method of pattern

Country Status (1)

Country Link
JP (1) JPH0536599A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6743885B2 (en) 2001-07-31 2004-06-01 Sumitomo Chemical Company, Limited Resin composition for intermediate layer of three-layer resist
US6887649B2 (en) 2001-06-14 2005-05-03 Fujitsu Limited Multi-layered resist structure and manufacturing method of semiconductor device
JP2007165703A (en) * 2005-12-15 2007-06-28 Nec Electronics Corp Patterning method for multi-layered resist film and manufacturing method for semiconductor device
US8987118B2 (en) 2012-11-07 2015-03-24 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6887649B2 (en) 2001-06-14 2005-05-03 Fujitsu Limited Multi-layered resist structure and manufacturing method of semiconductor device
US6743885B2 (en) 2001-07-31 2004-06-01 Sumitomo Chemical Company, Limited Resin composition for intermediate layer of three-layer resist
JP2007165703A (en) * 2005-12-15 2007-06-28 Nec Electronics Corp Patterning method for multi-layered resist film and manufacturing method for semiconductor device
US7754543B2 (en) * 2005-12-15 2010-07-13 Nec Electronics Corporation Method of patterning multiple-layered resist film and method of manufacturing semiconductor device
JP4734111B2 (en) * 2005-12-15 2011-07-27 ルネサスエレクトロニクス株式会社 Multilayer resist film patterning method and semiconductor device manufacturing method
US8987118B2 (en) 2012-11-07 2015-03-24 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device

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