JPH0536584A - Mask alignment method - Google Patents

Mask alignment method

Info

Publication number
JPH0536584A
JPH0536584A JP3194038A JP19403891A JPH0536584A JP H0536584 A JPH0536584 A JP H0536584A JP 3194038 A JP3194038 A JP 3194038A JP 19403891 A JP19403891 A JP 19403891A JP H0536584 A JPH0536584 A JP H0536584A
Authority
JP
Japan
Prior art keywords
alignment mark
alignment
mask
substrate
mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3194038A
Other languages
Japanese (ja)
Inventor
Tetsuya Yokota
哲也 横田
Shigeru Kawamata
繁 川又
Toshikazu Kamoshita
敏和 鴨志田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP3194038A priority Critical patent/JPH0536584A/en
Publication of JPH0536584A publication Critical patent/JPH0536584A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To perform a mask alignment and exposure operation a plurality of times by exposing an alignment mark in an element manufacturing process and to enhance its alignment accuracy in order to perform an alignment and photolithographic operation a plurality of times so as to correspond to a multilayer structure. CONSTITUTION:When a clad 7 is formed, a substrate-side alignment mark 2 is exposed by using a substrate-side alignment-mark cover 15 composed of Si or the like so that the clad 7 is not deposited on the substrate-side alignment mark 2. When a resist is coated for a second photolithographic operation, it is arranged that the substrate-side alignment mark 2 is not coated with the resist. Consequently, since the substrate-side alignment mark 2 is exposed in the second alignment and photolithographic operation, a mask alignment operation can be performed with high accuracy.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、フォトリソグラフィ技
術におけるマスク合わせ方法(マスクアライメント)に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask alignment method (mask alignment) in photolithography technology.

【0002】[0002]

【従来の技術】フォトリソグラフィを用いたパターニン
グによって、電子回路素子や光回路素子を、高密度化・
高集積化する研究が盛んに行われている。図3に示すよ
うに、中でも、一枚の基板1上に、複数枚のマスクによ
るパターニングを施す場合は、まず基板1上にマスク合
わせのための合わせマーク2の位置決め、図3(A)を
して、ついでその合わせマーク2に第2のフォトマスク
3の合わせマーク4を重ね合わせ、図3(B)をして、
しかる後、露光図3(C)をする方法がとられている。
2. Description of the Related Art Electronic circuit elements and optical circuit elements are densified by patterning using photolithography.
Researches for high integration have been actively conducted. As shown in FIG. 3, among others, when patterning is performed on one substrate 1 with a plurality of masks, first, positioning of the alignment mark 2 for mask alignment on the substrate 1, FIG. Then, the alignment mark 4 of the second photomask 3 is superposed on the alignment mark 2 and FIG.
After that, the method of exposing FIG. 3C is used.

【0003】[0003]

【発明が解決しようとする課題】図3の複数枚のマスク
によるパターニングを施す場合には、第1回目のフォト
マスクを用いた露光によるパターニングと、第2回目の
フォトマスクを用いた第1回目のマスク合わせ露光によ
るパターニングの間に、合わせマークが隠れてしまうよ
うなことが無いが、多層の金属を積み重ねて、より高機
能な素子をパターンの構成として形成するような場合に
は、第1回目の合わせマークが次の金属被覆によって隠
れてしまい、第2回目の合わせフォトリソグラフィが不
可能になってしまうことがある。例えば、ガラス導波路
の形成プロセスのように、第1回目の合わせマークを形
成した後、その上にクラッド膜を被覆するため、第2回
目のフォトリソグラフィの際に第1回目に形成した合わ
せマークが金属被覆の下にかくれてしまい、第2回目の
合わせマークとを合わせることが出来ない場合がある。
When patterning with a plurality of masks in FIG. 3, patterning by exposure using the first photomask and first patterning by using the second photomask are performed. Although the alignment mark is not hidden during the patterning by the mask alignment exposure described in (1), in the case of stacking multiple layers of metal to form a higher-performance element as a pattern structure, The second alignment mark may be hidden by the next metal coating, making it impossible to perform the second alignment photolithography. For example, as in the glass waveguide formation process, after the first alignment mark is formed, the cladding film is coated on the alignment mark. Therefore, the alignment mark formed at the first time during the second photolithography May be hidden under the metal coating and cannot be aligned with the second alignment mark.

【0004】本発明の目的は、前記従来技術の問題点を
解消し、多層構造に対応した複数回数の合わせフォトリ
ソグラフィを可能にするために、素子製造プロセス過程
において合わせマークを露出させて複数回のマスク合わ
せ露光を可能にし、またその合わせ精度を向上させるこ
との可能なマスク合わせ方法を提供することにある。
An object of the present invention is to eliminate the above-mentioned problems of the prior art and to enable alignment photolithography a plurality of times corresponding to a multi-layer structure, by exposing the alignment mark a plurality of times during the device manufacturing process. Another object of the present invention is to provide a mask aligning method that enables the mask aligning exposure described above and can improve the aligning accuracy.

【0005】[0005]

【課題を解決するための手段及び作用】即ち、本発明の
上記目的は、基板上に金属膜をフォトリソグラフィ技術
を用いて多層状に積層した回路を製造する際に、第1の
金属膜上に第1のマスクを用いて基板側合わせマーク付
きのパターンを形成し、該パターン上に次の金属膜を積
層する際に、基板側合わせマークが該金属膜で覆われな
いように基板側合わせマーク部のカバーを用いて次の金
属膜を積層後、該マークカバーを取り外し、該マークカ
バー以外の所にフォトレジストを塗布し次のマスクを用
いて前記基板側合わせマークと次のマスクのマークを合
わせてフォトリソグラフィを行うことを特徴とするマス
ク合わせ方法によって達成される。
That is, the above object of the present invention is to provide a metal film on a first metal film on a first metal film when manufacturing a circuit in which a metal film is laminated in multiple layers on a substrate by using a photolithography technique. When a pattern with a substrate side alignment mark is formed on the substrate using the first mask and the next metal film is laminated on the pattern, the substrate side alignment mark is not covered with the metal film. After stacking the next metal film using the cover of the mark part, remove the mark cover, apply photoresist to a place other than the mark cover, and use the next mask to mark the substrate side alignment mark and the mark of the next mask. The mask alignment method is characterized in that the photolithography is performed in accordance with the above.

【0006】本発明において次の金属膜、次のマスク
の、「次」の意味は、多層、積層回路を製作する場合
は、その層の回数を意味する。
In the present invention, the "next" meaning of the next metal film and the next mask means the number of layers when a multilayer or laminated circuit is manufactured.

【0007】本発明においては、次のフォトリソグラフ
ィ時に塗布されるレジストが、上記露出した該基板側合
わせマーク上にも塗布されてしまう場合にはネガパータ
ンのターゲットマスクによって露光を行い、該基板側合
わせマーク上と極近傍のレジストを除去することも出来
る。
In the present invention, when the resist applied at the next photolithography is also applied on the exposed alignment mark on the substrate side, exposure is performed by using a negative target mask to align the substrate side. It is also possible to remove the resist on and near the mark.

【0008】[0008]

【実施例】以下に本発明の図示を一実施例によって詳細
に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The illustration of the present invention will be described in detail below with reference to an embodiment.

【0009】図2は本発明の合わせフォトリソグラフィ
技術を用いて作成した光スイッチ素子の平面図(A)と
そのA−A断面の拡大図(B)である。光導波路5は、
単結晶シリコンの平面基板1上に、異なる屈折率をもっ
た酸化珪素の層を重ねた構造によって形成されており、
光の伝搬する略矩形状のコア(屈折率nw)6と、該コ
アの上下を覆う低屈折率のクラッド(屈折率nc)7、
8とを有する。基板上の光導波路コア6は少なくとも直
線状に存在する6a−6bと、これに直交するように配
置される6cの枝路によって構成された3つの路6a、
6b、6cを有し、これら3枝路は図2(A)に示すよ
うに軸線が交差する位置関係に置かれている。このう
ち、枝路6aは光導波路コアへの光の入射部として、残
りの2つの枝路6b、6cは光の射出部として機能す
る。ここでは、光の入射光端9の光導波路コア(枝6
a)に対し、一方の射出光端10の枝路6bは入射光端
9の枝路6aの延長線上に、又、他方の出射光端11の
枝路6cは入射光端9の枝路6aと直交するように形成
されている。
FIG. 2 is a plan view (A) of an optical switch element produced by using the combined photolithography technique of the present invention and an enlarged view (B) of its AA cross section. The optical waveguide 5 is
It is formed by a structure in which layers of silicon oxide having different refractive indexes are stacked on a flat substrate 1 of single crystal silicon,
A substantially rectangular core (refractive index nw) 6 through which light propagates, and a low-refractive-index clad (refractive index nc) 7, which covers the core from above and below,
8 and. The optical waveguide core 6 on the substrate has at least three linear paths 6a-6b and three paths 6a constituted by branch paths 6c arranged so as to be orthogonal thereto.
6b and 6c are provided, and these three branch paths are placed in a positional relationship in which the axes intersect as shown in FIG. 2 (A). Among these, the branch path 6a functions as a light incident portion on the optical waveguide core, and the remaining two branch paths 6b and 6c function as a light emitting portion. Here, the optical waveguide core (branch 6) of the incident light end 9 of light is used.
In contrast to a), the branch 6b of one exit light end 10 is on an extension of the branch 6a of the entrance light end 9, and the branch 6c of the other exit light end 11 is the branch 6a of the entrance light end 9. It is formed so as to be orthogonal to.

【0010】光導波路5の途中には、屈折率がコア6の
それと略等しい液体12(例フルオレベンゼン、シクロ
ヘキサノールなど)を挟み込む1本のスリット13が、
それぞれのコア枝路内を伝搬する光路に対して略45°
の角度をなすように設けられ、該スリット13によって
光導波路の交差部分が切断されている。
In the middle of the optical waveguide 5, there is one slit 13 for holding a liquid 12 (eg fluorenebenzene, cyclohexanol, etc.) having a refractive index substantially equal to that of the core 6.
About 45 ° to the optical path propagating in each core branch
The slit 13 cuts the intersecting portion of the optical waveguide.

【0011】該スリット13の溝の中に光導波路5のコ
ア6の屈折率とほぼ等しい屈折率を持つ液体12を充填
しておき、かつ、スリット13の直下に温度制御部14
を形成し、この温度制御部14に通電することによって
スリット13の近傍を加熱し、スリット13内の液体を
気化させる。それによってコア6内を入射光端9から出
射光端10方向に伝搬していた光は、このスリット内の
液体が加熱され気化しているので、スリット13の内面
で反射し、直交する光導波路コア枝路6cへ曲げられ、
出射光端11へ伝搬する。一方、温度制御部14によっ
てスリット13近傍を冷却した場合は、気化した液体は
凝結して液体となりスリット内に戻るので光は再び出射
光端10方向へ直進する。このように、スリット13内
への液体の注入及び除去動作を加熱・冷却による液体の
気化・凝縮によって行なうことにより、高速のスイッチ
ング動作を実現することができる。
A liquid 12 having a refractive index substantially equal to the refractive index of the core 6 of the optical waveguide 5 is filled in the groove of the slit 13, and the temperature controller 14 is provided just below the slit 13.
Is formed, and the temperature controller 14 is energized to heat the vicinity of the slit 13 to vaporize the liquid in the slit 13. As a result, the light propagating in the core 6 in the direction from the incident light end 9 to the outgoing light end 10 is reflected by the inner surface of the slit 13 because the liquid in the slit is heated and vaporized. Bent to core branch 6c,
Propagate to the outgoing light end 11. On the other hand, when the vicinity of the slit 13 is cooled by the temperature control unit 14, the vaporized liquid is condensed and becomes a liquid and returns to the inside of the slit, so that the light goes straight toward the outgoing light end 10 again. In this way, by performing the liquid injection and removal operations in the slit 13 by vaporizing and condensing the liquid by heating and cooling, high-speed switching operation can be realized.

【0012】該スイッチ素子を製作する場合には光導波
路5形成の工程(第1回目フォトリソグラフィ)と、該
スリット13形成の工程(第2回目フォトリソグラフ
ィ)があり、その間には光導波路5内に光を閉じ篭める
ための該クラッド7を形成する工程が含まれる。従来方
法では、第2回目の合わせフォトリソグラフィの時に該
基板側合わせマーク2が該クラッドに覆われてしまうた
めに、高精度のマスク合わせが困難である。
When the switch element is manufactured, there are a step of forming the optical waveguide 5 (first photolithography) and a step of forming the slit 13 (second photolithography), and the inside of the optical waveguide 5 is in between. The step of forming the clad 7 for closing and closing the light is included. In the conventional method, since the substrate side alignment mark 2 is covered with the clad during the second alignment photolithography, it is difficult to perform highly accurate mask alignment.

【0013】しかし、図1に示される本発明による方法
では、クラッド7の形成(工程)の時に、該基板側
合わせマーク2上にクラッド7が堆積しないように、S
iなどによる基板側合わせマークカバー15によって該
基板側合わせマーク2を露出させる工程と、第2回フォ
トリソグラフィのレジスト塗布時に、該基板側合わせマ
ーク2上にレジストが塗布されない様にする。従って、
第2回目の合わせフォトリソグラフィの時には、該基板
側合わせマーク2は露出しているので、高精度なマスク
合わせが可能となる。
However, in the method according to the present invention shown in FIG. 1, when the clad 7 is formed (step), the clad 7 is prevented from being deposited on the substrate side alignment mark 2 so that the clad 7 is not deposited.
The step of exposing the substrate-side alignment mark 2 by the substrate-side alignment mark cover 15 by i or the like, and the resist is not coated on the substrate-side alignment mark 2 during the resist application in the second photolithography. Therefore,
At the time of the second alignment photolithography, since the substrate side alignment mark 2 is exposed, highly accurate mask alignment becomes possible.

【0014】[0014]

【発明の効果】以上に述べたように、本発明によって次
の様な効果を得る事が出来る。
As described above, according to the present invention, the following effects can be obtained.

【0015】(1) フォトリソグラフィ技術を用いた多
層構造の素子を作成する場合に、複数回のマスク合わせ
が可能である。
(1) When a device having a multi-layer structure is formed by using the photolithography technique, mask alignment can be performed a plurality of times.

【0016】(2) 2回目以降の合わせフォトリソグラ
フィの際、露出した基板側合わせマーク上のレジスト除
去によって、合わせマークの視認性が向上し、より高精
度なマスク合わせが可能となる。
(2) In the second and subsequent alignment photolithography, the resist on the exposed alignment mark on the substrate side is removed to improve the visibility of the alignment mark and enable more accurate mask alignment.

【0017】(3) 基板側合わせマークを露出する方法
によって、素子の多重化による高機能化・高集積化が期
待出来る。
(3) By the method of exposing the substrate side alignment mark, higher functionality and higher integration can be expected by multiplexing the elements.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のマスク合わせ方法の工程の一実施例の
側面図。
FIG. 1 is a side view of an embodiment of steps of a mask alignment method of the present invention.

【図2】本発明のマスク合わせ方法で製作した光スイッ
チ素子の平面図(A)とA−A断面図(B)。
FIG. 2 is a plan view (A) and an AA cross-sectional view (B) of an optical switch element manufactured by the mask alignment method of the present invention.

【図3】従来のマスク合わせ方法の一例のフォトマスク
とマスク合わせ平面図、位置決め(A)、マスクの重合
わせ(B)、露出(C)。
FIG. 3 is a plan view of a photomask and a mask alignment example of a conventional mask alignment method, positioning (A), mask overlay (B), and exposure (C).

【符号の説明】[Explanation of symbols]

1 基板 2 基板側合わせマーク 3 次のフォトマスク 4 合わせマーク 5 光導波路 6 6a、6b、6cコア 7 クラッド 8 クラッド 9 入射光端 10 出射光端 12 液体 13 スリット 14 温度制御部 15 マスクカバー 1 substrate 2 substrate side alignment mark 3 next photomask 4 alignment mark 5 optical waveguide 6 6a, 6b, 6c core 7 clad 8 clad 9 incident light end 10 emission light end 12 liquid 13 slit 14 temperature control part 15 mask cover

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板上に金属膜をフォトリソグラフィ技術
を用いて多層状に積層した回路を製造する際に、第1の
金属膜上に第1のマスクを用いて基盤側合わせマーク付
のパターンを形成し、該パターン上に次の金属膜を積層
する際に、前記基板側合わせマークが該金属膜で覆われ
ないように基板側合わせマーク部のカバーを用いて次の
金属膜を積層後、該マークカバーを取り外し、該マーク
カバー以外の所にフォトレジストを塗布し、次のマスク
を用いて前記基板側合わせマークと次のマスクのマーク
を合わせてフォトリソグラフィを行うことを特徴とする
マスク合わせ方法。
1. A pattern with a substrate side alignment mark using a first mask on a first metal film when manufacturing a circuit in which a metal film is laminated in multiple layers on a substrate using a photolithography technique. And when a next metal film is laminated on the pattern, after the next metal film is laminated by using the cover of the substrate side alignment mark part so that the substrate side alignment mark is not covered with the metal film. A mask characterized in that the mark cover is removed, a photoresist is applied to a place other than the mark cover, and the substrate side alignment mark and the mark of the next mask are aligned using the next mask to perform photolithography. Matching method.
JP3194038A 1991-08-02 1991-08-02 Mask alignment method Pending JPH0536584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3194038A JPH0536584A (en) 1991-08-02 1991-08-02 Mask alignment method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3194038A JPH0536584A (en) 1991-08-02 1991-08-02 Mask alignment method

Publications (1)

Publication Number Publication Date
JPH0536584A true JPH0536584A (en) 1993-02-12

Family

ID=16317903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3194038A Pending JPH0536584A (en) 1991-08-02 1991-08-02 Mask alignment method

Country Status (1)

Country Link
JP (1) JPH0536584A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019138966A (en) * 2018-02-07 2019-08-22 三菱電機株式会社 Film resist and method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019138966A (en) * 2018-02-07 2019-08-22 三菱電機株式会社 Film resist and method for manufacturing semiconductor device

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