JPH0536289A - Bias potential generating circuit - Google Patents

Abstract

PURPOSE:To provide a bias potential generating circuit which can raise the bias potential in a short time at the time of releasing the standby, to suppress the current consumption in an action condition and to shorten the access time without depending on the power potential by the potential of the bit line when the data are read from a memory cell. CONSTITUTION:At the time of releasing the standby, a transistor N9, when a bias potential Vbias is lower than a stationary voltage, is conducted, and supplies the current to an output terminal 21. Subsequently, by a transistor N5, the bias potential Vbias is outputted. Therefore, the bias potential Vbias, after the standby is released, rises in a short time, and the current consumption of direct current at the time of the stationary action can be reduced. After the standby is released, a transistor P4 raises the bias potential Vbias accompanying the rise of a Vcc. Then, the dependency of a bit line potential Vbit for the power Vcc can be removed and the access time of the memory cell can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory such as an EPROM (Erasable Programmable ReadOnly Memor).
related to the bias potential generation circuit applied to y),
The present invention relates to a bias potential generation circuit that supplies a bias potential to a bit line.

[0002]

2. Description of the Related Art FIG. 1 shows a read circuit of a general EPROM. One ends of the sense line 11 and the reference line 12 are connected to a differential amplifier 13 that constitutes a sense amplifier. Y is connected to the sense line 11 via a transistor Q1 serving as a transfer gate.
It is connected to one end of the current path of a plurality of bit line selecting transistors Q2 that constitute the selector 14. Bit lines BL are connected to the other ends of the current paths of these transistors Q2, and EPRO is connected to these bit lines BL.
A plurality of memory cells Q3 of M are connected to each other, and a memory cell array 15 is constituted by these.

At the other end of the reference line 12, a transistor Q4 as a transfer gate,
Via the transistor Q5 which constitutes the dummy selector,
It is connected to the reference dummy cell Q6. The dummy cell Q6 is always in the erased state.

The sense line 11 and the reference line 12 are connected to a power source Vcc via transistors Q7 and Q8 as loads. Further, the output terminals of a bias potential generation circuit 16 that generates a bias potential Vbias are connected to the gates of the transistors Q1 and Q4.

In the above structure, the differential amplifier 13 compares the level of the sense line 11 changed according to the data stored in the selected memory cell Q3 with the level of the reference line 12 kept at a constant potential. Thus, the data stored in the memory cell Q3 is determined.

The case of reading the data "1" stored in the memory cell Q3 will be described. The memory cell Q3 in which the data "1" is stored is an erased cell having a low threshold value. Therefore, this transistor conducts when selected. Then, the charge of the sense line 11 charged by the transistor Q7 becomes
1, Q2, the bit line BL, and the memory cell Q3 are discharged. Therefore, the bit line BL is connected to the transistor Q7.
A low potential of about 1.0 V, for example, that balances the charged charge determined by the discharge and the discharge by the memory cell Q3.

Next, the case of reading the data "0" stored in the memory cell Q3 will be described. Data “0”
The memory cell Q3 in which is stored has a high threshold value. Therefore, even if this transistor is selected, it does not conduct, or even if it conducts, the flowing current is significantly smaller than that of the cell storing "1". Therefore, the sense line 11 and the bit line BL are charged by the transistor Q7 and the potential rises, but the bias potential output from the bias potential generation circuit 16 is Vbias,
When the threshold value of the transistor Q1 considering the back gate bias is Vthn, the potential of the bit line BL is Vbias−.
When the voltage exceeds Vthn, the transistor Q1 is turned off, and the potential of the bit line BL is no longer charged.

On the other hand, the potential of the sense line 11 is charged to Vcc-Vthp by the transistor Q1 when the threshold value of the transistor Q7 is Vthp. Therefore, the potential of the bit line BL at the time of reading is Vbias− due to the bias potential.
It is clamped below Vthn. The potential of the reference line 12 is set in the same manner as the sense line 11 by using the dummy cell Q6, but by making the size of the transistor Q8 larger than that of the transistor Q7 and increasing the charging potential,
It is set near the intermediate potential of the swing of the sense line 11 due to the change of the data "1" and "0".

The bit line potential at the time of reading is Vbias-Vth
The reason for clamping to n is as follows. As is well known, when writing data to a memory cell, the control gate and drain are set to a high potential for writing of Vcc or higher, and hot electrons are injected into the floating gate.

However, even if the potentials of the control gate and drain are low, if stress is applied for a long time, so-called soft write causes a slight amount of electrons to be injected into the floating gate. Therefore, the bit line potential during reading is
It must be set in consideration of the change in data due to this soft write.

Specifically, even if the memory cell in which the data "1" is stored is continuously read during the warranty period of, for example, 10 years, it is necessary that the fluctuation of the threshold value due to the soft write does not affect the normal operation at all. There is. Therefore, the potential of the bit line is clamped to a low level by using the bias potential. That is, the potential of the bit line is usually 1.0, for example.
It is set to about V.

Further, when the data "0" is read from the memory cell, the upper limit of the bit line potential can be kept low,
The level difference from the bit line potential when reading data "1" from the memory cell can be set to a small value of about 0.2 to 0.3V. The drain diffusion capacitances of many memory cells are added to the bit line. However, since the level difference between "1" and "0" is small, the time required for level change is short and the access speed is high.

Further, since the potential of the sense line 11 separated by the transistor Q1 as a transfer gate fluctuates sufficiently large as described above, the margin of the differential amplifier 13 can be sufficiently large.

Next, the bias potential generating circuit 16 will be considered. The potential of the bit line is Vbias as described above.
-Clamp to Vthn. Therefore, the bias potential Vbi
When the level of as changes due to noise or the like, the level of the bit line changes accordingly. However, since the bit line has a large capacitance, it takes a long time to recover the original level once the level changes. Therefore, the differential amplifier 13 also takes a long time to determine the data. Therefore, it is important that the bias potential Vbias is not affected by power supply noise.

Further, in the case where the level of the power supply Vcc is raised to 5 V or more for testing when checking the write amount, in order to prevent the soft write, the bias potential Vbi
It is desirable that as is constant without being affected by the power supply Vcc. FIG. 2 shows a conventional bias potential generating circuit.

The gate and source of the depletion type N-channel transistor N1 are connected to the output terminal 11. This transistor acts as a load, the drain of which is connected to the drain of the P-channel transistor P1. The transistor P1 cuts off the current flowing through the transistor N1 during standby, and is a sufficiently large transistor. The source of the transistor P1 is connected to the first power supply Vcc, and the gate is supplied with the chip enable signal / CE.

The gate and drain of the enhancement type N-channel transistor N2 are connected to the output terminal 11. The source of the transistor N2 is connected to the gate and drain of the enhancement type N-channel transistor N3. The source of the transistor N3 is connected to the second power supply, for example, the ground potential. Further, the output terminal 11 is connected to the drain of an enhancement type N-channel transistor N4. The source of the transistor N4 is connected to the second power supply, and the gate is supplied with the chip enable signal / CE. The transistor N4 resets the bias potential Vbias output from the output terminal 11 to the ground level. In the above configuration, when the chip enable signal / CE becomes low level, the transistor P1 becomes conductive and current flows through the transistors N1, N2 and N3.

FIG. 3 shows current characteristics (load characteristics) of the circuit shown in FIG. Here, I1 is a current flowing through the transistor N1, and I23 is a current flowing through the transistors N2 and N3. As shown in FIG. 3, the current I23 is
It begins to flow when the bias potential Vbias becomes about 2 Vthn or more. The transistor N2 has a threshold value Vthn due to the substrate bias.
Is a little high, but it starts to flow at almost this potential. Current I
23 is the bias potential Vbias.
And this potential is at the point of the threshold value 2Vthn + α. In the vicinity of the intersection A, the transistor N1 operates in the saturation region. Therefore, even if the power supply Vcc changes and becomes, for example, as shown by the dashed line in FIG.
The position of does not change. Therefore, the bias potential Vbias
Is constant regardless of the potential of the power supply Vcc.

[0019]

The bias potential generation circuit 16 is composed of an analog circuit. On the other hand, recent devices such as EPROM are
It is common knowledge that it is composed of CMOS circuits and consumes low power. Therefore, it is desirable to reduce the direct current flowing through the bias potential generation circuit as much as possible. Therefore, it is necessary to reduce the size of the depletion type N-channel transistor N1 and reduce the current. However, during standby, the transistor P1 cuts off the direct current and the transistor N4 drops the bias potential Vbias to the ground potential. Therefore, the rise time of the bias potential when the chip is selected and becomes active is delayed by reducing the size of the transistor N1. Therefore, the size of the transistor N1 cannot be reduced more than necessary.

Further, as the memory cell is miniaturized and the gate length, the width of the insulating film, etc. are scaled, the memory cell becomes more sensitive to writing. Therefore, in order to prevent soft writing, it is necessary to lower the potential of the bit line. That is, in the case of the circuit shown in FIG. 2, it is necessary to reduce the potential α in FIG. However, also in this case, the above problem occurs if the size of the transistor N1 is made smaller than necessary.

On the other hand, FIG. 4 shows the relationship between the bias potential Vbias and the bit line potential Vbit in the circuit shown in FIG. As described above, the bias potential Vbias is constant within the range of the power supply Vcc at which the circuit operates normally, regardless of the power supply Vcc. However, the bit line potential Vbi
The t becomes low as the power supply Vcc increases in the range where the bias potential Vbias is constant. That is, since the power supply Vcc is applied to the gate of the memory cell, when the power supply voltage rises, the current flowing through the memory cell increases.

In FIG. 4, the point PA where the potential of the bit line becomes maximum is lower than the normal operating voltage Vcc = 5V because the bias potential Vbias does not depend on the power source Vcc.
Therefore, assuming that the maximum bit line potential in consideration of soft write is Vsoft, the bit line potential Vbi at the point PA.
t will be suppressed to the potential Vsoft. Then, at the actual operating point PB, the potential Vbit of the bit line becomes lower than the potential Vsoft. Therefore, the current of the memory cell at the operating point PB is reduced due to the lower drain current, and the access time is deteriorated as compared with the case of the potential Vsoft.

The present invention has been made to solve the above problems, and an object of the present invention is to enable the bias potential to be raised in a short time when the standby is released, and to reduce the current consumption in the operating state. An object of the present invention is to provide a bias potential generation circuit that can be suppressed and, moreover, when reading data from a memory cell, the potential of the bit line does not depend on the power supply potential and the access time can be shortened.

[0024]

In order to solve the above problems, the present invention provides a predetermined potential at one end of a current path,
The gate and the other end of the current path are connected to the output end, and a depletion type transistor that supplies a predetermined potential to the output end and the output end are connected. When the output end is in the predetermined potential state, a current flows to the output end. And a current supply circuit for supplying

The output terminal for supplying the bias potential to the bit line of the semiconductor memory and the one end of the current path are the first terminals.
A first transistor connected to the electric potential of the first transistor and turned on in response to a control signal, and one end of the current path is connected to the other end of the current path of the first transistor, and the other end of the current path and the gate are output. A depletion type second transistor for supplying a predetermined potential to the output terminal when the first transistor is connected to the terminal and one end of the current path is connected to the first potential. And a third transistor that is turned on in response to the second transistor, one end of the current path is connected to the other end of the current path of the third transistor, the other end of the current path is connected to the output terminal, and the gate is the second terminal. And a depletion-type fourth transistor that supplies a current to the output end when the output end is lower than a predetermined potential when the third transistor is conductive. .

Further, an output end for supplying a bias potential to the bit line of the semiconductor memory and one end of the current path are connected to the first potential, and are electrically connected in response to a control signal.
And one end of the current path is connected to the other end of the current path of the first transistor, the other end of the current path and the gate are connected to the output terminal, and when the first transistor is conductive, the output A depletion-type second transistor that supplies a predetermined potential to the end, one end of the current path is connected to the first potential, and the other end of the current path is connected to the output end, in response to the control signal. And a third transistor that supplies a current to the output terminal.

Further, the output end for supplying the bias potential to the bit line of the semiconductor memory and the one end of the current path are the first
A first transistor connected to the electric potential of the first transistor and turned on in response to a control signal, and one end of the current path is connected to the other end of the current path of the first transistor, and the other end of the current path and the gate are output. A depletion type second transistor for supplying a predetermined potential to the output terminal when the first transistor is connected to the terminal and one end of the current path is connected to the first potential. And a third transistor that is turned on in response to the second transistor, one end of the current path is connected to the other end of the current path of the third transistor, the other end of the current path is connected to the output terminal, and the gate is the second terminal. A depletion-type fourth transistor for supplying a current to the output terminal when the third transistor is connected to the potential of the One end connected to said first potential,
The other end of the current path is connected to the output end, and a fifth transistor that boosts the output end according to the control signal is provided. Further, the first potential is composed of a power source potential. Further, the second potential is composed of a ground potential. Further, the semiconductor memory is
It is composed of an EPROM.

[0028]

That is, in addition to the depletion type transistor which supplies a predetermined bias potential to the output end, a current supply circuit which supplies a current to the output end when the output end is in a predetermined range of potential state is provided. Therefore, the current supply circuit can raise the bias potential in a short time after the standby is released.

The current supply circuit is composed of a third transistor which is made conductive in response to a control signal and a depletion type fourth transistor. When the third transistor is made conductive, the fourth transistor is controlled. A current is supplied to the output end when the output end is lower than a predetermined potential by the first transistor that is turned on in response to the signal.
Therefore, the bias potential can be raised in a short time after the standby is released.

Further, when the first transistor becomes conductive in response to the control signal, the depletion type second transistor supplies a predetermined bias potential to the output terminal. At the same time, the third or fifth transistor is rendered conductive in response to the control signal and supplies a current corresponding to the first potential to the output end. Therefore, the bit line of the semiconductor memory changes according to the first potential, and the access speed of the semiconductor memory can be increased.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows a bias potential generating circuit 51 according to the first embodiment of the present invention. In FIG. 5, the gate and the source of the depletion type N-channel transistor N 5 are connected to the output terminal 21.
This transistor N5 acts as a load, the drain of which is connected to the drain of the P-channel transistor P2. The transistor P2 cuts off the current flowing through the transistor N5 during standby.
The size of the transistor is such that the gate length is sufficiently large. The source of this transistor P2 is the first power supply Vcc.
The chip enable signal / CE is supplied to the gate.

The gate and drain of the enhancement-type N-channel transistor N6 are connected to the output terminal 21. The source of the transistor N6 is connected to the gate and drain of an enhancement type N channel transistor N7. The source of the transistor N7 is connected to the second power supply, for example, the ground potential.

Further, the output terminal 21 is connected to the drain of an enhancement type N-channel transistor N8. The source of the transistor N8 is connected to the second power source, for example, the ground potential, and the gate is supplied with the chip enable signal / CE. The transistor N8 resets the bias potential Vbias output from the output terminal 21 to the ground level.

On the other hand, the output terminal 21 is connected to the source of a depletion type N-channel transistor N9. This transistor N9 acts as a load, its gate is connected to a second power supply, for example ground potential, and its drain is connected to the drain of the P-channel transistor P3. The transistor P3 cuts off the current flowing through the transistor N9 during standby. The source of the transistor P3 is connected to the first power supply Vcc, and the gate is supplied with the chip enable signal / CE.

In the above structure, when the transistors P2 and P3 are turned on in response to the chip enable signal / CE,
First, a current flows through the transistor N9. Since the transistor N9 is of the depletion type, the current I9 flows while the bias potential Vbias output from the output terminal 21 is low. However, unlike the transistor N5, the gate of the transistor N9 is at the ground potential, so that the flowing current decreases as the bias potential Vbias increases. When the bias potential Vbias becomes almost constant, no current flows through the transistor N9, and the bias potential Vbias is output by the current flowing through the transistor N5. FIG. 6 shows the current characteristics of the above circuit.

Now, the bias potential Vbi at the time of releasing the standby
Considering the rise of as, the current I9 indicated by the diagonal lines in FIG.
Will contribute to the charging of the bias potential Vbias.
Therefore, even if the charging current by the transistor N5 is reduced by that amount, the rise of the bias potential Vbias is not worse than in the case of FIG. At the point A1 where the bias potential Vbias becomes a constant potential, almost no current I9 flows, and the direct current is only I5 flowing in the transistor N5. This current I5
Is smaller than that shown in FIG. For this reason,
The direct current consumption can be reduced during the steady operation.
Further, the bias potential Vbias does not depend on the power source Vcc as in the circuit shown in FIG. Therefore, according to this embodiment, it is possible to reduce the DC current consumption during the operation without delaying the rising time at the time of releasing the standby. Figure 7
The second embodiment of the present invention is shown. The same parts as those in FIG. 5 are designated by the same reference numerals and only different parts will be described.

In this embodiment, P-channel transistor P4 is used instead of the transistors N8 and P3 in the first embodiment.
Is provided. That is, the output terminal 21 is connected to the drain of the P-channel transistor P4. The source of the transistor P4 is connected to the power supply Vcc, and the gate is supplied with the chip enable signal / CE. The size of the transistor P4 is smaller than that of the transistor P2.

In the above structure, the transistors P2 and N
The operations of 5 to N7 are the same as in the above embodiment. The current flowing through the transistor P4 depends on the power source Vcc. That is, when the chip enable signal / CE is active, the gate of the transistor P4 is at ground potential,
The source is the power supply Vcc. Therefore, the gate-source potential VGS of the transistor P4 changes according to the power supply Vcc. Therefore, when the power supply Vcc rises, the bias potential Vbias output from the output terminal 21 via the transistor P4 also rises. However, the transistor N5
Since the transistor P4 does not depend on the power source Vcc and exhibits constant current characteristics, the bias potential Vbias can be made dependent on the power source Vcc by making the size of the transistor P4 smaller than that of the transistor P2.

By appropriately making the bias potential Vbias dependent on the power supply Vcc, the decrease in the bit line potential Vbit accompanying the increase in the power supply Vcc shown in FIG. 4 can be canceled by the increase in the bias potential Vbias.

That is, as shown in FIG. 8, the bias potential Vbias rises as the power supply Vcc rises, but the bit line potential Vbit is constant from the point PA to the operating point PB, and the bit line with respect to the power supply Vcc. The dependency of the potential Vbit can be removed. Therefore, the bit line potential Vbit in the vicinity of the operating point PB can be raised to the maximum bit line potential Vsoft in consideration of the soft write, so that the drain as shown in FIG. It is possible to prevent a decrease in cell current due to a decrease in potential and prevent a delay in access time. FIG. 9 shows a third embodiment of the present invention, in which the same parts as those in FIGS. 5 and 7 are designated by the same reference numerals.

This embodiment is a combination of the first and second embodiments. According to this embodiment, the first and second
It is possible to obtain the effects of preventing the delay of the rise of the bias potential at the time of releasing the standby, reducing the direct current consumption in the steady operation, and preventing the delay of the access time, which are obtained in the embodiment.

In the above embodiments, the case where the present invention is applied to the EPROM has been described. However, the present invention is not limited to this, and it can be applied to, for example, a flash / EPROM, a DRAM or the like that can electrically and collectively erase stored data. Can also be applied. Of course, various modifications can be made without departing from the scope of the invention.

[0044]

As described above in detail, according to the present invention, the bias potential can be raised in a short time when the standby is released, and the current consumption in the operating state can be suppressed, and the memory cell can be suppressed. It is possible to provide a bias potential generation circuit capable of shortening the access time because the potential of the bit line does not depend on the power supply potential when data is read from.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part showing a read circuit of a general EPROM.

FIG. 2 is a circuit diagram showing a conventional bias potential generation circuit.

FIG. 3 is a diagram showing current characteristics of the circuit shown in FIG.

4 is a characteristic diagram showing a relationship between a bias potential Vbias and a bit line potential Vbit in the circuit shown in FIG.

FIG. 5 is a circuit diagram showing a bias potential generating circuit according to the first embodiment of the present invention.

6 is a diagram showing current characteristics of the circuit shown in FIG.

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

8 is a characteristic diagram showing a relationship between a bias potential Vbias and a bit line potential Vbit in the circuit shown in FIG.

FIG. 9 is a circuit diagram showing a third embodiment of the present invention.

[Explanation of symbols]

N5, N9 ... Depletion type N-channel transistor, P2, P3, P4 ... P-channel transistor, 21
... output terminal, Vcc ... first power supply, Vbias ... bias potential,
BL ... bit line, Q3 ... memory cell, 16 ... bias potential generating circuit.

Claims (7)

[Claims] 1. A predetermined potential is supplied to one end of the current path,
The gate and the other end of the current path are connected to the output end, and a depletion type transistor that supplies a predetermined potential to the output end, and the output end when the output end is connected to the output end and the output end is in a predetermined range of potential state A bias potential generating circuit, comprising: a current supply circuit that supplies a current to the. 2. An output terminal for supplying a bias potential to a bit line of a semiconductor memory; a first transistor, one end of a current path of which is connected to a first potential, and which is made conductive in response to a control signal; When one end of the path is connected to the other end of the current path of the first transistor, the other end of the current path and the gate are connected to the output terminal, and the first transistor is conductive,
Second depletion type that supplies a predetermined potential to the output end
And a third transistor connected to the first potential at one end of the current path and rendered conductive in response to the control signal, and one end of the current path to the other end of the current path of the third transistor. Connected, the other end of the current path is connected to the output end, the gate is connected to the second potential, and the third transistor is conducting, the output end is lower than the predetermined potential when the output end is lower than the predetermined potential. And a depletion-type fourth transistor for supplying a current to the bias potential generating circuit. 3. An output terminal for supplying a bias potential to a bit line of a semiconductor memory; a first transistor, one end of a current path of which is connected to a first potential, and which is turned on in response to a control signal; When one end of the path is connected to the other end of the current path of the first transistor, the other end of the current path and the gate are connected to the output terminal, and the first transistor is conductive,
Second depletion type that supplies a predetermined potential to the output end
And a third transistor having one end of the current path connected to the first potential, the other end of the current path connected to the output end, and supplying a current to the output end in response to the control signal. A bias potential generation circuit comprising: 4. An output terminal for supplying a bias potential to a bit line of a semiconductor memory; a first transistor, one end of a current path of which is connected to a first potential, and which is made conductive in response to a control signal; When one end of the path is connected to the other end of the current path of the first transistor, the other end of the current path and the gate are connected to the output terminal, and the first transistor is conductive,
Second depletion type that supplies a predetermined potential to the output end
And a third transistor connected to the first potential at one end of the current path and rendered conductive in response to the control signal, and one end of the current path to the other end of the current path of the third transistor. Connected, the other end of the current path is connected to the output end, the gate is connected to the second potential, and the third transistor is conducting, the output end is lower than the predetermined potential when the output end is lower than the predetermined potential. A depletion-type fourth transistor for supplying a current to the output path, one end of the current path connected to the first potential, the other end of the current path connected to the output terminal, and the output terminal according to the control signal. A bias potential generating circuit comprising: 5. The bias potential generating circuit according to claim 2, wherein the first potential is a power source potential. 6. The bias potential generating circuit according to claim 2, wherein the second potential is a ground potential. 7. The bias potential generating circuit according to claim 1, wherein the semiconductor memory is an EPROM.