JPH0536287A - Content address system memory - Google Patents

Abstract

PURPOSE:To constitute a function equivalent to a conventional priority encoder of a smaller circuit scale by stipulating successively the address of a desired word memory for each 1 bit from a higher order bit side by a binary search. CONSTITUTION:Respective signals A3-A0 form an address signal AD in which A3 is the highest order bit and A0 is the lowest order bit, and input it to an address decoder 16. In the 0 condition, the A3 only is 1, other is 0, an access signal is outputted from an address register circuit 24 to a word line corresponding to an address signal AD (100) and a group designating signal RES of a logic Q3 is inputted from a comparing circuit 23 to a register 24. When one pulse of a clock signal CLK is inputted, the signal AD of the Q3 100 is outputted from the circuit 24 and the group designating signal RES of logic Q2 is inputted to the circuit 24. Thus, at the circuit 24, the address of the desired word memory is successively stipluated from a higher order bit side and in a condition 4, the address is obtained as Q3-Q0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Search data is input to a memory provided with a large number of word memories for storing words, and a word memory in which digital data having a bit pattern matching all or a predetermined part of the search data is stored is searched. Content addressable memory with functions (Conte
nt Addressable Memory, associative memory; Associative Memory).

[0002]

2. Description of the Related Art Recently, a content addressable memory having a search function as described above has been proposed. FIG. 4 is a circuit block diagram showing an example of a conventional content addressable memory.

In the content addressable memory 10, word memories 11a, 11b, ...
A memory 11 including a large number of 11f (here, only 6 for simplicity) is provided. The content address memory 10 also includes a search data register 12 into which one word of search data is input and latched, and a mask register 13 that determines which bit of the search data latched in the search data register 12 is used for the search. Of the search data latched in the search data register 12, the bit pattern of only the bit portion corresponding to the logic “0” of the mask data latched in the mask register 13 and each word memory 11a in the memory 11 are provided. , 11
Of the data stored in b, ..., 11f, the match / mismatch with the bit pattern of only the bit portion corresponding to the logic '0' of the mask data latched in the mask register 13 is compared, and the word memory 11a, 11b, ..., 1
Of the search result flag lines 14a, 14b, ..., 14f provided corresponding to 1f, the search result flag lines 14a, 14b, ..., 14f for the memories 11a, 11b ,. '
1 ', other search result flag lines 14a, 14b,
A matching signal of logic "0" is output to 14f.

Here, each flag line 14a, 14b, ...
14f are logical "0", "1", "0", "
It is assumed that a match signal of 0 ',' 1 ', and' 0 'is output. This match signal is input to the priority encoder 15, and a search result flag line (here, the search result flag line 14b and the search result flag line 14 here) to which the match signal of logic "1" is output from this priority encoder 15.
The address signal corresponding to the highest priority search result flag line having the highest priority of the two (e) is output. Here, it is assumed that the lower the alphabet of the subscript is, the higher the priority is. Therefore, the search result flag line 14b is the highest priority search result flag line here. The highest priority search result flag line 14 output from the priority encoder 15
The address signal AD corresponding to b is the address decoder 1
6 is input. The address decoder 16 decodes the input address signal AD to decode each word memory 1
, 17f provided corresponding to each of 1a, 11b, ..., 11f, any one of the word lines (here, word line 17b) ) To an access signal (here, a signal of logic "1"). As a result, the data stored in the word memory 11b corresponding to the word line 17b to which the access signal is output is read by the read data register 18 and latched.

As described above, the content addressable memory 10
Searches the contents (data) stored in the memory 11 by using all or a predetermined part of the search data,
It is a memory that can obtain the address of a word memory having matching data and read the entire data stored in the word memory.

[0006]

In the content-address type memory 10 configured as described above, when the number of word memories 11a, 11b, ..., 11f forming the memory 11 is large, the circuit scale becomes very large. Since a large priority encoder 15 is required, it is difficult to construct a content addressable memory having a large memory capacity. For example, when the memory capacity is 8 K words, it is known that the circuit scale of the priority encoder is, for example, about 30% of the circuit scale of the entire content address memory.

In view of the above circumstances, it is an object of the present invention to provide a content addressable memory having a circuit that realizes the same function as the priority encoder with a circuit scale smaller than the conventional one.

[0008]

The contents addressable memory of the present invention for achieving the above object is (1) a memory provided with a number of word memories for storing one word of digital data, and (2) search data. Of the result flag lines provided corresponding to each of the word memories, the search corresponding to the word memory storing the bit pattern that matches all or a predetermined part of the bit pattern of the search data. A search circuit for outputting a match signal to the result flag line, (3) An address of the memory is input, and a word line corresponding to the input address of the word lines provided corresponding to each of the word memories is accessed. An address decoder that outputs a signal, (4) is connected to the search result flag line and the word line, and connects the word memory The highest priority among the search result flag lines outputting the coincidence signal when divided into two word memory groups in the address order with the address of the word memory corresponding to the word line outputting the access signal as a boundary A comparison circuit that outputs a group designation signal that designates a word memory group to which the word memory that corresponds to a high-priority search result flag line belongs. (5) The group designation signal is input and the address of the memory is set. An address register is provided, which outputs and inputs to the address decoder to sequentially determine the bit pattern representing the address of the word memory corresponding to the highest priority search result flag line from the upper bit side of the bit pattern by the binary search method. It is characterized by that.

Here, the above-mentioned "binary search method" designates one of the divided word memory groups, divides the designated word memory group further into two, and divides this further divided word into two. This is a search method in which one of the memory groups is specified, and ... This is repeated in sequence to finally specify the target word memory.

[0010]

The content addressable memory of the present invention has the above (1).
To (5), especially the comparator circuit of (4) above and the address register of (5) above, for example, in the central word memory that constitutes the memory from the address register. Address signal 1000 ...... 0
Is output to determine which of the word memory groups divided into two by this address contains the desired word memory corresponding to the highest priority search result flag line, the logic Q _n of the most significant bit of the address is determined. Then, the address signal Q with the most significant bit being logic “Q _n ”, the next bit being logic “1”, and the other bits being logic “0” from the address register.
_n 100 ... 0 is output and any one of the word memory groups obtained by further _dividing the word memory group whose most significant bit corresponds to the logic Q _n among the two divided word memory groups is the desired word memory. , The logic Q _n-1 of the next bit is determined, and this is repeated to determine the address Q _n Q of the desired word memory.
_n-1 Q _n-2 ... Q ₁ is defined, and thereby a function equivalent to that of the priority encoder 15 provided in the conventional content addressing memory 10 described above is realized.

Next, the circuit scale of the priority encoder 15 provided in the conventional content address type memory 10 and the circuit scale of the portion corresponding to the priority encoder 15 provided in the content address type memory of the present invention will be described. Compare. In the conventional priority encoder 15, a circuit is configured by logically compressing from a truth table. On the other hand, in the present invention, when the number of word memories is N, the circuit scale S is, for example, S = 5. N (comparator circuit) + 14log ₂ N (address register) (1)

When N = 16 is compared with each other, it is estimated that the conventional priority encoder has about 40 gates (1 gate is estimated to be equivalent to a 2-input NAND gate, and a multi-input OR circuit is estimated to use a wired OR circuit). On the other hand, in the present invention, S = 192 (gate) (2), and in the case of a very small content addressable memory such as N = 16, the conventional priority encoder is It can be realized with a small circuit scale.

Next, comparing N = 1024 with each other, even if it is assumed that the logical compression ratio is the same as in the case of N = 16 in the conventional priority encoder, S = 6.4K (gate) (3) Becomes Actually, when N = 1024, the same logical compression as in the case of N = 16 is impossible.
Actually, the circuit becomes larger than the above equation (3).
On the other hand, in the case of the present invention, S = 5.3K (gate) (4). As described above, the present invention is more advantageous when the memory capacity is increased up to about N = 1024, and this difference is further widened when N is further increased.

As described above, the present invention realizes a content addressable memory having a smaller circuit scale than the conventional one, except for a very small content addressable memory.

[0015]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a block diagram showing a content addressable memory according to an embodiment of the present invention. In this figure, the components corresponding to the components of the conventional example (see FIG. 4) described above are given the same numbers and symbols as those shown in FIG. 4, and only the differences will be described.

The content addressing memory 20 is provided with a search result register 21, and the coincidence signals output to the search result flag lines 14a, 14b, ..., 14f are input to the search result register 21. It is latched in the search result register 21 during the operation for specifying the desired word memory address shown in FIG. This latched match signal is used as the search result flag lines 22a, 22b,
, 22f and is input to the comparison circuit 23. Further, word lines 17a, 17b, ..., 17f connected to the address decoder 16 are also connected to the comparison circuit 23, whereby the access signal output from the address decoder 16 is also input to the comparison circuit 23. .. This comparison circuit 23 outputs a group designation signal RES indicating which one of the word memory groups divided into two by the word line to which the access signal is output belongs to the desired word memory by the circuit configuration described later. It is a thing. The group designation signal RES is input to the address register 24. The address register 24 has a circuit configuration described later,
First, an address signal corresponding to the central word memory among the large number of word memories 11a, 11b, ..., 11f is output, and the group designation signal RES output from the comparison circuit 23 is checked thereby to find the desired word memory. By recognizing which group it belongs to, then outputting the address signal AD so as to further divide the group to which the desired word memory belongs, and repeating this a necessary number of times to finally obtain the desired word memory. It is a circuit that generates an address signal corresponding to a memory. When the address signal AD corresponding to the desired word memory is generated by the address register 24, the address signal AD is generated by the address decoder 1.
6, the access signal is output to the word line corresponding to the desired word memory, and the data stored in the desired word memory is read to the read data register 18.

The circuit configurations of the comparison circuit 23 and the address register 24 shown in FIG. 1 will be described below. Figure 2
FIG. 3 is a circuit diagram of the comparison circuit 23 shown in FIG. However,
For simplicity, only four word memories are shown here. A search result flag line 22a connected to the search result register 21 for outputting a match signal after latching,
From 22b, 22c, 22d, ... For example, here, as shown in the figure, logics “0”, “0”, “1”,
The coincidence signal of "1", ... Is input to the highest priority flag detection circuit 23a of the comparison circuit 23.

The highest priority flag detection circuit 23a is constructed so that the priority levels are lowered in the order of the detection result flag lines 23a, 23b, 23c, 23d, ... It is a circuit that selects and outputs the one with the highest priority (referred to as the highest priority flag). Here, the match signal of logic "1" is output from the search result flag lines 22c and 22d. Therefore, here, the match signal from the search result flag line 22c becomes the highest priority flag, and the output of the highest priority flag detection circuit 23a. Of the lines, the signal of logic "1" is output only to the output line corresponding to the detection result flag line 22c.

Each output line and word line 17a, 17b, 17c, 17 of this highest priority flag detection circuit 23a.
.. are input to the address comparison circuit 23b. The address comparison circuit 23b has an address of the word memory corresponding to the highest priority flag and an access signal (logic "1").
Is a circuit that detects which of the addresses of the word memory corresponding to the output word line is the young address, and here, if any of the word lines 17a, 17b, and 17c is logic "1", , A signal of logic "1" is output to the output line corresponding to the highest priority flag, and if either the word line 17d or a word line (not shown) lower than the word line 17d is logic "1", this address comparison is performed. All the output lines of the circuit 23b are logic "0".

The output line of the address comparison circuit 23b is input to the group detection circuit 23c. This group detection circuit 2
3c includes a first word memory group consisting of a word memory having a smaller address side than the word memory corresponding to the word line to which the logic '1' signal is output, and the other logics. When divided into a second word memory group including a word memory including a word memory corresponding to the word line to which the signal of "1" is output, the desired word memory corresponding to the highest priority flag is This is a circuit for detecting whether or not it belongs to the group, and if any one of the output lines of the address comparison circuit 23b has a logic "1", the desired word memory corresponding to the highest priority flag is the second word. When the group designation signal RES of logic "1" indicating that it belongs to the word memory group is output and all the output lines of the address comparison circuit 23b are logic "0", the desired word memory is the upper memory. A group designation signal R of logic "0" indicating belonging to the first word memory group
ES is output.

FIG. 3 is a circuit diagram of the address register circuit 24 shown in FIG. Here, it is assumed that the address is represented by a 4-bit signal. Further, the address register 24 will be described here by being divided into a first half portion 24a and a second half portion 24b. First, in the first half 24a, the initial setting signal I
When NIT is input, the flip-flop 25a at the top of the figure is preset and its output signal S3 is logic '.
1 ', and with this, another flip-flop 2
5b, 25c and 25d are reset so that their output signals S2, S1 and S0 become logic "0". This state is set to the state “0”, and every time one clock pulse of the clock signal CLK is input, the state 1 is set as shown in Table 1.
(Only S2 is logic '1') → State 2 (S1 only is logic ')
1 ′) → state 3 (only S0 is logic “1”) → state 4 (all logic “0”).

[0022]

[Table 1] ─────────────────────────────────── Status S3 S2 S1 S0 0 1 1 0 0 0 1 0 1 0 0 2 0 0 1 1 0 3 0 0 0 1 1 4 0 0 0 0 0 ──────────────────────────────── In the latter half 24b, all the flip-flops 26a, 26b, when the initial setting signal INIT is input,
26c and 26d are reset and each flip-flop 2
6 ', 26b, 26c, 26d's Q output terminals are logical
A signal of 0'is output. Each multiplexer 27a, 2
7b, 27c and 27d are input signals on the "1" side shown in FIG. 2, that is, shown in FIG. 2 when the signals S3, S2, S1 and S0 input to the respective select terminals are logic "1" signals. The group designation signal RES output from the comparison circuit 23 is
The corresponding flip-flops 26a, 26b, 26c,
When the signals S3, S2, S1 and S0 output to the D input terminal of 26d and input to each select terminal are signals of logic "0", the input signal on the "0" side shown in the figure, that is, The corresponding flip-flops 26a, 26b, 26c,
The signal output from the Q output terminal of 26d is directly output to the D input terminals of the flip-flops 26a, 26b, 26c and 26d. The signals output from the Q output terminals of the flip-flops 26a, 26b, 26c and 26d and the flip-flops 25 of the first half 24a.
The signals S3, S2, S1, and S0 output from the Q output terminals of a, 25b, 25c, and 25d are the corresponding two inputs O.
Input to the R gates 28a, 28b, 28c, 28d,
Each of these two-input OR gates 28a, 28b, 28c,
From 28d, the signals A3, A2, A1, A0 shown in Table 2 are shown.
Is output. In Table 2, Q3, Q2, Q1, Q0
Represents the logic level of the group designation signal RES in each state.

Here, each of the signals A3, A2, A1 and A0 forms an address signal AD (see FIG. 1) having A3 as the most significant bit and A0 as the least significant bit as a whole of these signals. Signal AD is address decoder 1
6 (see FIG. 1).

[0024]

[Table 2] ─────────────────────────────────── Status A3 A2 A1 A0 0 1 0 0 0 1 Q ₃ 1 0 0 2 Q ₃ Q ₂ 1 0 3 Q ₃ Q ₂ Q ₁ 1 4 Q ₃ Q ₂ Q ₁ Q ₀ ────────────────────── ────────────── As shown in Table 2, first, in state 0 (the state immediately after the initial setting signal INIT is input), only the most significant bit (A3) is Logic '1', other bits (A2, A
1, A0) is a logic “0”, and the address signal AD “1000” is output from the address register circuit 24 and input to the address decoder 16, whereby the word corresponding to the address “1000” is output from the address decoder 16. The access signal is output to the line, and the group specifying signal RES of the logic Q3 indicating whether the address of the desired word memory corresponding to the highest priority flag is less than "1000" or is "1000" or more is output from the comparison circuit 23. It is input to the address register circuit 24. At this stage the clock signal C
When one LK clock pulse is input, the state shifts to state 1 and this address register circuit 24 now outputs "Q ₃
The address signal AD of "100" is output, and thereby the group designation signal RES of logic Q ₂ is input to the address register circuit 24.

As described above, in the address register circuit 24, the address of the desired word memory corresponding to the highest priority flag is sequentially determined from the upper bit side, and in state 4, the desired word memory address is " is obtained as Q ₃ Q ₂ Q ₁ Q ₀ ". Here, in the above-described embodiment, a bit pattern that matches the portion of the search data latched in the search data register 12 that is not masked by the mask register 13 (the data portion used for the search) is stored in the memory 11. If there is no stored word memory 11a, 11b, ..., 11f, that is, the search result flag line 14
When a signal of logic "0" is output to all of a, 14b, ... 14f, when the address is obtained by the address register circuit 23 as described above, the obtained address is "0".
000 ”, which makes it indistinguishable from the case where desired data is stored in the word memory at address“ 0000 ”, but the word memory at address“ 0000 ”virtually exists and does not actually exist. Or the word memory at address "0000" is not used even if it actually exists, or after the contents of the word memory at address "0000" are read into the read data register 18, This inconvenience can be avoided by verifying the contents.

Needless to say, the present invention is not limited to the above-mentioned embodiment, and various circuits can be constructed.

[0027]

As described above, in the content addressing type memory of the present invention, the address of the desired word memory is sequentially determined bit by bit from the upper bit side by the binary search method. The function equivalent to can be configured with a smaller circuit scale.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a content addressable memory according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a comparison circuit shown in FIG.

FIG. 3 is a circuit diagram of the address register circuit shown in FIG.

FIG. 4 is a circuit block diagram showing an example of a conventional content addressable memory.

[Explanation of symbols]

 10 content address type memory 11 memory 11a, 11b, ..., 11f word memory 12 search data register 13 mask register 14a, 14b, ..., 14f search result flag line 15 priority encoder 16 address decoder 17a, 17b, ..., 17f word line 18 Read data register 20 Content addressable memory 21 Search result register 22a, 22b, ..., 22f Search result flag line 23 Comparison circuit 24 Address register circuit

Claims (1)

Claim: What is claimed is: 1. A memory provided with a large number of word memories for storing one word of digital data, and a result flag line to which search data is input and provided corresponding to each of the word memories. A search circuit that outputs a match signal to a search result flag line corresponding to the word memory that stores a bit pattern that matches all or a predetermined part of the search data, and an address of the memory And an address decoder that outputs an access signal to a word line corresponding to an input address among word lines provided corresponding to each of the word memories, and connected to the search result flag line and the word line,
The search result flag in which the coincidence signal is output when the word memory is divided into two word memory groups in the order of address with the address of the word memory corresponding to the word line to which the access signal is output as a boundary A comparison circuit that outputs a group designation signal that designates the word memory group to which the word memory corresponding to the highest priority search result graph line of the line belongs; Address is output to the address decoder, and a bit pattern representing the address of the word memory corresponding to the highest priority search result flag line is sequentially determined by the binary search method from the upper bit side of the bit pattern. A content addressable memory comprising a register.