JPH05347641A - Transmission reception circuit for digital system cellular telephone system - Google Patents

Abstract

PURPOSE:To attain miniaturization, light weight and to reduce power consumption by using a clock used for a delay detection circuit in common for a clock system of a modulated signal for an orthogonal modulator. CONSTITUTION:A signal of a clock signal source 3 used for a delay detection circuit 2 is subject to frequency division by a frequency divider 11 being a component of a processing circuit section in the transmission reception circuit having the delay detection circuit 2 and an orthogonal modulator 1 used for the digital system cellular telephone system and the result is used for a modulated signal of the orthogonal modulator 1. Since the same clock system is used in common, number of oscillating circuits is reduced and miniaturization, light weight and reduction in power consumption are attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitter / receiver circuit, and more particularly to a transmitter / receiver circuit for a digital cellular telephone.

[0002]

2. Description of the Related Art In recent years, digitization has progressed in the fields of portable telephones and car telephones. In this digital mobile / car phone, the modulator is
I (In-phase) and Q (Quadra-phase)
A quadrature modulator that inputs the baseband signal of e) is often used. An example of a conventional transmission / reception circuit having a quadrature modulator of this type will be described with reference to FIG. In FIG. 3, reference numeral 1 is a quadrature modulator, and mixer circuits 21, 22 and π / 2
It is composed of a phase shifter 23 and an adder circuit 24. Reference numeral 2 is a delay detection circuit, 3 is a clock signal source, 4 is a baseband signal waveform generation circuit, and 6 is a local signal source.

Then, the I signal and Q from the waveform generating circuit 4
The mixer circuit 22 and the mixer circuit 21 to which a signal is respectively input, and π are input to each of the mixer circuits 22 and 21.
In the quadrature modulator 1 including the π / 2 phase shifter 23 for inputting a signal whose phase is shifted by / 2 and the adder circuit 24 for adding and outputting the outputs of the mixer circuits 22 and 21, the π / 2 phase shifter is used. It was supplied from the local signal source 6 as an input of 23. Further, if the delay detection circuit 2 that creates a delay by using a D-type flip-flop is adopted as the detection circuit, the clock signal source 3 has a frequency N times (N: an integer) the intermediate frequency (IF). .. MOD OUT indicates a modulation output signal, IF IN
Indicates an intermediate frequency input signal. For example, if the IF frequency is 45
If the frequency is 5 KHz and N = 64, the frequency of the clock signal source 3 is 29.12 MHz. On the other hand, the local signal source 6 for transmission requires a transmission carrier frequency, for example, a high frequency signal in the 900 MHz band in the case of direct modulation. Here, in the quadrature modulator operating at high frequency, π / 2
The phase shifter 23 requires considerable power consumption.

[0004]

In the conventional transmission / reception circuit including the differential detection circuit and the quadrature modulator, the clock signal source for the delay detection circuit and the local signal source of the quadrature modulator are different, and the frequency of the local signal source is different. There is a problem that the frequency becomes high, a large amount of power supply current is consumed, and the mobile phone has a short talk time. Even if the local signal source has a low frequency, if the frequency is different from the frequency of the clock signal source, 2
Since there are two signal sources, there is a problem in that it is disadvantageous in downsizing and weight reduction.

[0005]

A transmission / reception circuit of a digital cellular telephone according to the present invention is a transmission / reception circuit comprising a delay detection circuit, a clock signal source for this delay detection circuit, and a quadrature modulator. It is provided with a means for supplying a modulated signal from an output obtained by processing the clock signal source.

[0006]

In the present invention, a signal obtained by performing simple signal processing such as frequency division on the clock signal source used in the differential detection circuit of the receiving system is used as the modulated signal of the quadrature modulator of the transmitting system.

[0007]

1 is a block diagram showing an embodiment of a transmitting / receiving circuit of a digital cellular telephone according to the present invention. In FIG. 1, the same reference numerals as those in FIG. 3 indicate corresponding parts, and 5 is a processing circuit section, which supplies the modulated signal of the quadrature modulator 1 from the output obtained by processing the clock signal source 3. Constitutes a means.

In the receiving system, there is a delay detection system among the detection circuits to which the intermediate frequency amplified intermediate frequency input signal IF IN is input. In this delay detection circuit 2, however, the intermediate frequency f _IF N times as many clock signal sources 3 are required. On the other hand, in the transmission system, when the quadrature modulator 1 using the I and Q signals outputted from the waveform generating circuit 4 for producing a signal which is differentially encoded and processed is used as a modulation signal, the quadrature modulator 1 receives a signal. As the modulation signal, a signal obtained by dividing the signal of the clock signal source 3 by the processing circuit unit 5 is used. With such a configuration, by making the signal source part common, the number of oscillators that occupy many places and are heavy can be reduced, so that the size and weight can be reduced. In terms of frequency, the intermediate frequency f
By using a frequency equal to or lower than the signal N times the _IF , it is possible to reduce the current consumption when the LSI is used.

FIG. 2 is a block diagram showing a circuit configuration example in which the block diagram shown in FIG. 1 is specifically implemented. This Figure 2
In FIG. 3, the same parts as those in FIGS. 1 and 3 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 2, 11 is a frequency divider, and 12
Is the received input signal (RX IN) and the received local signal (R
X LO) as an input, a receiving mixer section 13 has an intermediate frequency filter (bandpass filter) 13 having an output of the receiving mixer section 12 as an input, and 14 has an intermediate frequency having an output of the intermediate frequency filter 13 as an input. An amplifier, 15 is a transmission filter (bandpass filter) that receives the output of the quadrature modulator addition circuit 24, and 17 is this transmission filter 15
The output mixer and the transmission local signal (TX LO) are input, and the transmission mixer outputs the transmission output signal (TX OUT).

Next, the operation of the embodiment shown in FIG. 2 will be described. First, the reception system (RX) receives the reception input signal (RX
IN) and the reception local signal (RX LO) are input to generate a signal in the intermediate frequency band in the reception mixer unit 12, and the intermediate frequency signal is amplified by the bandpass filter which is the intermediate frequency filter 13 and the intermediate frequency amplifier 14. (IF signal) is generated and input to the differential detection circuit 2. And
The delay clock signal source 3 of the differential detection circuit 2 is an IF
If the frequency of the signal is 455 KHz and N = 64, the frequency is 29.12 MHz.

On the other hand, in the transmission system (TX), the I generated by the waveform generation circuit 4 after processing such as differential encoding is performed.
A signal and a Q signal are input to the I and Q inputs of the quadrature modulator 1, and the modulated signal is supplied from the clock signal source 3 used in the differential detection circuit 2 via the frequency divider 11. Next, assuming that the frequency division ratio is 16, 1.82 MHz is output from the output of the frequency divider 11, and π / 2 in the quadrature modulator 1 is output.
Enter the phase shifter 23. Here, the modulated frequency supplied to the mixer circuits 21 and 22 inside the quadrature modulator 1 is 4
55KHz, if there is a 1.82MHz clock, π
/ 2 phase shift with phase divider π /
It can be shifted by 2 and can be easily integrated into an LSI. Then, from the output of the quadrature modulator 1, in this case, 455 KHz
The signal modulated by is output, and then the bandpass filter which is the transmission filter 15 can be made to have a roll-off characteristic.

[0012]

As described above, according to the present invention, a signal obtained by performing simple signal processing such as frequency division on a clock signal source used in a differential detection circuit of a receiving system is used as a modulated signal of a quadrature modulator of a transmitting system. As a result, the number of oscillators can be reduced. Further, when the block including the differential detection circuit and the quadrature modulator is to be an LSI, a CMOS (complementary M
OS FET) can be adopted, and quadrature modulation is not applied at a frequency that is very high in terms of frequency. Therefore, power consumption can be extremely reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a transmitting / receiving circuit of a digital cellular telephone according to the present invention.

FIG. 2 is a block diagram showing a circuit configuration example in which the block diagram shown in FIG. 1 is specifically implemented.

FIG. 3 is a block diagram showing an example of a transmission / reception circuit having a conventional quadrature modulator.

[Explanation of symbols]

 1 Quadrature modulator 2 Delay detection circuit 3 Clock signal source 4 Waveform generation circuit 5 Processing circuit section 11 Frequency divider

Claims (1)

[Claims] 1. A transmission / reception circuit comprising a differential detection circuit, a clock signal source for the differential detection circuit, and a quadrature modulator, and means for supplying a modulated signal of the quadrature modulator from an output obtained by processing the clock signal source. A transmitter / receiver circuit for a digital cellular telephone, which is characterized by being provided.