JPH05346935A - Device and method for matrix data multiplication - Google Patents

Abstract

PURPOSE:To provide the matrix data multiplying device which can perform matrix multiplication and its transposed matrix multiplication by using the same circuit and same matrix data. CONSTITUTION:Unit arithmetic circuits 110 each consisting of a holding circuit 10 which holds serial input data as many as the dimensions of the matrix, a multiplying circuit 50 which multiplies the input by matrix data, and an adding circuit 70 which cumulatively adds the multiplication result of the precedent stage or its multiplication result are provided as many as the dimensions of the data matrix. At first, the unit arithmetic circuit 110 inputs the input data to the holding circuit 10 or multiplying circuit 50 according to a selection signal. Then the multiplication result of the precedent stage or its own addition result is selectively inputted to the adding circuit 70. By this selection, the input/output relation of the unit arithmetic circuit 110 can be changed between the relation for the matrix multiplication of the input or its transposed matrix multiplication of the input. With the selection signal, the output of a parallel/serial converting circuit 80 or the output of the register 63 of a final stage is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix data multiplication device in digital signal processing, and more particularly to a discrete cosine transform (DCT).
And an inverse discrete cosine transform (IDCT) computing device.

[0002]

2. Description of the Related Art Input data I0, I1, I2 and I3 are n
Output data Y0, Y1, as a result of the operation of Equation 1 being input bit-parallel sequentially in time order (serial)
A device configuration shown in FIGS. 7 and 8 is known as a device configuration in which Y2 and Y3 are sequentially output serially in parallel in n bits.

[Equation 1]

(Description of Operation of Device Configuration of Device 2) FIG. 7 is a diagram showing a configuration of a conventional matrix data multiplication device 2. The operation of the matrix data multiplication device 2 having the circuit configuration shown in FIG. Registers 60 and 6 in FIG.
1, 62, 63 are input data I0, I1, I2, I3
Initialized (cleared) before input of. After that, the input data I0, I1, I2, and I3 synchronized with the operation cycle signal 100 at the timings shown in FIG.
Serial inputs are sequentially input to 0, 51, 52, and 53. At the same time, the coefficient data “A” is stored in the multiplication circuits 50, 51, 52, 53 from the memories 41, 42, 43, 44, respectively.
0-A3 "," B0-B3 "," C0-C3 "," D0
To D3 "are read out. The coefficient data" A0 to A3 "and" B0 to B "read out from the coefficient memories 40 to 43, respectively.
3 ”,“ C0 to C3 ”, and“ D0 to D3 ”are respectively I
0 to I3 are multiplied in the multiplication circuits 50, 51, 52 and 53. These calculation results are respectively added to the adder circuit 70.
And register 60, adder circuit 71 and register 61, adder circuit 72 and register 62, and adder circuit 73 and register 63.
Y3 is calculated. Y0 to Y calculated by each cumulative addition circuit
3 is serial-converted by a parallel / serial conversion circuit (parallel / serial conversion circuit) 80 and output.

In this case, in the calculation, the memory 40 stores A0, A1, A2, A3, the memory 41 stores B0, B1, B2, B3, and the memory 42 stores C0, C1, By storing C2 and C3 and storing D0, D1, D2 and D3 in the memory 43, matrix calculation can be performed.
0, B0, C0, D0 are stored, and A is stored in the memory 41.
1, B1, C1, D1 are stored, and A is stored in the memory 42.
2, B2, C2, D2 are stored, and A is stored in the memory 43.
By storing 3, B3, C3, D3, the transposed matrix of the constant matrix of Expression 1 can be calculated. Therefore, when performing multiplication by a constant matrix and multiplication by its transposed matrix by one matrix data multiplication device, A0, A1, A2, A3, B0, C0, D0 are stored in the memory 40, and the memory 41 is stored in the memory 41. , B0, B1, B2, B3, A
1, C1, D1 are stored, and C0, C are stored in the memory 42.
1, C2, C3, A2, B2, D2 are stored, and D0, D1, D2, D3, A3, B3, C3 are stored in the memory 43.
Will need to be stored.

(Description of Operation of Device Configuration of Device 3) FIG. 8 is a diagram showing a configuration of a conventional matrix data multiplication device 3. The operation when the calculation of Expression 1 is performed with the device configuration of FIG. 8 is as follows. The hold circuits 10, 11, 12, and 13 in FIG.
The input data I0, I1, I2, and I3 are cleared prior to input. After that, at the timing shown in FIG. 3, the input data I0, I1, I2, and I3 are transferred to the hold circuit control signal 94.
As a result, the holding circuits 10, 11, 12, 13 are held for four operation cycles. Further, at the timing shown in FIG. 2, the coefficient data “A” is supplied from the memories 44, 45, 46, 47 to the multiplication circuits 51, 52, 53, 54, respectively.
0, B0, C0, D0 "," A1, B1, C1, D
1 "," A2, B2, C2, D2 "," A3, B3, C
3, D3 "is read out. The coefficient data" A0, B0, C0, D0 "," A1, "read out from each coefficient memory.
B1, C1, D1 "," A2, B2, C2, D2 ",
“A3, B3, C3, D3” and the input data I0 to I3 held in the hold circuits are multiplied by the multiplication circuits 50, 51, 52,
It is multiplied at 53. These calculation results are added by the adder circuits 70, 71, 72 and 73, respectively, but since they are respectively passed through the registers 60, 61, 62 and 63, the multiplication results shifted by one operation cycle signal are added,
As a result, Y0 to Y3 are serially output.

In this case, in the calculation, A0, B0, C0, D0 is stored in the memory 44, A1, B1, C1, D1 are stored in the memory 45, and A2, B2 is stored in the memory 46. Matrix calculation can be performed by storing C2, D2 and A3, B3, C3, D3 in the memory 47.
0, A1, A2, A3 are stored, and B is stored in the memory 45.
0, B1, B2, B3 are stored, and C is stored in the memory 46.
0, C1, C2, C3 are stored, and D is stored in the memory 47.
By storing 0, D1, D2, D3, the transposed matrix of the constant matrix of Expression 1 can be calculated. Therefore, when performing multiplication by a constant matrix and multiplication by its transposed matrix in one matrix operation device, the matrix data multiplication device 3
The memory 44 is the same as that shown in the explanation of the operation of the device configuration of
A0, A1, A2, A3, B0, C0, D0 are stored in the memory, and B0, B1, B2, B3, A are stored in the memory 45.
1, C1 and D1 are stored, and C0 and C are stored in the memory 46.
1, C2, C3, A2, B2, D2 are stored in the memory 47, and D0, D1, D2, D3, A3, B3, C3 are stored in the memory 47.
Will need to be stored.

Next, a case will be described in which the discrete cosine transform (DCT) and its inverse, the inverse discrete cosine transform (IDCT), are calculated by the above matrix data multiplication circuit. Calculation of DCT

[Equation 2] And the inverse transformation, IDCT calculation

[Equation 3] Is the case. However, in the equations 2 and 3, E = cos (2π / 8), F = cos (1π / 8), G = cos (3π / 8) ...

(Conventional Example in which Calculation of DCT / IDCT is Performed by Matrix Data Multiplier 2) When the calculation of DCT (Equation 2) is performed by the conventional matrix data multiplier 2, each constant in Equation 1 is set to A0. = E, A1 = E, A2 = E, A3 = E B0 = F, B1 = G, B2 = -G, B3 = -F C0 = E, C1 = -E, C2 = -E, C3 = E D0 = G, D1 = -F, D2 = F, D3 = -G ... It can be calculated by considering as Formula 5. That is,
E is stored in the memory 40,
F, G, -F, -G are stored in the memory 41,
The memory 42 stores E, −E,
By storing F, G, -F, -G in the memory 43, the DCT calculation (formula 2) can be performed by the conventional matrix data multiplication device 2.

When the IDCT calculation (formula 3) is performed by the conventional matrix data multiplication device 3, the constants in formula 1 are set to A0 = E, A1 = F, A2 = E, A3 = GB0 = E, B1. = G, B2 = -E, B3 = -F C0 = E, C1 = -G, C2 = -E, C3 = F D0 = E, D1 = -F, D2 = E, D3 = -G ... Formula It can be calculated by considering 6. That is,
The memory 40 stores E, F, G, the memory 41 stores F, G, -F, -G, and the memory 42 stores E, F, -E, -G. In the memory 43, E, -F, -G
By storing IDCT, the IDCT calculation (formula 3) can be performed by the conventional circuit (FIG. 7). Therefore, the memory 40 stores E, F, G, and the memory 41 stores E, F, G, -E, -F,
-G is stored, and the memory 42 stores E, F, -E,-.
G is stored and the memory 43 stores E,
By storing F, G, -F, -G, DCT and IDCT operations can be performed.

(Conventional example in which calculation of DCT / IDCT is performed by the circuit of FIG. 8) When calculation of DCT (formula 2) is performed by the conventional device 3, the memory 4 is considered in the same manner as the circuit of FIG.
4 stores E, F, G, memory 45 stores F, G, -E, -F, and memory 46 stores E, F, -E, -G. By storing E, −F, and −G in 47, the DCT calculation (formula 2) can be performed.

When the IDCT calculation (formula 3) is performed by the matrix data multiplication device 3, E is stored in the memory 44 and F is stored in the memory 45 in the same manner as in the matrix data multiplication device 2. , G, -F, -G
And the memory 46 stores E, −E
And the memory 47 stores E, G, -F, -G
By storing, the IDCT can be calculated (Equation 3). Therefore, like the circuit of FIG.
The memory 44 stores E, F, G
And the memory 45 stores E, F, G, −E, −.
F, −G is stored, and the memory 46 stores E, F, −.
E, −G are stored, and in the memory 47,
By storing E, F, G, -F, -G, DCT and IDCT operations can be performed.

[0012]

There is a demand that a single arithmetic unit should perform a calculation such as a DCT and IDCT operation which involves multiplication of a constant matrix and multiplication of its transposed matrix. For example, 4 × 4. In the case of the constant matrix of, the number of data required to multiply one of the constant matrix and its transposed matrix is 16, whereas when the multiplication of the constant matrix and its transposed matrix is performed by one arithmetic unit, Needs to store 28 pieces of data in the memory. Similarly, even in the case of DCT or IDCT operation using a 4 × 4 constant matrix, if only one of the multiplications is performed, the required data is 11, but in order to perform both multiplications, It is necessary to store 18 pieces of data in the memory, which causes a problem that the memory becomes too large. This problem becomes particularly important when performing multiplication that handles floating-point data in which the number of bits of constant data is larger than that of integer data. The present invention has been made in view of the above problems of the conventional technique, and constant matrix multiplication and its transposed matrix multiplication can be performed by the same device,
Moreover, it is an object of the present invention to provide a constant matrix and its transposed matrix data multiplication device in which the size of the memory for storing constant data does not increase as compared with a multiplication device that performs only constant matrix multiplication or a transposed matrix operation thereof. And

[0013]

In order to achieve the above object, a matrix data operation circuit of the present invention has a data holding circuit for holding input data of a corresponding order by the order and sequentially outputting it, and a selection signal. Depending on the above input data,
A selector circuit that selectively outputs the held data from the data holding circuit, a coefficient holding circuit that holds a coefficient of an order corresponding to the order of a constant matrix, an output from the selector circuit, and the coefficient holding A multiplication circuit for multiplying the coefficient from the circuit, and the data of the previous stage according to the selection signal,
Further, a unit operation circuit including a cumulative addition circuit for performing cumulative addition of the self cumulative addition result and the multiplication result of the multiplication circuit is provided in parallel for the degree, and the previous stage cumulative addition result is input to the next stage cumulative addition circuit. It is characterized by being connected as one.

[0014]

The operation of the matrix data multiplication device 1 of FIG. 1 will be described. In the matrix data multiplication device 1 of FIG. 1 according to the present invention, when the same constant matrix data as shown in FIGS. 7 and 8 is used, the input and output use transposed matrix data as constant matrix data. It includes two types of matrix data multiplication devices 2 and 3 which have an equivalent relation to the multiplication. The matrix data multiplication device 1 includes matrix data multiplication devices 2 and 3 included therein.
The internal configuration is changed and the input / output relation is changed by selecting the signal according to the application by the control signal. Therefore, the matrix data multiplication device 1 can perform multiplication by the constant matrix and its transposed matrix by the same matrix data multiplication device and the same matrix data. According to the present invention, the same matrix data multiplication device and matrix matrix that performs multiplication by a constant matrix and its transposed matrix by the same matrix data
It is possible to obtain a data multiplication device and a matrix data multiplication method. The matrix data multiplication device and matrix data multiplication method are suitable for DCT and IDCT operations.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a device configuration diagram of a matrix data multiplication device 1 according to the present invention. In FIG. 1, the hold circuit 10,
The selectors 20 and 24, the memory 30, the multiplication circuit 50, the register 60, and the addition circuit 70 form a unit arithmetic circuit 110. Other unit arithmetic circuits 111, 112, 113,
The same applies to 114. The parallel / serial conversion circuit 80, the output buffer 81, and the selector 28 form an output circuit 120. Hold circuits 10, 11, 12, 1
3 holds the input data during the operation cycle for the degree of the constant matrix from the data input. In the present embodiment, since the constant matrix is fourth-order, it is held for four operation cycles.

Selectors 20, 21, 22, 23, 24,
25, 26, 27 and 28 are controlled by the selector control signal 91 output from the matrix operation control circuit 90, and select and output one of the two inputs. Of this,
The selectors 20 to 23 are selectors for selecting input data, and when selected to the 0 side, the input signal is input to the multiplication circuits 50, 51, 52 and 53 as they are, and when selected to the 1 side, the hold circuit is operated. The input signal via the multiplication circuit 50,
Input to 51, 52, 53. Selectors 24, 25, 2
Reference numerals 6 and 27 select the data input to the adder circuits 70, 71, 72 and 73. When it is selected to the 0 side, the data input to the adder circuits 71, 72 and 73 becomes the outputs of the registers 60, 61 and 62, respectively, and when it is selected to the 1 side, the value of the register in the previous stage is added to the adder circuit 71. , 7
It is input to 2, 73. Selector 28 of output circuit 120
Selects the output of the matrix data multiplication device 1. When selected to the 0 side, the output of the matrix data multiplication device 1 is parallel /
When the data is from the serial conversion circuit 80 and is selected to be 1 side, the output of the register 63 is the matrix data multiplication device 1
Is output. At this time, the output buffer 81 outputs the output Y0,
When there is no Y1, Y2, or Y3, it is controlled by the output control signal 95 output from the matrix operation control circuit 90 and is in a high impedance state.

The memories 30, 31, 32 and 33 are memories for storing constant data. Multiplication circuits 50, 51, 52,
Reference numeral 53 multiplies the input data by the constant data stored in the memories 30, 31, 32 and 33. Registers 60 and 6
1, 62 and 63 store the results of the adder circuits 70, 71, 72 and 73. The adder circuits 70, 71, 72, 73 cumulatively add the outputs of the multiplier circuits 50, 51, 52, 53. Register 60 and adder circuit 70, register 61 and adder circuit 7
1, the register 62 and the adder circuit 72, and the register 63 and the adder circuit 73 form a set to form a cumulative adder circuit.
The parallel / serial conversion circuit 80 is an addition circuit 70, 7
The parallel data stored in 1, 72, 73 is converted to serial and output. The matrix operation control circuit 90 performs selector control, initialization control, memory control, hold circuit control and output circuit control of the matrix data multiplication device 1. The selector control signal 91 is output from the matrix operation control circuit 90, and the selectors 20, 21, 22, 23, 24, 25,
26, 27 and 28 are controlled. Initialization control signal 92
Is output from the matrix operation control circuit 90, and the register 6
0, 61, 62, 63 and hold circuits 10, 11,
Control the initialization of 12 and 13. Memory control signal 93
Is output from the matrix operation control circuit 90 and performs memory control during constant multiplication. The hold circuit control signal 94 is output from the matrix operation control circuit 90 and performs memory control during constant multiplication. The output control signal 95 controls the output circuit 120. The control signals 91 to 94 are all high-active control signals. The operation cycle signal 100 defines the timing of the operation cycle of the matrix data multiplication device 1.
The unit arithmetic circuits 110, 111, 112, 113 are function-selected by the selectors 20, 21, 22, 23, and when the selector 0 side is selected, the input data I0, I1, I
2, I3 and each row of the matrix are calculated, and the selector 1
When the side is selected, the input data I0, I1, I2, I
3 and each column of the matrix are calculated. The output circuit 120 controls the output of the multiplication result. Unless otherwise specified, each of the above circuits is composed of a digital logic circuit.

Since the matrix data multiplying apparatus 1 is configured as described above, the matrix data multiplying apparatus 1 of FIG. 1 has a 2-input 1-output selector 20, 21, 22, 23, 24, 25, 2.
By switching 6, 27 and 28 to the 0 side in conjunction with each other, it is possible to set the matrix data multiplication device 2 to have the same input / output relationship as that of the matrix data multiplication apparatus 2 of FIG. It can be set to have the same input / output relationship as the device 3.

A is stored in the memory 30 in order to perform the operation of Equation 1.
0, A1, A2, A3 are stored and B is stored in the memory 31.
0, B1, B2, B3 are stored and C is stored in the memory 32.
0, C1, C2, C3 are stored and D is stored in the memory 33.
0, D1, D2, D3 are stored and selectors 20, 21, 22, 23, 24, 25, 2 of 2 inputs and 1 output are further stored.
By setting 6, 27 and 28 to the 0 side, the same input / output relationship as that of the matrix data multiplication device 2 of FIG. 7 is set. The operation when the calculation of Expression 1 is performed with the circuit configuration of FIG. 1 is as follows. Each unit arithmetic circuit 110, 11 in FIG.
Registers 60, 61, 6 included in 1, 112, 113
2, 63 are cleared by the initialization control signal 92 before inputting the input data I0, I1, I2, I3.
After that, at the timing shown in FIG.
Input data I0, I1, I2, and I3 synchronized with 0 are arranged in n bits in parallel (n = 16) in the respective multiplication circuits 50, 51, and 5.
Serially input to 2, 53. At the same time, by the memory control signal 93, each coefficient memory 30, 31, 3
2 and 33, the coefficient data “A0 to A3”, “B0 to B3”, and “C” are supplied to the multiplication circuits 50, 51, 52, and 53, respectively.
0 to C3 "and" D0 to D3 "are read out. At this time, the memory cells 30a to 30d and the memory cell control signals 93a to 93d in the memory cell 30 of the matrix data multiplication device 1 are read.
The relationship is shown in FIG. 6A. 6A shows the details of the configuration of only the memory 30, but the memories 31, 32, and 33 have the same configuration. Coefficient data “A0 to A3”, “B0 to B3”, “C0 to C” read from each coefficient memory
3 "and" D0 to D3 "are respectively multiplied by I0 to I3 in the multiplication circuits 50, 51, 52 and 53. The calculation results are added circuit 70 and register 69, respectively.
As a result of cumulative addition, Y0 to Y3 are calculated by the cumulative adder including the adder circuit 71 and the register 61, the adder circuit 72 and the register 62, and the adder circuit 73 and the register 63.
Y0 to Y3 calculated by each cumulative adder are serial-converted by the parallel / serial conversion circuit 80 and output in parallel in n bits. That is, the memories 40, 41, 42 and 43 in the matrix calculation device of FIG.
It is equivalent to replacing with 1, 32, 33.

Next, the case of performing transposed matrix operation by the matrix data multiplication device 1 of FIG. 1 will be described. In this case, the contents of the memories 30, 31, 32, and 33 are not changed, and the selector control signal 81 causes the selectors 20 and 2 to output 2 inputs and 1 output.
By setting 1, 22, 23, 24, 25, 25, 27, 28 to the 1 side, the same input / output relationship as that of the matrix data multiplication device 3 of FIG. 8 is set. The hold circuits 10, 11, 12, and 13 included in the unit arithmetic circuits 110, 111, 112, and 113 shown in FIG.
Prior to the input of 0, I1, I2, and I3, it is cleared by the initialization control signal 92 at the same timing as shown in FIG. After that, input data I0, I1, I2, I synchronized with the operation cycle signal 100 at the timing shown in FIG.
3 is held in each of the hold circuits 10, 11, 12, and 13 for four operation cycles by the hold circuit control signals 94a to 94d. Further, at the timing shown in FIG. 3, the coefficient control memory 93 causes the coefficient memories 30, 31, 3 to be changed.
2 and 33, the coefficient data “A0 to A3”, “B0 to B3”, and “C” are supplied to the multiplication circuits 70, 71, 72, and 73, respectively.
0 to C3 "and" D0 to D3 "are read out. The coefficient data" A0 to A3 "and" B "read out from each coefficient memory.
0-B3 "," C0-C3 "," D0-D3 "and the input data I0-I3 held in the hold circuit are multiplied by the multiplication circuit 5
Multiply at 0, 51, 52, 53. These calculation results are added by the adder circuits 70, 71, 72 and 73, respectively.
Since they are passed through 62 and 63, the multiplication results shifted by one operation cycle are added, and the results Y0 to Y3 are serially output from the output circuit 120. This operation is performed by the memories 44 and 4 in FIG.
5, 46, and 47 are stored in memories 30, 31, 32, and 3, respectively.
3 and replace the contents of memory 30 with A0, B0, C
A0, A1, A corresponding to the transposed constants of 0, D0
2 and A3, and the contents of the memory 31 are changed to A1 and B
A0, A corresponding to the transposed matrix constants of 1, C1, D1
1, A2, A3, and the contents of the memory 32, A
C corresponding to the constant for the transposed matrix of 2, B2, C2, D2
0, C1, C2, C3, and the contents of the memory 33 are equivalent to D0, D1, D2, D3 corresponding to the transposed constants of A3, B3, C3, D3. As described above, the 2-input 1-output selectors 20, 2
By switching 1, 22, 23, 24, 25, 26, 27, 28, the same matrix data multiplication device 1 can perform matrix multiplication and its transposed matrix multiplication without increasing the memory amount. It should be noted that the initial input 96 is an external input when the matrix data multiplication device 1 is used in multiple layers, and in this embodiment, the signal input from this is zero.

The second embodiment of the present invention will be described below. Here, a case will be described in which the matrix data multiplication device 1 of the present invention calculates the discrete cosine transform (DCT) and its inverse, the inverse discrete cosine transform (IDCT). The calculation of DCT and the calculation of IDCT which is the inverse transform thereof are as described in the description of the conventional example. When the DCT calculation (formula 2) is performed by the matrix data multiplication device 1, first, E is stored in the memory 30, F, G, −G, and −F are stored in the memory 31, and the memory 3 is stored.
2, E and −E are stored in the memory 33.
, G, --F, F, -G are stored. Further, the selectors 20 to 28 are selected to the 0 side, and the input / output relationship is set to be equivalent to that of the matrix data multiplication device 2. Memory 30
Is set to always output E, and the memory 32 stores E, −
In order of E, −E, E, the other memories 31, 33 output the memories 30, 31, 32, in order as described above.
33 is configured to be controlled. Memories 30, 31, 32,
Memory cells 30a, 31a, 31b, 32a in 33
32d and 33a to 33d are memory cell control signals 93a.
The contents of ~ d are output at a high level. The input / output relationship of the matrix data multiplication device 1 at this time is shown in FIG. 4, and the relationship between the memory cell and the memory control signal is shown in FIG. 6B. With such settings and configurations, the selector 20 in the first embodiment is
The DCT calculation can be performed by the same operation as that described when .about.29 is selected to the 0 side. When performing the IDCT calculation, the selectors 20 to 29 are selected to the 1 side. Other configurations are the same as the DCT calculation. The input / output relationship of the matrix data multiplication device 1 at this time is shown in FIG. Selector 20-2
By selecting 9 on the 1 side, the IDCT operation can be performed by the same operation as that described in the case of selecting the selectors 20 to 29 on the 0 side in the first embodiment. Although various control signals are all high-active signals in this embodiment, they may be low-active signals if necessary in terms of circuit configuration.

In the embodiment of the present invention, the memory 30-
The constant matrix data is set in 33, the operation performed by selecting the selectors 20 to 28 on the 0 side is matrix multiplication, and the selector 20
Although the operation performed by setting ~ 28 to the 1 side is the transposed matrix operation, constant matrix data having a transposed relationship with the above matrix is set in the memories 30 to 33, and the selectors 20 to 28 are selected to the 1 side to perform the operation. The operation is matrix multiplication, and the selectors 20 to 28 are set to 0.
The calculation performed on the side may be transposed matrix multiplication. A similar relationship is the same for DCT and IDCT operations.

In the embodiment of the present invention, only the 4 × 4 matrix is described. However, unit arithmetic circuits are provided for the orders,
A matrix data multiplication device according to the present invention for a matrix multiplication of an arbitrary order can be obtained by configuring the constant data storage memory in accordance therewith and storing the constant in the constant data storage memory. This is DCT and IDC
The same applies to the T calculation. Further, each unit arithmetic circuit shown in the embodiment of the present invention can be replaced with another circuit configuration having an equivalent function. Although the input / output format is serial input / output in this embodiment, all input / output may be parallel input / output depending on the application. In the embodiment of the present invention, the input / output data is 16-bit parallel (n =
16), but n may have another value. Further, serial input / output (n = 1) may be used. Further, the bit lengths of the input and the output do not have to be the same. In the embodiment of the present invention, the input data and the coefficient data are multiplied by having the coefficient data storage memory and the multiplication circuit. However, the multiplication may be performed using a lookup table.

[0024]

As described above, according to the matrix data multiplication device of the present invention, when the constant data in the same constant storage memory are multiplied, the input / output relationship is the multiplication of the constant matrix and its transposed matrix. Since a multiplication device is built-in and they are switched by the selector to perform multiplication, constant matrix multiplication and its transposed matrix multiplication can be performed in the same circuit using one type of constant memory, and constant matrix multiplication can be performed. It is possible to obtain a matrix data multiplication device in which the constant data storage memory does not increase as compared with a matrix data multiplication device which performs only one of the transposed matrices, although it can perform both of its transposed matrices.

[Brief description of drawings]

FIG. 1 is a matrix data multiplication device of the present invention.

FIG. 2 is a diagram showing the timing of a constant matrix multiplication operation of the matrix data multiplication device 1 of the present invention and the first conventional matrix data multiplication device.

FIG. 3 is a diagram showing the timing of a transposed constant matrix multiplication operation of the matrix data multiplication device of the present invention and the second conventional matrix data multiplication device.

FIG. 4 is a diagram showing the timing of DCT calculation in the matrix data multiplication device of the present invention.

FIG. 5 is an IDCT in the matrix data multiplication device of the present invention.
It is a figure which shows the timing of calculation.

FIG. 6 is a diagram showing a memory configuration and a timing of a memory control signal in the matrix data multiplication device of the embodiment of the present invention.

FIG. 7 is a configuration diagram of a first conventional matrix data multiplication device.

FIG. 8 is a diagram showing operation timing of a second conventional matrix data multiplication device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Matrix data multiplication device of the Example of this invention 10-13 ... Hold circuit 20-28 ... Selector 30-33 ... Constant data storage memory 30a-33d ... Memory of this invention Cell 50-53 ... Multiplier circuit 60-63 ... Register 70-73 ... Adder circuit 80 ... Parallel / serial conversion circuit 81 ... Output buffer 90 ... Matrix operation control circuit 91 ... Selector control signal 92 ... Initialization control signal 93 ... Memory control signal 93a to 93d ... Memory cell control signal 94 ... Hold control signal 94a to 94d ... Hold to each hold circuit Control signal 95 ... Output control signal 96 ... External input 100 ... Operation cycle signal 110-113 ... Unit arithmetic circuit 120 ... Output circuit

Claims (4)

[Claims] 1. A data holding circuit that holds input data of a corresponding order by the order and outputs the data sequentially, and selectively outputs the input data or the held data from the data holding circuit according to a selection signal. Selector circuit, a coefficient holding circuit that holds a coefficient of an order corresponding to the order of the constant matrix, a multiplication circuit that multiplies the output from the selector circuit by the coefficient from the coefficient holding circuit, and the selection Depending on the signal, a unit arithmetic circuit including a cumulative addition circuit that performs cumulative addition of the previous stage data or the self cumulative result and the multiplication result of the above multiplying circuit is provided in parallel for the order, and the previous stage cumulative addition result is A matrix data multiplication device connected as one of the inputs of the next-stage cumulative addition circuit. 2. A data holding circuit that holds input data of a corresponding order by the order and outputs the data sequentially, and selectively outputs the input data or the held data from the data holding circuit according to a selection signal. Selector circuit, a coefficient holding circuit that holds the coefficients used for the discrete cosine transform and the inverse discrete cosine transform of the order corresponding to the order of the constant matrix, the output from the selector circuit, and the coefficient holding circuit A unit arithmetic circuit consisting of a multiplication circuit for multiplying the coefficient of and a cumulative addition circuit for performing the cumulative addition of the preceding stage data or its own cumulative addition result and the multiplication result of the multiplication circuit according to the selection signal A discrete cosine transform and inverse discrete cosine transform calculation device that is provided in parallel and that the result of the cumulative addition of the preceding stage is connected as one of the inputs of the cumulative addition circuit of the next stage. 3. The input data of a corresponding order is held by that order and sequentially output, and the input data or the held and sequentially output data is selectively output according to a selection signal, The coefficient of the order corresponding to the order of the constant matrix is held, the input data is multiplied, or the held and sequentially output data is multiplied by the coefficient, and the data of the preceding stage, or A matrix data multiplication method in which the cumulative addition result of the self and the above multiplication result are cumulatively performed, these unit operations are performed in parallel for the degree, and the cumulative addition result of the preceding stage is one of the inputs of the cumulative addition of the next stage. 4. An input data of a corresponding order is held for that order and sequentially output, and the input data or the held and sequentially output data is selectively output according to a selection signal, The coefficient used for the discrete cosine transform and the inverse discrete cosine transform corresponding to the order of the constant matrix is held, and the input data or the held and sequentially output data is multiplied by the coefficient, Depending on the selection signal, the previous stage data or its own cumulative addition result and the above multiplication result are cumulatively added, these unit operations are performed in parallel for the degree, and the previous stage cumulative addition result is input to the next stage cumulative addition. Discrete Cosine Transform and Inverse Discrete Cosine Transform calculation method.