JPH0534587A - Accumulation controller for photoelectric converting element - Google Patents

Abstract

PURPOSE:To reduce a ratio occupied on the chip of a control part of a photoelectric converting element, and to improve the yield, and the degree of freedom of arrangement of the photoelectric converting element photodetecting part by providing the accumulation control signal detecting function of a pair of photoelectric converting element trains on only one of the pair. CONSTITUTION:A photoelectric converter for constituting an accumulation controller is constituted of a pair of photoelectric converting element trains, and a circuit SNDOUT for reading out the minimum value at the time when accumulation is finished. This photoelectric converting element train is provided with sensor control arrays SNCTLU-A, B containing sensor arrays SNSPX-A, B being photodetecting parts, respectively, and image signal reading-out circuits SNOUTU-A, B consisting of plural accumulating signal reading-out circuits. Also, only one photoelectric converting element train is provided with an accumulation maximum signal detecting circuit PDETU-A consisting of plural pieces of circuits having a maximum value detecting function of an accumulating signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls accumulation of photoelectric conversion elements used in a focus detection device of a camera or the like using a method of detecting a focus state from a relative positional relationship between two images.
The present invention relates to a storage control device for photoelectric conversion elements.

[0002]

2. Description of the Related Art As a conventional device of this type, for example, JP-A-61-167916 and JP-A-62-113.
There are those disclosed in Japanese Patent Application No. 468, Japanese Patent Application No. 61-219668 and Japanese Patent Application No. 62-27267. The configuration of the device disclosed in Japanese Patent Laid-Open No. 61-167916 is as follows.
The storage is controlled based on the average value of the amounts of light incident on the photoelectric conversion element array or the sum signal. The latter configuration controls the storage time based on the substantially maximum value of the photoelectric conversion element array. In either configuration, control is performed so that the signal level is as constant as possible so that signal processing in the subsequent stage is facilitated. As the signal processing in the latter stage, A / D conversion is carried out after amplification based on a light-shielded pixel (optical black), and then, Japanese Patent Laid-Open No. 58-1.
42306, JP-A-59-107313 and JP-A-6.
No. 0-101513 or Japanese Patent Application No. 61-16
The configuration for performing the operation disclosed in No. 0824 can be adopted.

FIG. 9 shows one conventional example. This figure shows a photoelectric conversion device including a pair of photoelectric conversion element arrays in which the photoelectric conversion element has a function of detecting the maximum value of the accumulated signal and the accumulation control is performed based on this. Further, FIG. 10 is a circuit block diagram of one photoelectric conversion element array constituting this photoelectric conversion device, and the block SNSCTL,
It consists of SNOUT and PDET. Note that FIG. 11 illustrates a photoelectric conversion device including four pairs of photoelectric conversion element arrays as an example in which a plurality of photoelectric conversion element arrays of FIG. 9 are arranged on the same chip.
Only the main part of FIG. 9 is shown in the figure, and SNS-1,
2, 3 and 4 are photoelectric conversion element arrays forming a pair.

Blocks SNSPX-A and SNS in FIG.
PX-B, SNSCTLU-A and SNSCTLU-B,
PDETU-A and PDETU-B and SNOTU-A and SNOTU-B have the same configuration, and block SNSPX-A is SNSPX and SNSCTLU-, respectively.
A is SNSCTLU, PDETU-A is PDETU, S
NOUTU-A is a collection of a plurality of SNOTU.

In FIGS. 9 and 10, the block SNSC is used.
TL is a bipolar transistor TR which is a photoelectric conversion element
1 control circuit, a plurality of MOS transistors MOS
5, MOS8. A block SNOUT is a circuit for reading out the accumulated signal of the photoelectric conversion element, and MOS10, M
OS11, MOS12, MOS13 and capacitor Ct
It is composed of n and Cts.

Further, a differential output amplifier SNAMP, MOS
It is composed of transistors MOS14 and MOS15.
The block PDET is a maximum signal detection circuit that detects the largest output signal obtained by photoelectrically converting the luminous flux incident on the photoelectric conversion element array, and is composed of a bipolar transistor TR2, a MOS transistor MOS6, and several MOS transistors shown in the figure. .. The block SNSCTLD has the same structure as the block SNSCTL except that the photoelectric conversion element is shielded by a sensor control circuit including the photoelectric conversion element SNSPXD shielded from light. The block DDET is connected to the output of a sensor control block SNSCTLD including a light-shielded photoelectric conversion element SNSPXD, and its circuit configuration is the same as that of the block PDET. Block SN
DOUT is a circuit that reads out the accumulated signal of the photoelectric conversion element that is shielded from light, and is the same as SNOUT.

In FIG. 10, P- connected to the base of a bipolar transistor TR1 which is a photoelectric conversion element.
The gates of the channel MOS transistors MOS5 are commonly connected and the reset clock φres of the photoelectric conversion element is input. The sources of the same MOS transistors are also commonly connected and supplied with a constant potential VBB. T
MOS transistor MOS connected to the emitter of R1
The gates of 8 are commonly connected and the reset clock φvrs is input. Further, the emitter is connected to the capacitor Ctn via the MOS transistor MOS10,
Via the MOS transistor MOS11, the capacitor C
respectively connected to ts and each capacitor Ctn,
The charge of Cts is the MOS transistor MOS1.
2, output to RDNL and RDLS via the MOS 13, and input to the output amplifier SNAMP. Also, MOS1
2, the MOS 13 is sequentially turned on by the shift register SNSR. The register SNSR is configured so that the signal terminal that becomes "H" is sequentially shifted by the read clock φread that is input.

The gates of the MOSs 10 are commonly connected and the accumulation starting clock φTn is input. MOS11
The gates of are connected in common and the clock
Ts is input. The inputs RDLN and RDLS of the output amplifier SNAMP are common output lines of the accumulated signal reading circuit connected to each photoelectric conversion element. Also, the MOS transistors MOS14, MO
It is connected to GND through S15. MOS14,
A read clock φhrs is input to the gate of the MOS 15.

The emitter of the bipolar transistor TR1 which is a photoelectric conversion element is also connected to the gate of the N-channel MOS transistor MOS6, and the output of the photoelectric conversion element is always supplied to the maximum signal detection circuit PDET during the accumulation time. The maximum signal detection circuit has a differential amplifier configuration, and the output stage is TR2 which is an NPN transistor and has an emitter follower type. Bipolar transistor TR2
Is the input line VpL of the output amplifier VpAMP.
Connected to. The emitter of the bipolar transistor TR2 of the maximum signal detection block PDET connected to each photoelectric conversion element is commonly connected to this VpL.

At this time, the emitter output of the bipolar transistor TR1 is at various levels depending on the illuminance of the luminous flux applied to each photoelectric conversion element, and the maximum signal detection circuit PDET connected to the emitter not at the maximum level performs a comparator operation. Therefore, the bipolar transistor TR2
Are all cut off, and only the maximum signal detection circuit PDET connected to the emitter at the maximum level operates as a voltage follower. The voltage follower output Vpmax of the bipolar transistor TR2 outputs a value equal to the potential input to the gate of the MOS transistor MOS6, and is the largest of one or a plurality of PDETs configuring PDETU-A and PDETU-B in FIG. The emitter potential Vpm of the output bipolar transistor TR2
ax is a constant current load ILmax and a buffer amplifier VpAM
It is output via P.

Further, the light-shielded photoelectric conversion element SNSPX
The output of block SNSCTLD containing D is block DD
Output to VdL via ET. A constant current load ILD is applied to VdL and is input to the buffer amplifier VdAMP. The buffer amplifier VpAMP output Vmax and the buffer amplifier VdAMP output Vd are input to the storage control circuit and the storage signal processing circuit, respectively.

[0012]

However, since the conventional example is configured as described above, the proportion of the control section becomes much larger than that of the photoelectric conversion element light receiving section (phototransistor), which increases the chip area. However, there is a problem in that the yield is reduced due to this. The present invention has been made to solve the problems of the conventional example as described above, and an object thereof is to improve the yield and the degree of freedom in arrangement of the photoelectric conversion element light receiving portion.

[0013]

Therefore, the storage control device for photoelectric conversion elements according to the present invention is provided with the storage control detection function of each pair of photoelectric conversion element rows only in one of the pair of each photoelectric conversion element row. Therefore, the above-mentioned object is achieved.

[0014]

With the above structure, the proportion of the control unit on the chip is reduced, the yield is improved, and the degree of freedom in arranging the photoelectric conversion element light receiving unit is also improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

(Structure) The photoelectric conversion device of this embodiment is a storage type photoelectric conversion element array composed of a phototransistor array disclosed in JP-A-60-12579 and JP-A-60-12765. It is configured. Unlike the known CCD sensor or MOS sensor, the photoelectric conversion element array accumulates charges proportional to incident light in the base portion of the transistor, and outputs a signal according to the accumulated charge amount for each element when reading. To do. The operation of the photoelectric conversion element alone is disclosed in the above-mentioned publications and the like, and therefore its explanation is omitted.

1 to 4 show an embodiment of the present invention.
FIG. 1 is a block diagram of a photoelectric conversion device including a pair of photoelectric conversion element arrays and peripheral circuits which best show the features of the present invention, and FIG. 2 is a diagram showing drive timing of the photoelectric conversion elements.
FIG. 3 is a block diagram of a storage control device for controlling the storage time of the photoelectric conversion device and a storage signal processing device, and FIG. 4 is a flowchart thereof. In the figure, the same or corresponding parts as in the conventional example are represented by the same reference numerals. In FIG. 1, the photoelectric conversion element is provided with a function of detecting the maximum value of the accumulated signal as the accumulation control signal detection function, and the photoelectric conversion device is composed of one photoelectric conversion element array for performing accumulation control based on this. Further, FIG. 10 is a circuit block diagram of one photoelectric conversion element which constitutes this photoelectric conversion device, and is composed of blocks SNSCTL, SNOUT and PDET.

A block SNSCTLU-A shown in FIG. 1 is a sensor control array including a sensor array SNSPX-A which is a light receiving section, and SNOUTU-A is an accumulated signal read circuit SNOUT.
SNDOUT is a circuit for reading out the minimum value VB at the end of accumulation, and PDETU-A is a circuit for maximizing accumulated signal detection including a plurality of circuits PDET having a maximum value detection function for accumulated signals. Blocks SNSPX-A and SNSPX- in the figure
B, SNSCTLU-A and SNSCTLU-B, SNO
UTU-A and SNOUTU-B have the same configuration. In the conventional example shown in FIG. 9 and the example shown in FIG. 1, blocks having the same function and configuration have the same block name. Therefore, the parts that overlap with the contents already described are omitted here.

Next, the structure of the storage controller will be described with reference to FIG. In FIG. 3, reference numeral 11 denotes a photoelectric conversion device having a plurality of photoelectric conversion elements, which has a function of detecting the maximum value Vmax of the accumulated signal and the light-shielding sensor output Vd during accumulation shown in FIG. Controls its accumulation. Here, φcont is a clock signal φres, φvrs, φTn, φ input to the photoelectric conversion device 11.
It is a general term for Ts, φsh, φhrs, and φread. 1
Reference numeral 2 denotes a differential amplifier that takes the difference between the maximum value Vmax and the light-shielding sensor output Vd. Reference numerals 13 and 14 denote difference signals between the maximum value Vmax and the light-shielding sensor output Vd from the differential amplifier 12 as predetermined levels Vref and Vref / 10, respectively. A comparator for comparison, 15 is a comparator for comparing the maximum value Vmax with a predetermined level Vref-L slightly smaller than the saturation level of the photoelectric conversion element, 16 is a memory circuit for storing the light-shielding sensor output VD at the end of accumulation, and 17 is An amplifier for amplifying the image signal VIDEO from the photoelectric conversion device 11 with the output of the storage circuit 16 as a reference, and a gain control signal Gcont (G
1, G2), the amplification factor (gain) is switched to 1 or 10 times. Specifically, when G1 = high level and G2 = low level, the gain of the amplifier 17 is 1 time, and when G1 = low level and G2 = high level, the gain is 10 times. Reference numeral 18 is a one-chip microcomputer, 19 is an oscillator, and 20 is a counter for counting a predetermined time Tmax immediately after the start of accumulation.

(Operation) Next, the operation of the blocks SNSCTL and SNOUT shown in FIG.
It will be described based on the chart. Since the operation of PDET has been described in the conventional example, the description thereof will be omitted. In the figure, φres, φvr
s, φTn, φTs, φsh, φhrs, and φread are clock signals input from the one-chip microcomputer 18 shown in FIG.
In the figure, the generic name is shown as φcont.

By setting φres to be "L", all P-
The channel MOS transistor MOS5 turns on,
The potential VBB is applied to the base of each transistor TR1. As a result, the residual potential of the base of TR1 becomes VBB.
If it is larger, the excess charge is recombined, and finally the charge having the base potential as VBB is held in the base. Further, since φTn, φTs, and φvrs are also “H” between t1 and t2, the charges in the capacitors Cts and Ctn are also cleared via the MOS transistor MOS8.

Next, since φres becomes “H” at time t4 and φvrs becomes “H” at t5, the charges held in the base gradually recombine and disappear. At the time t4, the base potential of the base of each transistor TR1 is V
Since the electric charge of BB was held, the amount of electric charge remaining in the base at time t6 is equal in all TR1 regardless of the amount of electric charge held before time t3.

When φvrs becomes "L" at time t6, M
The OS8 is turned off, and the electric charges generated by photoexcitation are accumulated in the base of the transistor from this point. The period from time t1 to time t6 is the reset operation of the sensor. After a predetermined accumulation time, φ from time t9 to t10
The pulse of Ts causes the MOS 11
Is turned on, and a signal corresponding to the amount of charge accumulated in the base of TR1 is transferred to the capacitor Cts by the transistor operation. Therefore, at this time, the charges accumulated in the base do not decrease, and TR1 continues to accumulate the photoexcited charges in the base.

After this, first, from time t1 to t11, φh
When rs becomes “H” for a predetermined time, the MOS14, MO
S15 turns on for that time, and read lines RDLN, R
The electric charge remaining in the floating capacitance of DLS is caused to flow to GND, and a pulse of φread from time t12 to t13 causes each MOS transistor MO by the shift register SNSR.
The scanning of S12 and MOS13 is started. MOS12, M
When the OS13 is turned on, the light-shielding sensor output reading circuit S
The signals held in the capacitors Ctn and Cts of NDOUT pass through the read lines RDNL and RDLS, and through the differential output amplifier SNAMP, their differential output VIDE.
O is output, then each sensor output read circuit SNO
The signals of the UT capacitors Ctn and Cts are also VID
Output to EO.

By repeating the above operation, the time t
The photoelectrically converted signals can be sequentially read during the accumulation time from 6 to t9. When the reading of the signals from all the bipolar transistors TR1 is completed in this way, the reset operation from time t1 to t6 is performed again and the next accumulation operation is started. The above is the description of the operation of the image signal detection system.

Next, the operation of FIG. 3 will be described with reference to the flowchart of FIG. FIG. 4 is described in a subroutine format. In general, such a storage control program for a sensor is rarely used by itself, and the description in the subroutine format is more versatile. Further, the control signal φcont used in the following description is φres, φvrs, φTn, φT in the timing chart shown in FIG.
It is a general term for s, φhrs, and φread.

(Step 201) This subroutine is called.

(Step 202) The control signal φcont and the reset signal are generated, and the photoelectric conversion device 11 automatically shifts to the accumulation operation immediately after the initialization operation.

(Step 203) A counter 20 determines whether or not a predetermined time Tmax has elapsed after the accumulation operation was started.
Detected by the signal from. If the predetermined time Tmax has elapsed, the accumulation is terminated, and the process proceeds to (Step 206) to determine the gain of the amplifier 17, and otherwise the process proceeds to (Step 204).

(Step 204) It is detected whether or not the accumulated signal reaches the saturation level of the photoelectric conversion device 11. Therefore, when the signal φmax indicating whether or not the maximum value Vmax of the photoelectric conversion device 11 exceeds Vref-L indicating a level close to saturation is at a high level, the accumulation is ended and the gain of the amplifier 17 is determined ( The process proceeds to step 206), and otherwise proceeds to (step 205).

(Step 205) The difference between the maximum value Vmax of the photoelectric conversion device 11 and the light-shielding sensor output Vd is a predetermined level V.
The signal φcomp is used to check whether ref has been reached.
If 2 is a high level, the accumulation is terminated, the process proceeds to (Step 206) to determine the gain of the amplifier 17, and otherwise returns to (Step 203).

(Step 206) In order to determine the gain of the amplifier 17 at the time of reading the accumulated signal, the state of the signal φcomp1 is examined by comparing the difference between the maximum value Vmax and the light-shielding sensor output Vb with the predetermined level Vref / 10. As a result, when the signal φcomp1 is at high level (step 20
7), and when the signal φcomp1 is at low level, the process proceeds to (step 208).

(Step 207) Since the signal φcomp1 is at the high level (if the signal φcomp1 is at the high level, the process always goes to the step), the gain of the amplifier 17 is set to 1 time. = High level (H), G2 = Low level (L). In this case, the contrast of the subject is relatively high.

(Step 208) Since the signal φcomp1 is at the low level, G1 = low level and G2 = high level are set to set the gain of the amplifier 17 to 10 times. In this case, the contrast of the subject is relatively low.

(Step 209) A control signal φcont is generated to end the storage of the photoelectric conversion device 11.

(Step 210) This subroutine is completed.

Next, a second embodiment will be described with reference to FIGS. In the first embodiment, the storage control signal detector is a method for detecting the maximum value of the plurality of photoelectric conversion elements, but the storage control signal detector in the present invention is not limited to this. FIG. 5 shows another embodiment of the photoelectric conversion device having a function of detecting the maximum value and the minimum value of the accumulated signal of the photoelectric conversion device, which greatly contributes to the improvement of the low contrast limit of the focus detection device. The application is shown. In the figure, the configuration of FIG. 1 used in the first embodiment is added with a function of detecting the minimum value of a plurality of photoelectric conversion elements, and its circuit block is shown by BDETU in the figure. Further, BDETU is composed of a plurality of blocks BDET shown in FIG.

FIG. 6 shows the photoelectric conversion element array 1 shown in FIG.
FIG. 3 is a block diagram showing the configuration of a photoelectric conversion element, which is composed of blocks SNSCTL, SNOUT, PDET, BDET. 6, blocks having the same names as those in FIG. 1 have the same configuration and function. Therefore, since the same name block has already been described, the minimum value detection circuit blocks BDET and BDETU will be mainly described here.

In the figure, the emitter of the bipolar transistor TR1 which is a photoelectric conversion element is an N-channel M.
Gate of OS transistor MOS6, P-channel M
It is also connected to the gate of the OS transistor MOS7,
Output of photoelectric conversion element is always maximum signal detection circuit PDE during accumulation
It is supplied to T and the minimum signal detection circuit BDET. The maximum signal detection circuit PDET and the minimum signal detection circuit BDET are mutually complementary differential amplifier configurations, and the output stages are NPN transistors and PNP transistor emitter-follower types, respectively, and VpAM is used for each.
Vmax via P, V via output amplifier VbAMP
It is output to min.

The maximum signal detection block PDE connected to each photoelectric conversion element is connected to the input line VpL of VpAMP.
The emitter of the bipolar transistor TR2 of T is Vb
The minimum signal detection block B is provided on the input line VbL of the AMP.
The emitters of the DET bipolar transistors TR3 are commonly connected.

Further, since the minimum signal detection circuit connected to the emitter not at the minimum level performs a comparator operation, all the bipolar transistors TR3 are cut off, and the minimum signal connected to the emitter at the minimum level is connected. Only the detection circuit operates as a voltage follower. The output Vbmin of the bipolar transistor TR3 outputs a value equal to the potential input to the gate of the MOS transistor MOS7, and a plurality of B's constituting BDETU-A of FIG.
Of the DETs, the smallest output, the emitter potential Vbmin of the bipolar transistor TR3, is the constant current load I.
It is output via Lmin and the buffer amplifier VbAMP. The buffer amplifier VpAMP output Vmax and the buffer amplifier VbAMP output Vmin are input to the storage control circuit and the storage signal processing circuit, respectively.

Further, the minimum accumulated signal reading block SN
VbL is input to BOUT, and the image signal reading circuit SNO is output according to the signal from the shift register SNSR.
Similar to UTU-A and SNOUTU-B, the differential output amplifier SN is output to the read lines RDLN and RDLS.
It is output to VIDEO via AMP.

Next, a third embodiment will be described with reference to FIG. In the first embodiment, the storage control signal detector is provided in the first row of the one-to-one photoelectric conversion element row. However, in such a focus detection device, the storage control signal detector is provided in the second row, and the accumulation is performed based on this. Control can also be performed. FIG. 7 is a diagram showing the characteristics of the third embodiment. Each block in the figure has the same function and configuration as the first embodiment.

Next, a fourth embodiment will be described with reference to FIG. In Embodiments 1, 2, and 3, the implementation to a photoelectric conversion device including a pair of photoelectric conversion element arrays was taken up, but when the present invention is applied to a photoelectric conversion device including a plurality of photoelectric conversion element arrays, Give effect. FIG. 8 shows a block diagram of a photoelectric conversion device including four pairs of photoelectric conversion element arrays. It should be noted that the figure shows only the main part of FIG. 1 in blocks, and SNS-1, 2, 3, and 4 are a pair of photoelectric conversion element arrays, respectively.

[0045]

As described above, according to the present invention, the number of the storage control signal detection units based on the storage signals of the photoelectric conversion device is one for each pair of photoelectric conversion element rows, thereby reducing the circuit scale and the yield. It will be possible to improve resources and save resources and reduce costs.

[Brief description of drawings]

FIG. 1 is a block diagram of a photoelectric conversion device according to a first embodiment.

FIG. 2 is a drive timing diagram of a photoelectric conversion element.

FIG. 3 is a block diagram of a storage control device that performs storage time control and storage signal processing of the photoelectric conversion device.

FIG. 4 is a flowchart of a storage control program

FIG. 5 is a block diagram of a photoelectric conversion device according to a second embodiment.

FIG. 6 is a block diagram of one photoelectric conversion element included in the photoelectric conversion device according to the second embodiment.

FIG. 7 is a block diagram of a photoelectric conversion device according to a third embodiment.

FIG. 8 is a block diagram of a photoelectric conversion device including four pairs of photoelectric conversion element arrays according to a fourth embodiment.

FIG. 9 is a block diagram of a conventional photoelectric conversion device.

FIG. 10 is a block diagram of one photoelectric conversion element that constitutes a photoelectric conversion device of a conventional example.

FIG. 11 is a block diagram of a photoelectric conversion device including four pairs of photoelectric conversion element arrays of a conventional example.

[Explanation of symbols]

 SNSCTLU-A, B Sensor control circuit array SNOUTU-A, B Image signal readout circuit array PDETU-A, B Accumulated maximum signal detection circuit array

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/335 Q 8838-5C

Claims (1)

Claim: What is claimed is: 1. A photoelectric conversion element array comprising one or more pairs of photoelectric conversion element arrays, the photoelectric conversion element array having a storage control signal detection function based on a storage signal, In a photoelectric conversion element accumulation control device for performing accumulation control, the photoelectric conversion element accumulation control is provided with the accumulation control detection function of each pair of photoelectric conversion element rows only in one of the pairs of each photoelectric conversion element row. apparatus.