JPH05345438A - Semiconductor chip for driving recording head and recording head driving device - Google Patents

Abstract

PURPOSE:To carry out recording of well-balanced printing density based on the recording information such as heat accumulation between recording heads adjoining each other. CONSTITUTION:A control signal for power application time to a heating resistance element 7b (recording head) is input to a driving gate circuit 5b by AND gates 2a and 2c and OR gates 3a and 3c correspondingly to the recording information at the present time or in the past from latch circuits 1a and 1c adjoining each other. The adjoining information of latch circuits 11a and 11c at both ends are terminal processed in the above manner by external input and output terminals (LD1IN, LD64OUT and the like) on semiconductor chips when a plurality of semiconductor chips are provided. Therefore, adjoining recording information at both end bits can be found even when a plurality of semiconductor chips are installed in parallel, and heat control of high accuracy can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording head driving semiconductor chip and a recording head driving device used as a printing section of a facsimile, a printer or the like.

[0002]

2. Description of the Related Art FIG. 9 is a circuit diagram showing a conventional recording head driving device for a thermal head for 3 dots. As shown in FIG. 9, the thermal head has this circuit for a predetermined number of dots. In FIG. 9, 1 is a shift register that shifts the input current line data in accordance with a clock, and has a number of stages corresponding to the number of dots of the thermal head. Reference numerals 11a to 11c are latch circuits for capturing and holding the data appearing in the taps (Q1 to Q3) of the shift register 1, 31 is three gate signals GA, GB, GC.
Signal generators 4a to 4c and 8a to 8c
Is the output of the latch circuits 11a to 11c and the gate signal G
NAND gates of inverted logical product (NAND) in which B and GC are introduced, 5a to 5c are gate circuits of logical product (AND) that outputs a pulse signal indicating an energized state, and 6a to 6c are heating resistors 7a according to the pulse signal. A Darlington transistor (driving element) for driving ~ 7c (recording head).
Reference numerals 10a to 10c are AND gates, and two input terminals are connected to the Q1 terminals of the respective latch circuits 11a to 11c adjacent to each other. 9a to 9c are analog switches, which are output signals of the AND gates 10a to 10c. It receives and opens. Reference numeral 102 denotes a control signal, which is a predetermined pulse signal and is an analog switch 9a.
Is input to 9c. Reference numeral 52 is a gate circuit as an AND gate, and 7 is a heating resistor as a recording head.

Next, the operation of this conventional example will be described.
The latch circuits 11a to 11c sequentially take in data from the shift register 1 according to a latch signal externally input, as in the conventional case. As a result, the record information of the previous line (past) is output to the Q2 terminal, and the record information of the previous line (the past) is output to the Q3 terminal. Also,
The recorded information (current) of the current line is stored in the latch circuits 11a to 11a.
Although output to the Q1 terminal of 1c, the recording information of the adjacent dot, that is, the recording information of the Q1 terminal of each adjacent latch circuit is input to the respective AND gates 10a to 10c. On the other hand, as shown in FIG. 10, the control signal 102 ((K) in FIG. 10) is input to each of the analog switches 9a to 9c at the input timing ((C) in FIG. 10) of the latch signal of the latch circuits 11a to 11c. The AND gates 10a-10
When the analog switches 9a to 9c are turned on in response to the output of c, the control signal is input to the gate circuits 5a to 5c. In this case, the energization time of the control signal 102 is set to be slightly shorter than the gate signal GA of the gate signal generator 31 ((D) of FIG. 10) as shown in FIG. Therefore, one of the AND gates 10a to 10c is input, that is, a pair of adjacent latch circuits 11a to 11c.
When the output signals of both Q1 terminals of c are "H", the analog switches 9a-9c connected to the AND gates 10a-10c are closed and the control signal 102 is input to the gate circuits 5a-5c. On the other hand, when one or both Q1 terminals of the adjacent latch circuits 11a and 11c are "L", the analog switches 9a to 9c are turned off and the control signal 102 is input to the gate circuits 5a to 5c. Therefore, the gate inputs of the gate circuits 5a to 5c have high impedance. As a result, the outputs of the gate circuits 5a to 5c become (G) to (J) in FIG. Here, Q1 to Q3 in (G) to (J) indicate output states of the latch circuits 11a to 11c. Also,
GB and GC of (E) and (F) are output signals (GB and GC) of the gate signal generator, (A) is a clock signal, and (B) is data.

FIG. 11 shows the surface temperature when the adjacent heating resistors generate heat. Now, as shown in FIG. 11 (A), the adjacent heating resistors 70a, 70b,
70c, each heating resistor 70a, 70 under certain conditions.
b and 70c are selectively driven. For example, the heating resistor 70b generates heat, and the heating resistors 70a, 7 adjacent to the heating resistor 70b generate heat.
When 0c does not generate heat, as shown in FIG.
While it is 50 ° C., when it is heated adjacent to it, the temperature is 280 ° C. as shown in FIG. Further, when one of the heating resistors 70a or 70c does not generate heat, the temperature becomes 265 ° C. as shown in FIG. 11 (C).
Therefore, by supplying the energy determined by the energization time of the control signal to each of the heating resistors 70a, 70b, 70c, it is possible to correct the relative influence of heat generated by the adjacent ones for printing, and to obtain a highly accurate thermal history. A balanced print density can be obtained by the control. FIG. 12 shows the position of each input / output signal pad when the conventional recording head drive device is mounted on a semiconductor chip. 12
In the figure, 30 is an output pad portion, and 31 is a semiconductor chip. The output pad 30 is a pad for outputting print information to the recording head, and includes GND, 102, GA, GB,
The GC, latch signal, data, clock, and power supply are pads for input / output signals with other circuits. The positions of the pads in the conventional semiconductor chip have been arranged in a row at positions facing each other on the semiconductor chip 31.

Thus, in the semiconductor chip 31 shown in FIG. 12, the output pads 30 for driving the heating resistors are arranged in a line at one end, and the input / output signal pads including the power supply and the ground (GND) are arranged at the other end. To do. A plurality of semiconductor chips 31 are usually arranged, but since these semiconductor chips are mounted on a ceramic substrate, a glass substrate, or the like, the pattern manufacturing accuracy is high. On the other hand, the output pad 30 has the same substrate or a semiconductor chip with poor pattern manufacturing accuracy, for example, P
Even if it is installed on a CB (printed wiring board) substrate, the corresponding pads can be accurately manufactured as long as they are the above-mentioned ceramic substrate or glass substrate. Therefore, the output pads can be installed with high density even on the semiconductor chip. However, since the total number of input / output signal pads and the like is smaller than the number of output pads, the input / output signal pads are installed at a low density.

[0006]

Since the conventional recording head drive device is configured as described above, when the print history control of the recording head is to be strictly performed, the output Q1 of the latch circuit 11a is changed. There is only one adjacent data at both ends of the circuit that constitutes it (the input of the AND gate 10a is only the output Q1 of the latch circuit 11b). For this reason, when a plurality of constituent circuits are arranged, the heating resistor 7a located at the boundary for each constituent circuit unit is subjected to different thermal control from that of the other portions, and strict print density control is performed. There was a problem that it could not be realized. In addition, when the above-described recording head driving device is mounted on a semiconductor chip and a plurality of the recording head driving devices are connected, high density mounting cannot be performed.

The present invention has been made in order to solve the above-mentioned problems, and solves the inconvenience regarding the control of the print density generated by the heating resistor at the boundary of each unit of the circuit to be formed. It is possible to give optimum print energy to each recording head, and it is possible to perform high-precision and high-quality recording with a constant print density in the dots of the recording head. An object of the present invention is to obtain a recording head driving semiconductor chip and a recording head driving device which can be mounted at high density by devising the arrangement position.

[0008]

As shown in FIG. 1, a recording head driving semiconductor chip according to the present invention has a recording information of a current line of a dot to be driven and recording information of each dot of a previous line. Circuit 11a for holding
.About.11c, gate circuits 5a to 5c for outputting pulse signals indicating the energized state to the recording head, and the gate circuits to output pulse signals corresponding to the energized states according to the output patterns of the latch circuit. Control for controlling the energization time to the recording head according to the recording information from the gate signal generating unit 31 that outputs a gate signal and the latch circuit for each dot and the other latch circuit adjacent thereto. A recording head driving device having gates (OR gates 3a to 3c, etc.) for inputting signals to the gate circuit, wherein external input / output terminals (LD1IN, LD64OUT, etc.) are provided for information of the first and last bits of adjacent bits.
Installed as. In addition, a pull-down resistor or a pull-up resistor was inserted and installed in the input terminal. Further, as the external input / output terminal, as shown in FIG. 5, it was installed on the side surface of the end portion of the semiconductor chip. In addition, the ground pad of the semiconductor chip pad of the semiconductor chip and all or some of the external I / O terminal pads of the first and last bits are grouped together, the other I / O pads are grouped together, and the input pad except the output pad is grouped together. The output signal pad is divided and arranged.

As shown in FIG. 1, the recording head driving apparatus according to the present invention holds latch information 11a to 11c for holding the recording information of the current line of the dot to be driven and the recording information of each dot of the previous line. And a gate circuit 5a for outputting a pulse signal indicating the energization state of the recording head.
5c, a gate signal generator 31 for outputting a gate signal for causing the gate circuit to output a pulse signal corresponding to the energized state according to each output pattern of the latch circuit, and the latch circuit for each dot, A control signal for controlling the energization time to the recording head is output according to the recording information from the own latch circuit and another adjacent latch circuit.
AND gates 2a to 2c, 2 input to the gate circuit
, and external input / output terminals (LD1IN, LD64OUT, etc.) capable of inputting / outputting recording information from the other latch circuit adjacent to the output of its own latch circuit located at the boundary.
Further, a pull-down resistor or a pull-up resistor is inserted in the external input terminal.

Further, as shown in FIG. 1, the recording head drive device according to the present invention latches the recording information of the current line of the dot to be driven and the recording information of each dot of the previous line. .About.11c, gate circuits 5a to 5c for outputting a pulse signal indicating the energization state to the recording head, and a gate for causing the gate circuit to output a pulse signal corresponding to the energization state according to each output pattern of the latch circuit. Gate signal generator 31 for outputting a signal
And a control signal for controlling the energization time to the recording head is input to the gate circuit according to the recording information from the latch circuit for each dot and the other adjacent latch circuit. Gates 2a-2
c, 2n, and a control signal for controlling an energization time different from the above energization time according to recorded information from other adjacent latch circuits other than the own latch circuit among the latch circuits for each dot. OR gate 3 input to the gate circuit
external input / output terminals (LD1IN, LD64OUT) capable of inputting / outputting recording information from the own latch circuit output located at the boundary and the adjacent latch circuit
Etc.). In addition, a pull-down resistor or a pull-up resistor is inserted in the external input terminal.

Further, the recording head drive device according to the present invention has a latch circuit for holding the recording information of the current line of the dot to be driven and the recording information of each dot of the previous line, and the energization state to the recording head. Gate circuits 11a to 11c for outputting a pulse signal indicating that the gate signal is generated, and a gate signal generator 5a for outputting a gate signal for causing the gate circuit to output a pulse signal corresponding to the energized state according to each output pattern of the latch circuit. 5c and a control signal for controlling the energization time to the recording head in accordance with the recording information from the latch circuit for each dot and the other latch circuit adjacent thereto among the latch circuits for each dot are input to the gate circuit. The first AND gates 2a to 2c and 2n and adjacent latch circuits other than the own latch circuit among the latch circuits for each dot. A second AND gate (not shown) for inputting a control signal for controlling an energization time different from the above energization time to the gate circuit according to past record information from the circuit is provided at the boundary. External input / output terminals (LD1IN, LD64OUT) for inputting / outputting recording information from another latch circuit adjacent to the output of the latch circuit are provided. In addition, a pull-down resistor or a pull-up resistor is inserted in the external input terminal.

Further, as shown in FIG. 1, the recording head drive device according to the present invention holds the recording information of the current line of the dot to be driven and the recording information of each dot of the previous line. .About.11c, gate circuits 5a to 5c for outputting pulse signals indicating the energized state to the recording head, and the gate circuits to output pulse signals corresponding to the energized states according to the output patterns of the latch circuit. Gate signal generator 3 that outputs a gate signal
1 and a control signal for controlling the energization time to the recording head in accordance with the recording information from the latch circuit for each dot and the other latch circuit adjacent thereto is input to the gate circuit. A recording head driving device comprising a semiconductor chip provided with an external input / output terminal capable of inputting / outputting recording information from another latch circuit adjacent to the output of its own latch circuit located at the boundary with a gate, The pattern pad adjacent to the pad of the semiconductor chip corresponding to the terminal was set at the boundary (FIG. 5) of the adjacent semiconductor chip, and the input part and the output part of the external input / output terminal were connected to the same pattern pad. Further, the pattern pad is installed on a substrate different from the substrate on which the semiconductor chip is mounted and connected by wire bonding, and the pattern pad has a small structure (FIG. 8).
Further, the substrate on which the pattern pad is installed is composed of a printed wiring board.

[0013]

In the semiconductor chip for driving a recording head according to the present invention, information of the first and last bits of adjacent bits is installed as external input / output terminals (LD1IN, LD64OUT, etc.). When using by connecting multiple semiconductor chips,
The external input terminal of one semiconductor chip is connected to the external output terminal of a semiconductor chip adjacent to the semiconductor chip, and the external output terminal of one semiconductor chip and the external of the semiconductor chip adjacent to the semiconductor chip are connected. Connect to the input terminal. By doing so, in one semiconductor chip and a semiconductor chip adjacent to this semiconductor chip, the respective gates (OR gates 3a to 3c, etc.) at the boundary between the two chips have their own latch circuit and other adjacent latches. A control signal for controlling the energization time to the recording head is input to the gate circuit in accordance with the recording information from the. As a result, the print density can be controlled in a balanced manner according to the states of the adjacent print heads, the print density in each dot of the print heads can be made uniform, and high-precision and high-quality printing can be realized. Further, since a pull-down resistor or a pull-up resistor is inserted in the input terminal, when a plurality of semiconductor chips are connected, the gates at both ends of these chips do not operate. Dot does not print. Therefore, high-precision and high-quality printing can be realized. Furthermore, by providing the external input terminal on the side surface of the end portion of the semiconductor chip, the connection when a plurality of semiconductor chips are lined up is facilitated and high-density mounting becomes possible. In the above semiconductor chip, the ground pad of the semiconductor chip pad and all or some of the external input / output terminal pads of the first and last bits are grouped together, the other input / output pads are grouped together, and the output pad is excluded. I / O signal pads are divided and arranged. As a result, connection can be facilitated when a plurality of semiconductor chips are arranged, and high-density mounting can be achieved. Further, the gate is an AND gate to print with high accuracy and high image quality. Further, the gate is an OR gate so that printing can be performed with high accuracy and high image quality.

In the recording head drive device according to the present invention, the information of the first and last bits of the adjacent bits is installed as external input / output terminals. When a plurality of devices are connected and used, the external input terminal of one device is connected to the external output terminal of a device adjacent to the device, and further the external output terminal of one device and the device Connect to the external input terminal of the adjacent device. By doing so, in one device and a device adjacent to this chip, the respective first and second AND gates (AND gates 2a to 2c, etc.) at the boundary of both devices have their own latch circuit and A control signal for controlling the energization time of the recording head is input to the gate circuit according to the current and past recording information from another adjacent latch. As a result, the print density in each dot of the recording head can be made uniform, and high-precision and high-quality printing can be realized. Further, since the pull-down resistor or pull-up resistor is inserted in the input terminal, when a plurality of semiconductor chips are connected, the first and second AND gates at both ends of these chips do not operate. The dots on the recording head corresponding to the AND gate of are not printed. Therefore, high-precision and high-quality printing can be realized.

Further, the recording head drive device according to the present invention includes the latch circuits 11a to 11c and the gate circuits 5a to 5c.
, The gate signal generator 31, and the external input / output terminal (LD1
IN, LD64OUT) and a patterning pad connected to a pad of the semiconductor chip corresponding to the external input / output terminal is provided at a boundary between adjacent semiconductor chips. ..
Further, the input part and the output part of the external input / output terminal are adjacent to the same pattern pad. As a result, high-density mounting on a semiconductor chip becomes possible. Further, the pattern pad is installed on a substrate different from the substrate on which the semiconductor chip is mounted and connected by wire bonding, and the pattern pad has a "chidori" structure, which enables high-density mounting. .. Furthermore, by using a printed wiring board as the substrate on which the pattern pads are installed, higher density packaging can be achieved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a recording head driving device according to an embodiment of the present invention. In FIG. 1, LD1I
N is an input terminal for externally input adjacent recording information, LD
64IN is also an input terminal for adjacent recording information input from the outside, LD1OUT is an adjacent recording information output terminal output to the outside, and LD64OUT is also an adjacent recording information output terminal output to the outside. 12a to 12c are analog switches, and 133 is a control signal, and this control signal is input to the analog switches 12a to 12c as a predetermined pulse signal. This analog switch 1
It is also possible to configure the NAND gate circuits 15a to 15c shown in FIG. 4 for 2a to 12c. 40,4
Reference numeral 1 is a pull-down resistor, 2a to 2c and 2n are AND gates, and 3a to 3c and 3n are AND gates. The external input terminal LD1IN is connected to the input of the OR gate 3a, and the external input terminal LD1IN is grounded by the pull-down resistor 40. Similarly, the external input terminal LD
64IN is connected to the input of the AND gate 2n and is grounded by the pull-down resistor 41. These pull-down resistors 40 and 41 are dots (heating resistors) at both ends of the recording head when a plurality of head drive devices are connected.
Is not printed because only the condition of the latch circuit recording information on one side is input for the dots at both ends. The pull-down resistors 40 and 41 are connected to the pull-up resistors 50 and 41 as shown in FIG.
It is also possible to comprise 52 and inverters 51 and 53. Further, pull-down or pull-up resistors may be inserted as external resistors at the inputs of the adjacent recording information terminals corresponding to the first and last dots of the drive circuit as the thermal recording head. Regarding the other circuits, the same components as those shown in the figure are designated by the same reference numerals, and the duplicated description thereof will be omitted.

In this embodiment, 64 units constitute one unit of the constituent circuit. Therefore, a boundary portion occurs at the 64th position and the 1st position. Normally, since a plurality of constituent circuits are provided, a large number of boundaries are generated, but boundaries are generated at both ends where a plurality of constituent circuits are integrated, but this can be dealt with by performing terminal processing.

Next, the operation of the above embodiment will be described.
This device is designed to control the energizing time of the heating resistor.
The system control signals 102 and 133 are used, and each Q1 terminal of the adjacent latch circuits 11a and 11c is AND gate 2
By inputting the record information of each Q1 terminal of the other adjacent latch circuits 11a and 11c other than the own latch circuit 11b to the OR gate 113, it is possible to respond to the output of the AND gate 2b and the output of the OR gate 3b. The control signals 102 and 133 are input to the AND gate 5b via the analog switches 9b and 12b that open and close.

During the period when the analog switch 9b is turned on,
Since the control signal 102 is input to the gate circuit 5b, when both the recording information of the current line and the information of the adjacent bit are "H", the width is shorter than the gate signal GA of the normal widest gate signal generating section 31. The energization of the heating resistor is completed. Also, during the period when the analog switch 12b is turned on,
Since the control signal 133 is input to the gate circuit 5b, when either of the adjacent information of the corresponding bits of the recorded information of the current line is "L", the heating resistor 7b is energized with a width shorter than the gate signal GA. Done.

FIG. 2 shows the control signals 102 and 133.
5 is a timing chart showing the timing relationship between ((K), (L)) and the energization time of each gate signal GA, GB, GC of the gate signal generator 31. Each of these signals 102,
133, the gate signal GA has the same rising edge,
The energization time is completed in the order of the control signal 102, the control signal 133, and the gate signal GA ((K) to FIG. 2).
(D)). That is, these energization times are 280 ° C. and 265, which are the heat generation states of the adjacent bits as shown in FIG.
C., 250.degree. C. ((B) to (D) in FIG. 11), and when the heat generation is large, the energization time is shortened, and here, each signal is adjusted to be equivalent to 250.degree. Determine the set time of.

FIG. 5 shows the outer shape of the semiconductor chip of the circuit that constitutes the recording head drive circuit. In this case, a pad for inputting / outputting adjacent recording information is added. Since it is customary to use a plurality of these semiconductor chips side by side, in the present embodiment, LD1IN and LD1OU are used.
T and LD64IN and LD64OUT are properly connected by wire bonding or face down bonding. Also, LD1IN and LD64OUT are installed close to each other, and LD64IN and LD1OUT are installed close to each other. Further, by disposing LD64IN and LD64OUT at positions opposite to the group of LD1IN and LD1OUT, connection becomes easy when a plurality of semiconductor chips are arranged. Further, in the present embodiment, 64 constituent elements are grouped as one unit,
Secondly, a pad for inputting / outputting the adjacent recording information is provided, and a pull-down resistor is added to the input signal section. Even when a plurality of semiconductor chips are connected, the boundary portions at both ends remain as before, and the recorded information on the outside is “L” (white), and is added in the sense of terminal processing. .. By doing so, highly accurate printing control can be performed on all the elements.

In this embodiment, two systems of control signals are provided, but one system or three or more systems may be provided. Further, although the input / output logic of the adjacent recording information is composed of AND gates or OR gates, since it is only a logic problem, it may be composed of other gates, switches or gate arrays. Further, in this embodiment, the adjacency information of Q1 is described, that is, the adjacency information of the boundary part regarding the current line information is described. It may be configured using input / output signals for recording. Furthermore, in this embodiment, a pull-down resistor is added to the adjacent recording information input terminal at the boundary portion, but it can be used even if it is not functional.

Here, LD1IN, LD1OUT, LD
The input / output signal pads of 64IN and LD64OUT indicate the external input / output terminals of FIGS. 1, 3 and 4. Regarding the arrangement of pads, it is customary to install an output pad at one end and an input / output signal pad including a power supply and a ground (GND) at the other end. On the other hand, when the adjacent input / output pads for the recording information are added as in this embodiment, the number of input / output signal pads increases, so that it is difficult to arrange them in a line. Therefore, when the pads are arranged using the side surface, the pads can be installed even if the number of pads for the adjacent recording information is increased by adopting the pad arrangement shown in FIG.

Further, in the case of the pad arrangement shown in FIG. 5,
If there is a gap between the adjacent semiconductor chips, there is no problem, but if the semiconductor chips are arranged close to each other, the pattern pad cannot be installed on the side surface of the semiconductor chip. Therefore, as shown in FIG. 6, the pad arrangement has a two-stage structure of an upper part and a lower part, and input / output signals are installed on the end side. I / O signal pads for adjacent recording information (LD
1IN, LD1OUT, LD64IN, LD64OU
T) It is good to install together.

When the semiconductor chips are arranged close to each other, if the pattern pads corresponding to the adjacent recording information pads are partially or entirely installed at the boundary surface positions of the semiconductor chips as shown in FIG. However, high density mounting is possible at most.

Further, when the semiconductor chips are arranged close to each other, when the pattern pads are wire-bonded to another substrate and the other substrate has a relatively low mounting wiring density such as a PCB base material, As shown in FIG. 8, the pattern pads on the PCB side are arranged in a narrow manner, and the pattern pads corresponding to the adjacent recording information terminals are also provided on the boundary surface of the semiconductor chip, which enables high-density mounting even if the number of pads is large. ..

[0027]

As described above, according to the present invention, when a plurality of recording head driving semiconductor chips and a plurality of recording head driving devices are connected and used, adjacent recording information is recorded at the boundary portion between the chips and the device. Since the circuit located at is also input, the print density in the recording head becomes constant, and there is an effect that high-precision and high-quality recording can be performed.
Further, since the dots at both ends of the recording head cannot be printed due to the pull-down resistor or the pull-up resistor, the print density of all dots of the recording head becomes constant, and there is an effect that high-precision and high-quality recording is possible. .. Furthermore, since the chip pads of the semiconductor chip and the pattern pads of the substrate are provided at positions where it is easy to connect, there is an effect that high density mounting is possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a recording head driving device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signals of various parts of the circuit in FIG.

FIG. 3 is a circuit diagram showing a recording head driving device according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a recording head driving device according to another embodiment of the present invention.

FIG. 5 is a layout diagram of semiconductor pads of a recording head driving device according to an embodiment of the present invention.

FIG. 6 is a semiconductor pad diagram of a recording head driving device according to another embodiment of the present invention.

FIG. 7 is a semiconductor pad diagram of a recording head driving device according to another embodiment of the present invention.

FIG. 8 is a semiconductor pad diagram of a recording head driving device according to another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a conventional recording head driving device.

10 is a timing chart showing signals of various parts of the circuit in FIG.

FIG. 11 is an explanatory diagram showing the influence of heat generation of one bit of the recording head on an adjacent bit.

FIG. 12 is a layout diagram of semiconductor pads of a conventional recording head driving device.

[Description of Reference Signs] 1 shift register 11a to 11c latch circuit 31 gate signal generator 5a to 5c recording head driving gate circuit 2a to 2c, 2n AND gate 9a to 9c, 12a to 12c analog switch 30 output pad 51, 53 inverter 50,52 Pull-up resistance 102,133 Control signal 6a-6c Driving element 7a-7c Heating resistor (recording head) 3a-3c, 3n OR gate 4a-4c, 7a-7c NAND gate 40,41 Pull-down resistance

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display area B41J 3/20 115 F

Claims (13)

[Claims] 1. A latch circuit for holding recording information of a current line of a dot to be driven and each recording information of that dot of a previous line, and a gate circuit for outputting a pulse signal indicating an energized state to a recording head. , A gate signal generator for outputting a gate signal for causing the gate circuit to output a pulse signal corresponding to the energized state according to each output pattern of the latch circuit, and a latch circuit of the latch circuit for each dot A recording head drive device having a gate for inputting to the gate circuit a control signal for controlling an energization time to the recording head according to recording information from another adjacent latch circuit, A semiconductor chip for driving a recording head, characterized in that the information of the last bit and the information of the last bit are set as external input / output terminals. 2. The semiconductor chip for driving a recording head according to claim 1, wherein a pull-down resistor or a pull-up resistor is installed in the external input terminal. 3. The recording head driving semiconductor chip according to claim 1, wherein the external input terminal is provided on a side surface of an end portion of the semiconductor chip. 4. An input / output other than an output pad, wherein a ground pad and all or a part of external input / output terminal pads for the first and last bits of the semiconductor chip pad are integrated, and other input / output pads are integrated. 4. The recording head driving semiconductor chip according to claim 3, wherein the signal pads are divided and arranged. 5. A latch circuit for holding recording information of a current line of a dot to be driven and each recording information of that dot of a previous line, and a gate circuit for outputting a pulse signal indicating a power supply state to a recording head. , A gate signal generator for outputting a gate signal for causing the gate circuit to output a pulse signal corresponding to the energized state according to each output pattern of the latch circuit, and a latch circuit of the latch circuit for each dot And an AND gate for inputting a control signal for controlling the energization time to the recording head to the gate circuit according to recording information from another adjacent latch circuit, and adjacent to the output of the own latch circuit located at the boundary. A recording head drive device characterized in that an external input / output terminal for inputting / outputting recording information from another latch circuit is provided. 6. The recording head drive device according to claim 5, wherein a pull-down resistor or a pull-up resistor is inserted in the external input terminal. 7. A latch circuit for holding the record information of the current line of the dot to be driven and each record information of the dot of the previous line, and a gate circuit for outputting a pulse signal indicating the energization state to the recording head. , A gate signal generator for outputting a gate signal for causing the gate circuit to output a pulse signal corresponding to the energized state according to each output pattern of the latch circuit, and a latch circuit of the latch circuit for each dot And an AND gate for inputting a control signal for controlling the energization time to the recording head to the gate circuit according to the recording information from another adjacent latch circuit, and the latch circuit of each of the dots for each dot. A control signal for controlling an energization time different from the above-mentioned energization time is supplied to the gate according to the record information from the adjacent latch circuit other than the circuit. And an OR gate for inputting to the output circuit, and an external input / output terminal for inputting / outputting recording information from another latch circuit adjacent to the output of the own latch circuit located at the boundary is provided. .. 8. The recording head drive device according to claim 7, wherein a pull-down resistor or a pull-up resistor is inserted in the external input terminal. 9. A latch circuit for holding record information of a current line of a dot to be driven and each record information of a get of a previous line, and a gate circuit for outputting a pulse signal indicating a power supply state to a recording head. , A gate signal generator for outputting a gate signal for causing the gate circuit to output a pulse signal corresponding to the energized state according to each output pattern of the latch circuit, and a latch circuit of the latch circuit for each dot A first AND gate for inputting a control signal for controlling the energization time to the recording head to the gate circuit according to recording information from another adjacent latch circuit, and the latch circuit for each dot. , A control signal for controlling an energization time different from the above energization time according to past record information from other adjacent latch circuits except the own latch circuit. A second AND gate for inputting the signal to the gate circuit, and an external input / output terminal for inputting / outputting recording information from another latch circuit adjacent to the output of the own latch circuit located at the boundary is provided. And a recording head drive device. 10. The recording head drive device according to claim 9, wherein a pull-down or pull-up resistor is inserted in the external input terminal. 11. A latch circuit for holding recording information of a current line of a dot to be driven and each recording information of that dot of a previous line, and a gate circuit for outputting a pulse signal indicating an energized state to a recording head. , To the gate circuit,
A gate signal generator that outputs a gate signal that outputs a pulse signal corresponding to the energized state according to each output pattern of the latch circuit, and a latch circuit for each dot, which includes a self-latch circuit and another adjacent one. According to the recording information from the latch circuit, a control signal for controlling the energization time to the recording head is input to the gate circuit, and the output from its own latch circuit located at the boundary is provided from the other latch circuit adjacent to the output. A recording head driving device comprising a semiconductor chip provided with external input / output terminals capable of inputting / outputting recording information, wherein a pattern pad adjacent to a pad of the semiconductor chip corresponding to the external input / output terminal is a boundary between adjacent semiconductor chips. Recording head, characterized in that the input part and the output part of the external input / output terminal are connected to the same pattern pad. Drive. 12. The pattern pad is provided on a substrate different from the substrate on which the semiconductor chip is mounted and is connected by wire bonding, and the pattern pad has a small structure. A recording head drive device according to the item. 13. The printed circuit board according to claim 11, wherein the board on which the pattern pad is installed is a printed wiring board.
And a recording head drive device for recording of item 12.