JPH05344164A - Automatic threshold value control circuit - Google Patents

Abstract

PURPOSE:To properly identify and reproduce input data by controlling a threshold value with a signal component from a threshold value for data output and the signal components of threshold values set above and under this threshold value so that the threshold value can be always set at the center of an eye opening. CONSTITUTION:The threshold values for input data output and data output are compared by a first comparator circuit 2, and the output data signals of the same phase and reverse phase are obtained. At the same time, a second comparator circuit 4 compares the input data signal with the first threshold value so as to obtain a first comparative signal, and a third comparator circuit 6 compares the input data signal with the second threshold value so as to obtain a second comparative signal. Then, a signal for setting the first threshold value decided from the output data signal of the reverse phase and the first comparative signal is outputted from a first circuit 8 and at the same time, a signal for setting the second threshold value decided from the data signal of the same phase and the second comparative signal is obtained from a second circuit 10. Corresponding to these signals, a control circuit 12 controls the threshold value for data output at a desired value, the identifying and reproducing operations are properly performed while automatically positioning the threshold value for data output at the center of the eye opening, and code error rate characteristics can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic threshold control circuit capable of automatically setting a threshold used for signal reproduction in an optical repeater or the like to an optimum level.

When transmitting an optical signal through an optical communication path,
It is unavoidable that distortion and attenuation of the optical signal occur in the optical fiber forming the transmission line. Therefore, it is necessary to provide a repeater (see FIG. 5A) in the optical fiber at predetermined intervals (for example, every 40 to 60 km) to reproduce the optical signal.

[0003]

2. Description of the Related Art As shown in FIG. 5B, the repeater is a photoelectric conversion element (for example, APD) 100 and an equalizer 1.
02, a timing circuit 104, an identification reproduction circuit 106, and an electro-optical conversion circuit (for example, a laser) 108. The electric signal converted by the photoelectric conversion element 100 is equalized by the equalizer 102 and the clock signal component is regenerated by the equalizer 102. The timing circuit 104 generates a clock signal from the clock signal component. The clock signal is output from the equalizer 102, for example, 200
electrical signal mV _pp is an identification reproducing circuit 106 which receives the clock signal, for example, be the reproduction processing to an electric signal of 800 mV _pp. The reproduced electric signal is converted into an optical signal again by the electro-optical conversion element 108 and transmitted through the optical fiber in the next section.

As shown in FIG. 6, the identification reproduction circuit 106 comprises a slice amplification circuit 110 and a flip-flop circuit 112. The slice amplification circuit 110
6 is composed of a differential amplifier circuit that receives a reference voltage V _ref given by resistance division, and the output signal of the equalizer 102 (for example, the above-mentioned output signal of the equalizer 102 supplied to its data input D _in is shown in FIG. , 200 mV _pp electric signal) is 800 mV between the data output terminal and the inverted data output terminal.
It is amplified to _pp and output. The flip-flop circuit 112 is a master-slave type flip-flop circuit as shown in FIG. In the master-slave type flip-flop circuit, the data set in the master side circuit section 112M in response to the current clock is set in the slave side circuit section 112S in response to the inverted clock of the current clock. Further, the data set in the slave side circuit unit 112S at the clock one clock before the current clock outputs an electric signal of 800 mV _pp between the output terminal and the inverting output terminal by the current clock. The clock signal reproduced by the timing circuit 104 is supplied to the flip-flop circuit together with its inverted clock signal, and an electric signal of 800 mV _pp is output between its data output and its inverted output terminal.

[0005]

In the slice amplifier circuit 110, the electrical signal of 200 mV _pp is 80
Amplifies to an electric signal of 0 mV _pp , but its reference voltage V
_{When ref} does not change, the reference voltage V _ref is at the center level of the input data and performs a normal identification operation as shown in (1) of FIG.

However, the reference voltage may fluctuate from an appropriate reference level due to a factor of fluctuation of the reference voltage such as temperature change and aging change. Due to this fluctuation, the input signal is inverted and output, and as a result, the identification / reproduction circuit 106 malfunctions.

Therefore, even in the conventional case, in order to prevent the reference voltage from fluctuating due to a temperature change, an electric element having an inverse characteristic to the temperature gradient of the resistance dividing circuit for setting the reference voltage is provided in the resistance dividing circuit. Is provided to suppress the fluctuation.

According to this reference voltage fluctuation suppression method, the input
The function is not effective against the fluctuation of the data level.
Yes. For example, as shown in (2) of FIG.
Voltage V _refIs approaching and noise is on the input data
In some cases, as shown in (3) of FIG. 8, the reference voltage goes to the “0” side.
V_refIs approaching and noise is on the input data
The input signal is inverted and output.
As a result, the identification / reproduction circuit 106 malfunctions.

The present invention has been made in view of the above technical problem, and provides an automatic threshold control circuit capable of always automatically setting the reference voltage to the center of the eye opening even when a reference voltage fluctuation factor occurs. Is its purpose.

[0010]

FIG. 1 shows a block diagram of the principle of the invention according to claims 1 to 3. The invention according to claim 1 is, as shown in FIG. 1A, a first comparison circuit 2 that compares an input data signal with a data output threshold value and outputs an in-phase and anti-phase output data signal. And a first higher than the input data signal and the data output threshold
The second comparison circuit 4 that outputs the first comparison output signal of the same phase by comparing the input data signal with the second threshold value lower than the data output threshold value. Third comparison circuit 6 which outputs the second comparison output signal having the opposite phase
A first circuit 8 for outputting a signal for setting a first threshold value determined by the output data signal of the opposite phase and the first comparison output signal; the output data signal of the positive phase and the second circuit 8; A second circuit 10 for outputting a signal for setting a second threshold value determined by the comparison output signal of (1), and a signal for setting the first and second threshold values to receive the data output threshold value. And a control circuit 12 for controlling the value of.

According to a second aspect of the present invention, as shown in FIG. 1A, in the automatic threshold control circuit according to the first aspect, the first circuit 8 has an opposite phase output data signal and a first phase. First adder circuit, second circuit 1 for adding comparison output signals
0 is a second addition circuit that adds the output data signal of the opposite phase and the second comparison output signal, and the control circuit 12 is predetermined as the average value of the first addition circuit and the average value of the second addition circuit. A circuit for generating a signal for setting the first and second threshold values based on the difference from the reference value and controlling the data output threshold value to a desired value.

According to a third aspect of the present invention, as shown in FIG. 1B, in the automatic threshold control circuit according to the first aspect, the data output threshold of the first comparison circuit 2 is the first threshold. The threshold value and the second threshold value are divided and set by resistors 13 and 15 having a constant ratio.

[0013]

According to the first aspect of the present invention, the first comparison circuit 2 compares the input data output with the data output threshold value and outputs the in-phase and anti-phase output data signals. In parallel with this, the second comparison circuit 4 compares the input data signal with the first threshold value to output the first comparison signal, and the third comparison circuit 6 outputs the input data signal and the second threshold value. Are compared with each other and a second comparison signal is output.

A first signal is a signal for setting a first threshold value determined by the output data signal having the opposite phase and the first comparison signal.
The second circuit 10 outputs a signal for setting a second threshold value determined by the output data signal having the same phase and the second comparison signal.

The signal for setting the first and second threshold values is used by the control circuit 12 to control the data output threshold value to a desired value. By this control, the data output threshold value is automatically positioned at the center of the eye opening, and the identification / reproduction operation is correctly performed.

Since this operation is automatically performed by the identification / reproduction circuit in a state where the repeater or the like is installed, adjustments at the time of shipment of the repeater or the like are unnecessary. The automatic adjustment action of the data output threshold value to the center of the eye opening can alleviate the interface condition and improve the code error rate characteristic.

[0017]

2 is a diagram showing a part of a repeater incorporating an automatic threshold control circuit according to the first to third aspects of the present invention. In FIG. 2, 17 is an automatic threshold control circuit, 18 is an input buffer, and 19 is an identification reproduction circuit. The circled terminals in these circuits indicate that they are in the opposite phase (inverted) with respect to the signals of the terminals not circled. The input buffer 18 is a circuit that generates in-phase and anti-phase clocks for the input clock thereto. The identification reproduction circuit 19 is almost the same as the identification reproduction circuit of FIG. 7, and receives the reference input Vref from the input circuit so as to receive the output data signal (described later) of the opposite phase of the automatic threshold control circuit 17. It is configured by excluding R1 and R2.

FIG. 3 shows the automatic threshold control circuit 17 shown in FIG.
Shows the configuration of. In FIG. 3, reference numerals 20, 22, and 24 are first, second, and third comparison circuits, respectively. The first comparison circuit 20 has an input data signal and a data output threshold V.
The output data signal (S1) having the same phase and the output data signal (S1 ') having the opposite phase are generated by comparing with _ref1 . The in-phase output data signal (S1) is the same as the identification / reproduction circuit 19
Of the output data signal (S
1 ') is supplied to the anti-phase input of the above-mentioned identification reproduction circuit 19. The data output threshold V _ref1 is the first reference voltage V
In _ref2 and second reference voltage difference resistor 21 and the voltage generated by the resistor divided by the resistance 23 with the V _ref3, 2 minutes of the difference between the first reference voltage V _ref2 and second reference voltage V _ref3 It is 1. Here, the output data signal having the same phase means that the signal resulting from the comparison between the data output threshold value V _ref1 and the input data signal has the same phase as the input data signal. The output data signal of the opposite phase is the data output threshold value V _ref1.
And the input data signal is in the opposite phase with the input data signal. Second comparison circuit 22
Generates an output data signal (S2) having the same phase as the input data signal by comparing the input data signal with a first threshold value higher than the data output threshold value V _ref1 by a predetermined value.
The third comparison circuit 24 compares the input data signal with a second threshold value lower than the data output threshold value V _ref1 by a predetermined value, and outputs an output data signal (S3 ′) having a phase opposite to that of the input data signal. Occur.

Reference numeral 26 denotes a first adder circuit, which has an opposite phase output data signal output from the first comparator circuit 20,
This is a circuit for obtaining the sum (S4) with the output data signal of the same phase output from the second comparison circuit 22. 28 is
In the second adding circuit, the in-phase output data signal output from the first comparing circuit 20 and the third comparing circuit 2
Sum of the output data signal of the opposite phase output from
This is a circuit for obtaining 5).

Reference numerals 30 and 32 denote first and second low pass filters (LPF1 and LPF2), respectively. The first low pass filter 30 is an average value (S4 of the output signals of the first adder circuit 26). ') And outputs the second low-pass filter 3
2 is the average value of the output signals of the second adding circuit 28 (S
5 ') is output.

Reference numerals 34 and 36 denote first and second differential amplifier circuits (AMP1 and AMP2), respectively, and the first differential amplifier circuit 34 is an average value of the low-pass filter 30 and a predetermined reference. A value obtained by multiplying the difference from the voltage V _ref [(S6)] by a predetermined coefficient is output. The second differential amplifier circuit 36 outputs a value obtained by multiplying the difference between the predetermined reference voltage V _ref and the average value of the low pass filter 30 by a predetermined coefficient.

In FIG. 3, a first comparison circuit 20 corresponds to the first comparison circuit 2 of FIG. 1 and a second comparison circuit 22.
Corresponds to the second comparison circuit 4 of FIG. 1, and the third comparison circuit 24 corresponds to the third comparison circuit 6 of FIG. The first adder circuit 26 corresponds to the first circuit 8 in FIG. 1, and the second adder circuit 28 corresponds to the first circuit 10 in FIG. The first low pass filter 30 and the first differential amplification circuit 34, the first low pass filter 32 and the first differential amplification circuit 36, and the resistors 21 and 23 are the control circuit 12 of FIG.
Corresponding to.

Next, the operation of the circuit configured as described above will be described below.
explain. Input data signal without noise (Fig. 4
(Refer to the waveform signal without the shaded area in (1))
Then, the input data signal is supplied to the first to third comparison circuits.
And the data output threshold V_ref1, The first reference voltage V
_ref2And the second reference voltage V _ref3Compared to. This comparison
Thus, the output data of the same phase is output from the first comparison circuit 20.
Signal (see (S1) of (3) in FIG. 4) and the opposite phase
Output data signal (see (S1 ') in (2) of Fig. 4)
The second comparison circuit 22 generates the output data of the same phase.
Signal (see (S2) in (3) of FIG. 4) is generated,
Then, the output data signal of the opposite phase is output from the third comparison circuit 24.
No. (see (S3 ′) in (3) of FIG. 4) is generated. Na
Incidentally, ‘1’ and ‘0’ in FIG. 4 are binary signals.
High and low levels are shown.

The addition of the output data signal (S1 ') of the opposite phase from the first comparison circuit 20 and the output data signal (S2) of the same phase from the second comparison circuit 22 is performed by the first addition circuit 26. The average value of the sum output signal (S4) is output from the first low-pass filter 30 (see (4) (A) in FIG. 4). Low-pass filter 3 at this time
2 average value (S4 ') and the predetermined reference voltage V
A value obtained by multiplying the difference from _ref by a predetermined coefficient is output from the first differential amplifier circuit 34. The value is exactly the desired value as shown in (A ') of (6) of FIG. First reference voltage V
Set to a voltage equal to _ref2 . Similarly, the in-phase output data signal from the first comparison circuit 20 and the opposite-phase output data signal from the third comparison circuit 24 are added by the second addition circuit 28, The average value of the sum output signal (S5) is output from the second low-pass filter 32 (see (5) (B) in FIG. 4). A value obtained by multiplying the difference between the average value (S5 ′) of the low pass filter 32 and the predetermined reference voltage V _{ref at} this time by a predetermined coefficient is output from the second differential amplifier circuit 36. , Its value is set to a voltage equal to the desired second reference voltage V _ref3 , as shown in (B ′) of (7) of FIG.
Therefore, the first reference voltage V _ref1 is V _ref2 + V _ref3 /
The second reference voltage V _ref1 set to 2 is set to a desired value.

However, noise is added to the "1" side of the input data, and the addition signal of the first comparison circuit 22 becomes (2) in FIG.
As shown in (4), when the eye opening is crushed, the output signal from the first addition circuit 26 has a waveform as shown in (A _N ) of (4) of FIG. 4, and is output from the low-pass filter 30. Since the averaged value decreases as shown in (A _N ′) of (6) of FIG. 4, the voltage that decreases the first reference voltage V _ref2 by the voltage corresponding to the decrease is the first. It is generated from the differential amplifier circuit 34. Therefore, the first reference voltage V
_ref1 is moved to the center of the eye opening.

When noise is added to the "0" side of the input data and the addition signal of the third comparison circuit 24 is crushed by the eye opening as shown in (3) of FIG. Adder circuit 2
The output signal from 8 has a waveform as shown in (B _N ) of (5) of FIG. 4, and the average value output from the low-pass filter 32 is (B _N ′) of (7) of FIG. Therefore, the voltage that increases the third reference voltage V _ref3 by the voltage corresponding to the decrease is the second differential amplifier circuit 36.
Is generated from. Therefore, also in this case, the first reference voltage V _ref1 is moved to the center of the eye opening.

While the threshold control as described above is applied,
Output data D _out and D _out are output from the first comparison circuit 20 and are supplied to the identification reproduction circuit composed of the flip-flop circuit shown in FIG. 7 to perform identification reproduction of the input data.

The DC level of the input data and / or the reference voltage is changed due to a change in temperature, a change in the power supply voltage, etc. in addition to the case where noise is added to the "1" side or "0" side of the input data as described above. Even when is changed, it is possible to prevent the above-mentioned malfunction of the identification reproduction circuit.

Although the above embodiment is an embodiment of the identification and regeneration circuit of the repeater of the optical transmission line, it may be implemented in a circuit that requires other threshold values. For example, in an optical receiver of an optical communication system, a light receiving element (A
The present invention can also be applied to the case where noise is added to the received data due to noise such as DP, or the input light level of the optical receiver is attenuated.

[0030]

As described above, according to the present invention, the signal component obtained for the data output threshold and the signal component obtained for the threshold provided above and below the data output threshold are used for the data output. Since the threshold value is automatically set to the center of the eye opening when controlling the threshold value, the input data is identified and reproduced while eliminating the effects of noise on the input data, temperature changes, power supply voltage changes, etc. Etc. can be done correctly. Since the automatic setting is performed during the operation of the apparatus, adjustment at the time of shipment is not necessary, it is useful for alleviating the interface condition, and the code error rate characteristic is improved.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the invention according to claims 1 to 3.

FIG. 2 is a diagram showing a part of a repeater incorporating the automatic threshold control circuit of the invention according to claims 1 to 3;

FIG. 3 is a configuration diagram of an automatic threshold control circuit.

FIG. 4 is a signal waveform diagram of each part in the automatic threshold control circuit.

FIG. 5 is a diagram showing a configuration of an optical transmission system and a repeater thereof.

FIG. 6 is a configuration diagram of an identification reproduction circuit.

FIG. 7 is a diagram showing a flip-flop circuit in a conventional identification reproduction circuit.

FIG. 8 is a signal waveform diagram for explaining the operation of a conventional identification / reproduction circuit.

[Explanation of symbols]

 2 1st comparison circuit 4 2nd comparison circuit 6 3rd comparison circuit 8 1st circuit 10 2nd circuit 12 control circuit 20 1st comparison circuit 22 2nd comparison circuit 24 3rd comparison circuit 26 First addition circuit 28 Second addition circuit 30 First low-pass filter 32 Second low-pass filter 34 First operational amplifier circuit 36 Second operational amplifier circuit

Claims (3)

[Claims] 1. A first comparison circuit (2) for comparing an input data signal and a data output threshold value and outputting an output data signal of the same phase and an opposite phase, said input data signal and said data output A second comparison circuit (4) for comparing a first threshold value higher than a threshold value and outputting a first comparison output signal of the same phase; the input data signal; and a second lower value than the data output threshold value. A third comparison circuit (6) which compares the second threshold value with the second threshold value and outputs a second comparison output signal having an opposite phase; and a first comparison output signal which is determined by the output data signal having the opposite phase and the first comparison output signal. A first circuit (8) for outputting a signal for setting a threshold, and a first circuit (8) for outputting a signal for setting a second threshold determined by the output data signal of the positive phase and the second comparison output signal. A second circuit (10) for setting the first and second thresholds Automatic threshold control circuit, characterized in that said data output threshold in response to a signal for providing a control circuit for controlling to a desired value (12). 2. The automatic threshold control circuit according to claim 1, wherein the first circuit (8) adds a reverse phase output data signal and a first comparison output signal, and a second addition circuit. The circuit (10) is a second adder circuit for adding the output data signal of the opposite phase and the second comparison output signal, and the control circuit (12) is the average value of the first adder circuit and the average value of the second adder circuit. And a reference value determined in advance to generate a signal for setting the first and second threshold values and control the data output threshold value to a desired value. circuit. 3. The automatic threshold value control circuit according to claim 1, wherein the data output threshold value of the first comparison circuit (2) is a constant ratio of resistors 13 and 15 between the first threshold value and the second threshold value. An automatic threshold control circuit characterized by being set separately.