JPH05344036A - Simultaneous command reply collection system - Google Patents

Simultaneous command reply collection system

Info

Publication number
JPH05344036A
JPH05344036A JP17204892A JP17204892A JPH05344036A JP H05344036 A JPH05344036 A JP H05344036A JP 17204892 A JP17204892 A JP 17204892A JP 17204892 A JP17204892 A JP 17204892A JP H05344036 A JPH05344036 A JP H05344036A
Authority
JP
Japan
Prior art keywords
polling
clock
period
reply
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17204892A
Other languages
Japanese (ja)
Inventor
Noboru Nakamura
襄 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP17204892A priority Critical patent/JPH05344036A/en
Publication of JPH05344036A publication Critical patent/JPH05344036A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To collect a correct order of a reply station signal by generating a clock pulse of the same period as a polling period synchronously with polling and a clock pulse synchronously with the first polling signal and using a period for circulation of polling as a period and using the clock pulses as the reference pulses. CONSTITUTION:A reply signal 6 is received sequentially in time division by a channel section 1, the sequence is discriminated and the result is sent to a system control section 2. In this case, two kinds of clock pulses are sent to the channel section 1 from the system control section 2. The one pulse is generated synchronously with polling and has a same period as the polling as an A clock 4 and the other pulse is a B clock 5 synchronously with the initial polling whose period is equal to a period between the first polling and the last polling. That is, The reply sequence is normally recognized by the A clock 4 and the count of reply sequence is initialized by using the B clock 5. Thus, no discrepancy relating to a reply station between channels is caused.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は無線システムにおける一
斉指令通報に対する端末局応答の収集方式に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of collecting terminal station responses to a simultaneous command notification in a wireless system.

【0002】[0002]

【従来の技術】従来,一斉指令通報に対する端末局の応
答信号が時分割により順次受信される場合,その順番に
よって端末局を割出している。すなわち,得られる応答
信号を計数することによって順番を判定している。この
場合,応答信号の抜け発生により,正しい順番が得られ
ない場合が起こる。
2. Description of the Related Art Conventionally, when the response signals of the terminal stations to the simultaneous command notification are sequentially received by time division, the terminal stations are indexed according to the order. That is, the order is determined by counting the obtained response signals. In this case, the correct order may not be obtained due to missing response signals.

【0003】[0003]

【発明が解決しようとする課題】前述の従来方式では,
応答局数が少なく,かつ収集時間が長い場合問題は発生
しないが,複数チャネルによる同時ポーリング時のよう
に応答局数が多く,かつ収集時間が短い場合,応答局の
判定ミスが発生しやすいという問題がある。本発明はこ
れらの問題を解決し,応答局信号の正しい順番を認識し
収集できるようにすることを目的とする。
In the above-mentioned conventional method,
If the number of responding stations is small and the collection time is long, no problem will occur. However, if the number of responding stations is large and the collection time is short, such as when polling multiple channels at the same time, it is easy to make an error in determining the responding stations There's a problem. It is an object of the present invention to solve these problems so that the correct sequence of responder signals can be recognized and collected.

【0004】[0004]

【課題を解決するための手段】本発明は,上記目的を達
成するため,ポーリングに同期した二種類のクロックパ
ルスを発生させる。1つは,ポーリングに同期し周期は
ポーリング周期と同じもの,もう1つは,最初のポーリ
ングに同期し,周期は最初と最後のポーリング間隔すな
わち,ポーリングが一巡する期間のものである。前者の
クロックパルスはポーリングに指定されたグループ内の
応答信号の順序を正しく認識するための基準パルス,後
者はポーリングの開始を知らせる基準パルスで,順序計
数の初期化を知らせるものである。
In order to achieve the above object, the present invention generates two kinds of clock pulses synchronized with polling. One is in synchronization with polling and the cycle is the same as the polling cycle. The other is in synchronization with the first polling and the cycle is the first and last polling intervals, that is, the period in which the polling completes one cycle. The former clock pulse is a reference pulse for correctly recognizing the order of the response signals in the group designated for polling, and the latter is a reference pulse for notifying the start of polling and notifying the initialization of the sequence counting.

【0005】[0005]

【作用】この二種のクロックパルスの発生により,応答
局数が多く収集時間が短い場合でも応答信号に対する端
末局の割出しが正常に実行できる。
By generating these two kinds of clock pulses, the terminal station can be normally indexed to the response signal even when the number of response stations is large and the collection time is short.

【0006】[0006]

【実施例】以下,この動作について図1,2を用いて説
明する。図1は本発明を説明するためのブロック図,図
2はポーリング信号と2つのクロック信号のタイムチャ
ートである。応答信号6はチャネル部1に時分割で順次
受信される。応答信号はチャネル部1で順番を判定さ
れ,一定のフォーマットに変換され,系制御部2に送信
される。チャネル部1と系制御部2の伝送路は有線であ
る。この場合,系制御部2からチャネル部1へ直接二種
類のクロックパルスが供給される。1つは系制御部で指
令されるポーリングに同期して発生し,周期はポーリン
グとポーリングの期間に等しいAクロック4,もう1つ
は最初のポーリングに同期し周期が最初のポーリングと
最後のポーリングの期間に等しいBクロック5である。
EXAMPLE This operation will be described below with reference to FIGS. FIG. 1 is a block diagram for explaining the present invention, and FIG. 2 is a time chart of a polling signal and two clock signals. The response signal 6 is sequentially received by the channel unit 1 in a time division manner. The order of the response signal is determined by the channel unit 1, converted into a fixed format, and transmitted to the system control unit 2. The transmission lines of the channel unit 1 and the system control unit 2 are wired. In this case, two types of clock pulses are directly supplied from the system control unit 2 to the channel unit 1. One occurs in synchronization with the polling commanded by the system control unit, the cycle is equal to the polling and polling period A clock 4, and the other is in synchronization with the first polling and the cycle is the first polling and the last polling. B clock 5 equal to the period.

【0007】Aクロック4によって,ポーリング信号3
で指定されたグループ内の応答順番を正常に認識でき
る。また,Bクロック5にて応答順番の計数の初期化を
する。A,Bクロックとも,すべてのチャネル部に供給
される。これは,一斉指令の応答を収集する応答信号の
チャネルがその都度移動すること,応答が2つのチャネ
ルを使用して受信していることによる。この場合,チャ
ネル間の処理時間の差によって両者の応答局の認識が矛
盾することが無い。
Polling signal 3 by A clock 4
The order of responses within the group specified by can be recognized normally. Also, the counting of the response order is initialized by the B clock 5. Both the A and B clocks are supplied to all channel parts. This is because the channel of the response signal that collects the response to the simultaneous command moves each time, and the response is received using two channels. In this case, the recognition of both responding stations does not contradict due to the difference in processing time between channels.

【0008】[0008]

【発明の効果】本発明によれば,応答収集局数の拡大,
収集時間の圧縮が可能である。また,応答信号の受信チ
ャネルを増加した場合,チャネル間の応答局に関する矛
盾は発生しない。
According to the present invention, the number of response collecting stations can be increased.
The collection time can be compressed. In addition, when the number of response signal reception channels is increased, no contradiction occurs regarding the response station between channels.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を示すブロック図である。FIG. 1 is a block diagram showing the present invention.

【図2】クロックパルスのタイムチャートである。FIG. 2 is a time chart of clock pulses.

【符号の説明】[Explanation of symbols]

1 チャネル部 2 系制御部 3 ポーリング信号 4 局順位判定用基準クロック(Aクロック) 5 ポーリング開始基準クロック(Bクロック) 6 応答信号 1 channel section 2 system control section 3 polling signal 4 station order determination reference clock (A clock) 5 polling start reference clock (B clock) 6 response signal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ポーリングにより指定したグループに属
する端末局から,時分割により順次送出される応答信号
を収集する応答収集方式において,ポーリングに同期し
ポーリング周期と同一周期のクロックパルスと,最初の
ポーリング信号に同期しポーリングが一巡する期間を周
期とするクロックパルスとを発生させ,これら2種類の
クロックパルスを基準として応答信号の順序を誤りなく
認識し収集するようにしたことを特徴とする一斉指令応
答収集方式。
1. A response collecting method for collecting response signals sequentially transmitted in a time division manner from terminal stations belonging to a group designated by polling, in a polling period, a clock pulse having the same period as a polling period, and a first polling. Synchronous command characterized by generating a clock pulse which is synchronized with the signal and whose period is one cycle of polling, and recognizes and collects the order of response signals without error based on these two types of clock pulses. Response collection method.
JP17204892A 1992-06-05 1992-06-05 Simultaneous command reply collection system Pending JPH05344036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17204892A JPH05344036A (en) 1992-06-05 1992-06-05 Simultaneous command reply collection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17204892A JPH05344036A (en) 1992-06-05 1992-06-05 Simultaneous command reply collection system

Publications (1)

Publication Number Publication Date
JPH05344036A true JPH05344036A (en) 1993-12-24

Family

ID=15934572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17204892A Pending JPH05344036A (en) 1992-06-05 1992-06-05 Simultaneous command reply collection system

Country Status (1)

Country Link
JP (1) JPH05344036A (en)

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