JPH05343614A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To ensure or increase capacitance without decreasing the thickness of storage capacitor insulating film of a stacked capacitor cell. CONSTITUTION:An alloy film (1-8) containing silicon is formed on a polycrystalline silicon film (1-7) turning to a first storage capacitor electrode. By heat-treating the alloy film, silicon nodules (1-9) are segregated. By using the nodules (1-9), the surface of the polycrystalline silicon film (1-7) is roughened, so that the electrode surface area is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a charge storage node in a semiconductor device.

[0002]

2. Description of the Related Art A stacked capacitor cell is known in which a memory cell area is reduced by forming a storage capacitor on a select transistor, a bit line, or an element isolation region by using a three-layer polycrystalline silicon technique. ing.

A conventional method of forming the charge storage node will be described with reference to FIG.

FIG. 3A shows a cell storage node formed by depositing an insulating film on a gate wiring of a DRAM having an LDD type transistor structure, opening a cell contact hole, and diffusing phosphorus into polycrystalline silicon. FIG.

Here, 2-1 is a silicon single crystal substrate, 2-2 is a field oxide film for element isolation having a thickness of 6000Å, 2-3 is a gate oxide film having a thickness of 200Å, and 2-4 is polycrystalline silicon. Gate wiring with a thickness of 4000 Å diffused in phosphorus, PSG (phospho silicon)
3,000 Å thick gate sidewall by te glass, 2-6 is NSG (non-doped-s)
An interlayer insulating film having a thickness of 2000 Å is formed of an ilicate glass, and 2-7 is polycrystalline silicon having a thickness of 2000 Å diffused by phosphorus, and forms one storage capacitor electrode.

Next, as shown in FIG. 3B, a nitride film 2-8, which is a storage capacitor insulating film and is a dielectric having a thickness of 100 Å, is formed.
Then, depressurize the polycrystalline silicon 2-9 with a thickness of 2500Å C
The other storage capacitor electrode is formed by depositing by the VD method, diffusing phosphorus into the polycrystalline silicon 2-9, and then patterning.

Next, as shown in (c), a 5000 Å-thick BPSG (phosphopho sili) which is an interlayer insulating film.
Cate glass) 2-10 is deposited, and a glass flow is performed in a nitrogen atmosphere at 900 ° C. to flatten the surface.
Then, a contact hole is opened to form an Al wiring 2-11 having a bit line thickness of 6000Å.

[0008]

However, in the method of forming the charge storage region described above, the reduction of the capacitance due to the reduction of the cell area due to the high integration of the LSI is compensated.
The film thickness of the nitride film 2-8, which is a dielectric, must be reduced. However, if the film thickness of the nitride film 2-8 is reduced, the leak current in the cell increases, and there is a problem in thinning the nitride film.

It is an object of the present invention to solve the above-mentioned problem of the decrease in capacitance due to the decrease in the area of the charge storage portion without depending on the decrease in the film thickness of the nitride film.

[0010]

According to the present invention, in the method of manufacturing a stacked capacitor cell, the surface of the charge storage node is roughened to increase the electrode surface area. An alloy containing silicon is deposited on the charge storage node, and single crystal silicon nodules or solid solutions are segregated in the alloy, and then the alloy is etched away to remove the surface of the charge storage node from the rough surface of the remaining silicon nodules. Turn into.

[0011]

The surface area increased by roughening the surface of the charge storage node makes it possible to increase the capacitance without decreasing the dielectric film thickness.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

FIG. 1A shows that an insulating film is deposited on a gate wiring of a DRAM having an LDD type transistor structure, a contact hole is opened, and then polycrystalline silicon, which will be a charge storage node of a stacked capacitor cell, is deposited. FIG.

In FIG. 1A, 1-1 is a silicon single crystal substrate, 1-2 is a field oxide film having a thickness of 6000 Å for element isolation, 1-3 is a gate oxide film having a thickness of 200 Å, 1-4 Is a thickness of 40 diffused with phosphorus in polycrystalline silicon.
00 Å gate wiring, 1-5 is a 3000 Å thick gate sidewall (PSG), 1-6 is a 2000 Å thick interlayer insulating film (NSG), and 1-7 is 2000 Å thick polycrystalline silicon.

As shown in FIG. 1B, an Al--Si--Cu alloy or the like having a thickness of 4000 is formed on this wafer by a sputtering method.
Deposit as a film 1-8 of Å. Next, this film 1-8 is formed by, for example, R.M. T. A. Using (Rapid Thermal Annealing), heat treatment is performed at a temperature of 400 to 450 ° C. for about 1 to 2 minutes to segregate the single crystal silicon nodules or solid solution in the film 1-8.

Next, as shown in FIG.
The l alloy is removed by etching using 5% hydrochloric acid or the like so that the solid solution segregated within the alloy or the silicon nodules 1-9 remains. Then polycrystalline silicon layer 1
-7 and silicon nodules 1-9 diffuse phosphorus into silicon.

Next, as shown in FIG. 1D, photolithography and etching are performed to form one storage capacitor electrode of the charge storage node having irregularities by the silicon nodules 1-9.

Then, as shown in FIG. 1 (e), a nitride film 1 as a dielectric having a thickness of 100 Å is formed on the charge storage node.
-10 is formed as a storage capacitor insulating film, and polycrystalline silicon 1-11 having a thickness of 2500 Å to be the other storage capacitor electrode is deposited thereon by a low pressure CVD method to form a phosphorus on the polycrystalline silicon layer 1-11. After diffusion, patterning is performed to form a cell plate.

Next, as shown in FIG. 1 (f), a thickness of 5000
An interlayer insulating film (BPSG) 1-12 of Å is deposited by a normal pressure CVD method, and a glass flow is performed in a nitrogen atmosphere at 900 ° C. to flatten it. After that, a contact hole is opened to form an Al wiring 1-13 having a bit line thickness of 6000Å.

The rough surface of the polycrystalline silicon layer 1-7 can be implemented by other methods. An example thereof is shown in FIG. 2 (d) '-2 (f)'.
The example will be described. This method is a method in which the silicon nodules 1-9 shown in FIG. 1 (c) are used as a mask to roughen the polycrystalline silicon 1-7 serving as a capacitor node.

Polycrystalline silicon layer 1- in FIG. 1 (c)
7 and silicon nodule 1-9 before the diffusion of phosphorus into silicon nodule 1-9 and polycrystalline silicon 1-7 using silicon nodule 1-9 as a mask.
The entire surface is etched by an iv ion etching) method to roughen the polycrystalline silicon 1-7, and then, as shown in FIG.
After obtaining the structure shown in FIG. 3, phosphorus is diffused in the polycrystalline silicon layer 1-7.

Next, as shown in FIG. 2 (e) ', the thickness 100
A Å dielectric nitride film 1-10 and a 2500 Å thick polycrystalline silicon 1-11 are deposited by a low pressure CVD method, and phosphorus diffusion is performed to perform patterning to form a cell plate.

Next, as shown in FIG. 2 (f) ', the thickness 500
An interlayer insulating film (BPSG) 1-12 of 0 Å is deposited by the atmospheric pressure CVD method, and a glass flow is performed in a nitrogen atmosphere at 900 ° C. to flatten it. After that, a contact hole is opened to form an Al wiring 1-13 having a bit line thickness of 6000Å.

[0024]

As described above, according to the method of forming the electrode of the charge storage node of the present invention, an alloy film containing silicon is deposited on the surface of the electrode, and then silicon oxide is formed in the layer by appropriate heat treatment. After that, the alloy layer is etched so that the silicon nodules are left to deposit the silicon nodules on the electrode surface, or the silicon nodules on the surface are used as a mask to etch the lower electrode, so that the surface area of the electrode is doubled. And above,
It is not necessary to reduce the film thickness of the nitride film that becomes the dielectric.
Therefore, it is possible to realize a highly reliable capacitor having a large capacitance and a small leak current.

[Brief description of drawings]

FIG. 1 is a diagram showing a process of one embodiment of the present invention.

FIG. 2 is a diagram showing a process of another embodiment of the present invention.

FIG. 3 is a diagram showing a conventional method.

[Explanation of symbols]

 1-1 Silicon substrate 1-2 Field oxide film 1-3 Gate oxide film 1-4 Gate wiring 1-5 Side wall 1-6 Interlayer insulating film 1-7 Polycrystalline silicon film 1-8 Silicon alloy film 1-9 Silicon nodule 1-10 Storage Capacitance Insulating Film 1-11 Polycrystalline Silicon Film 1-12 Interlayer Insulating Film 1-13 Aluminum Wiring

Claims (3)

[Claims] 1. A method of forming a charge storage node, which comprises the following steps in manufacturing a semiconductor device: depositing an alloy film containing silicon on the surface of a polycrystalline silicon film; heat treating the alloy film. Segregating single-crystal silicon nodules or solid solutions in the alloy film by: roughening the surface of the polycrystalline silicon film using the segregated silicon nodules or solid solutions; the roughened polycrystals Forming a first storage capacitor electrode by diffusing phosphorus on the surface of the silicon film: forming a storage capacitor insulating film on the first storage capacitor electrode; forming a second storage capacitor electrode on the storage capacitor insulating film Stage to do. 2. The roughening step of the surface of the polycrystalline silicon film using the silicon nodule removes the alloy film by etching so as to leave a silicon nodule or a solid solution formed by heat treatment of the silicon alloy film. The method of claim 1 including the steps. 3. The roughening step of the surface of the polycrystalline silicon film using the silicon nodules, the alloy films are removed by etching so as to leave silicon nodules or solid solutions formed by heat treatment of the silicon alloy films. 2. The method of claim 1 including the steps of: and etching the entire surface of the polycrystalline silicon film having the silicon nodules thus left on its surface until the silicon nodules are removed.