JPH05342856A - Random access semiconductor memory device - Google Patents

Abstract

PURPOSE:To make the simultaneous reading of plural random access semiconductor memory devices possible by individually providing a reading control circuit or a writing control circuit at each data input and output terminal. CONSTITUTION:In a writing cycle, a writing control WE terminal 1.4 is turned to an L after an address input, so that data can be written in a memory cell selected by an input address among a memory cell array 1.11. On the other hand, entire four reading control OE1-OE4 terminals 1.5 are turned to the L after a memory cell selection, so that a reading cycle using entire four data input and output DQ1-4 terminals 1.6 can be attained. And also, at the time of outputting the data only from one part of the DQ1-DQ4 terminals 1.6, the reading control terminal corresponding to the terminal which outputs the data among the OE1-OE4 terminals 1.6 is turned to the L.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access semiconductor memory device.

[0002]

2. Description of the Related Art In general, a semiconductor memory device is one in which a selected address is input from the outside and a signal is input to a control terminal to write or read to a memory cell of the selected address.

In the case of a dynamic random access semiconductor memory device, as a signal for fetching an address,
ROW address strobe (RAS) terminal and COLUM
It has an N address strobe (CAS) terminal, and further, a write control (WE) terminal controls writing, and a read control (OE) terminal controls reading.

FIG. 9 is a block diagram showing a configuration of a conventional dynamic random access semiconductor memory device having four data input / output terminals, and FIG. 10 is a timing diagram of a write cycle and a timing diagram of a read cycle. Details of the conventional example will be described.

In FIG. 9, 9.1 is a RAS terminal, and 9.
2 is a CAS terminal, 9/3 is an address terminal, and 9/4 is WE
Terminal, 9/5 is OE terminal, 9/6 is data input / output (DQ
1 to DQ4) terminals, 9 and 7 are ROW address buffers,
9/8 is a COLUMN address buffer, 9/8 is RO
W decoder, 9/10 is a COLUMN decoder, 9.1
Reference numeral 1 is a memory cell array, 9 and 12 are write control circuits, 9 and 13 are read control circuits, 9 and 14 are data input buffers, and 9 and 15 are data output buffers.

After the ROW address is given to the address terminal 9/3, the RAS terminal 9/1 is turned off to make the RO
The ROW address is fetched into the W address buffer 9/7, and the memory cell array 9
・ Select the 11th row line (word line). Then CO
The LUMN address is given to the address terminals 9 and 3, and CAS
By taking down the terminal 9 ・ 2, the COLUMN address is fetched into the COLUMN address buffer 9/8,
One column line (bit line) of the memory cell array 9/11 is selected by the COLUMN decoder 9/10. By this operation, an arbitrary memory cell (4 bits) is selected from the memory cell arrays 9 and 11 arranged in a matrix.

In a semiconductor memory device having one data input / output terminal or a semiconductor memory device having one data input terminal and one data output terminal, the memory cell selected by the above operation is 1 bit. However, as shown in FIG. 9, a plurality of data input / outputs (DQ1 to
DQ4) In a semiconductor memory device having terminals 9 and 6, or a semiconductor memory device having a plurality of data input terminals and the same number of data output terminals, the number of memory cells selected by the above operation is a plurality of bits. ..
Up to this point, the read cycle and the write cycle are basically the same.

At this time, as shown in FIG. 10, when the WE terminal 9.4 connected to the write control circuit 9/12 is set to "L", a write cycle starts, and the data input / output terminal 9/6 receives data. The data is fetched into the buffers 9 and 14, and the data is written into the selected memory cell. When the OE terminal 9/5 connected to the read control circuit 9/13 is set to "L", a read cycle is started, and after selecting the memory cell, each bit is output to the data output buffer 9.1.
Data is output from 5.

[0009]

In recent years, with the high integration of semiconductor integrated circuits, the capacity and functionality of semiconductor memory devices have been increasing. Along with this, the systems to which the random access semiconductor memory device is applied are also becoming higher in functionality and performance.

However, in the conventional random access semiconductor memory device, one write control circuit 9, 12 or 1 is used.
Since one read control circuit 9/13 controls the write operation and read operation of the plurality of data input / output terminals 9/6 or the plurality of data input terminals and the same number of data output terminals, all read / write operations are performed. For data input / output terminals or all data input terminals and data output terminals,
You can only write or read at the same time.

For example, as shown in FIG. 11, three random access semiconductor memory devices 11.1-11.3 each provided with four data input / output (DQ1-DQ4) terminals.
When reading data in a system that uses
Data can be read from only one random access semiconductor memory device in one cycle. Therefore, the first and second data lines DATA1, DAT
The data of A2 is D of the first semiconductor memory device 11.1.
From the Q1 terminal and the DQ2 terminal to the third data line DATA
The data of 3 is the DQ of the second semiconductor memory device 11.2.
From the 3rd terminal, the data of the 4th data line DATA4 is the 3rd
When reading from each of the DQ4 terminals of the semiconductor memory device 11.3, the reading operation of 3 cycles had to be performed as shown in FIG.

In FIG. 11, data is read from the DQ1 terminal and DQ2 terminal of the first semiconductor memory device 11.1 and data is read from the DQ3 terminal and DQ4 terminal of the same semiconductor memory device 11.1. 13 to write all data input / output (DQ1 to DQ) of the first semiconductor memory device 11.1 as shown in FIG.
4) After reading from the terminal, the same data as the previously read data is applied to the DQ3 terminal and the DQ2 terminal.
A new write data is given to the terminal and the DQ4 terminal to perform a write cycle, that is, two memory cycles are required.

An object of the present invention is to realize partial reading of data through some of the plurality of data input / output terminals or some of the plurality of data output terminals. It is to enable simultaneous reading of random access semiconductor memory devices. Another object of the present invention is to provide a random access semiconductor memory device having a plurality of data input / output terminals, or a random access semiconductor memory device having a plurality of data input terminals and the same number of data output terminals. It is possible to simultaneously execute the data writing through the terminal and the data reading through the other terminal.

[0014]

In order to solve the above problems, the present invention provides a read control circuit and a write control circuit independently for each terminal of a semiconductor memory device.

Specifically, the invention of claim 1 has a plurality of data input / output terminals, and an independent read control circuit for each data input / output terminal.

The invention of claim 2 has a plurality of data input / output terminals, and an independent read control circuit for each data input / output terminal and an independent write control circuit for each data input / output terminal. It was decided.

The invention of claim 3 has a plurality of data output terminals, and an independent read control circuit for each data output terminal.

According to a fourth aspect of the present invention, a read control circuit having a plurality of data input terminals and the same number of data output terminals, each data output terminal being independent, and each data input terminal being independent. And a write control circuit.

[0019]

According to the first to fourth aspects of the invention, the portion of the data is read through the read control circuit independently provided for each data input / output terminal or the read control circuit independently provided for each data output terminal. Reading can be performed. Therefore, it is possible to simultaneously read a plurality of random access semiconductor memory devices.

In particular, according to the second or fourth aspect of the invention, the configuration is such that an independent write control circuit is provided for each data input / output terminal, or an independent write control circuit is provided for each data input terminal. Data writing through some terminals and data reading from other terminals can be executed simultaneously.

[0021]

Embodiments Hereinafter, four embodiments will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing the configuration of a first embodiment of a random access semiconductor memory device according to the present invention, in which four data input / output (DQ1 to DQ)
4) The terminals 1 and 6 are provided, and the read control circuits 1 and 13 and the read control (OE1 to OE1) are provided independently for each data input / output terminal.
OE4) has terminals 1.5.

The address input method (method of selecting an arbitrary memory cell) in the embodiment of FIG. 1 is the same as the conventional example.

In the write cycle, after address input,
By setting the write control (WE) terminals 1 and 4 to "L", it is possible to write to the memory cell selected by the input address in the memory cell array 1 and 11.

After selecting a memory cell, all four data input / output (DQ1 to DQ4) terminals 1 and 6 are used by setting all four read control (OE1 to OE4) terminals 1 and 5 to "L". The read cycle can be realized. When data is output only from some of the four DQ1 to DQ4 terminals 1 and 6, the data is output to one of the four read control (OE1 to OE4) terminals 1 and 5 to which data is to be output. The corresponding read control terminal is set to "L". "H" of DQ1 to DQ4 terminals 1 and 6
The data input / output terminal corresponding to the read control terminal of 1 remains high impedance.

For example, as shown in the left half of FIG.
If you want to output data only from 1 terminal and DQ3 terminal, set OE1 terminal and OE3 terminal of OE1 to OE4 terminals 1 and 5 to "L" and leave OE2 terminal and OE4 terminal to "H". , Its operation is possible. Also, as shown in the right half of the figure, the DQ1 terminal, D
When you want to output data from the three data input / output terminals of Q2 terminal and DQ4 terminal, set the OE1 terminal, OE2 terminal, and OE4 terminal to "L" and leave the OE3 terminal at "H". Is possible.

(Embodiment 2) FIG. 3 is a diagram showing the configuration of a second embodiment of a random access semiconductor memory device according to the present invention, which is four data inputs (DI1 to DI4).
A read control circuit 3.14 and a read control (OE1 to OE4) which are provided with terminals 3 and 6 and four data output (DO1 to DO4) terminals 3 and 7 and are independent for each data output terminal.
It has terminals 3 and 5.

The embodiment of FIG. 3 is an embodiment of a random access semiconductor memory device in which the data input terminal and the data output terminal are separated, and the operation whose timing is shown in FIG. 4 is the same as that of the first embodiment (FIG. 1, FIG. 2).

(Embodiment 3) FIG. 5 is a diagram showing the configuration of a third embodiment of a random access semiconductor memory device according to the present invention, in which four data input / outputs (DQ1 to DQ).
4) Provided with terminals 5 and 6, each data input / output terminal has an independent write control circuit 5/12 and write control (WE1 to WE1).
WE4) terminals 5 and 4, read control circuits 5 and 13, and read control (OE1 to OE4) terminals 5 and 5.

The address input method (method of selecting an arbitrary memory cell) in the embodiment of FIG. 5 is the same as the conventional example.

In the write cycle, after inputting the address,
By setting the write control (WE1 to WE4) terminals 5.4 to "L", it is possible to write to the memory cell selected by the input address in the memory cell array 5.11.

After selecting the memory cell, all the four data input / output (DQ1 to DQ4) terminals 5 and 6 are used by setting all the four read control (OE1 to OE4) terminals 5 and 5 to "L". The read cycle can be realized. When data is output only from some of the four DQ1 to DQ4 terminals 5 and 6, the first
As in the case of the above embodiment, four read controls (OE1
~ OE4) Of the terminals 5 and 5, the read control terminal corresponding to the terminal to which data is to be output is set to "L". DQ1-D
The data input / output terminal corresponding to the "H" read control terminal of the Q4 terminals 5 and 6 remains at high impedance.

For example, as shown in the left half of FIG.
If you want to output data only from 1 terminal and DQ3 terminal, set OE1 terminal and OE3 terminal of OE1 to OE4 terminals 5 and 5 to "L" and leave OE2 terminal and OE4 terminal to "H". , Its operation is possible.

Further, four data input / output (DQ1 to DQ
4) Of the terminals 5 and 6, when it is desired to read data from the DQ1 and DQ2 terminals and write data through the DQ3 and DQ4 terminals, two memory cycles are required as shown in FIG. 13 in the conventional example. Although necessary, according to this embodiment, as shown in the right half of FIG.
After selecting the memory cell, four write controls (WE1-
WE4) Of the terminals 5 and 4, the WE3 terminal and the WE4 terminal are set to “L”, and four read controls (OE1 to OE) are performed.
4) By setting the OE1 terminal and the OE2 terminal of the terminals 5 and 5 to "L", the operation can be performed in one memory cycle.

(Embodiment 4) FIG. 7 is a diagram showing the structure of a fourth embodiment of a random access semiconductor memory device according to the present invention, and four data inputs (DI1 to DI4).
A write control circuit 7.13 and a write control circuit (WE1 to WE) each including a terminal 7.6 and four data output (DO1 to DO4) terminals 7.7 and independent for each data input terminal.
4) Terminals 7 and 4, read control circuits 7 and 14 and read controls (OE1 to OE) independent for each data output terminal
4) It has terminals 7 and 5.

The embodiment of FIG. 7 is an embodiment of a random access semiconductor memory device in which a data input terminal and a data output terminal are separated, and its operation whose timing is shown in FIG. 8 is the third embodiment (FIG. 5, FIG. 6).

[0037]

As described above, according to the first to fourth aspects.
According to the invention, in a random access semiconductor memory device having a plurality of data input / output terminals or a plurality of data output terminals, a read control circuit is independently provided for each data input / output terminal or for each data output terminal. Since this is adopted, partial reading of data can be realized through some of the plurality of data input / output terminals or some of the plurality of data output terminals, which has been impossible in the past. Therefore, it is possible to simultaneously read a plurality of random access semiconductor memory devices.

In particular, according to the invention of claim 2 or 4, a random access semiconductor memory device having a plurality of data input / output terminals, or a random access semiconductor having a plurality of data input terminals and the same number of data output terminals. In the memory device, a write control circuit that is independent for each data input / output terminal or a write control circuit that is independent for each data input terminal is used. It is possible to simultaneously execute the data writing through and the data reading from other terminals.

As described above, according to the inventions of claims 1 to 4, it is effective in increasing the speed and function of the random access semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a random access semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram for explaining the operation of the random access semiconductor memory device according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a random access semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a timing diagram for explaining the operation of the random access semiconductor memory device according to the second embodiment.

FIG. 5 is a block diagram showing a configuration of a random access semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a timing diagram for explaining the operation of the random access semiconductor memory device according to the third embodiment.

FIG. 7 is a block diagram showing a configuration of a random access semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a timing diagram for explaining the operation of the random access semiconductor memory device according to the fourth embodiment.

FIG. 9 is a block diagram showing a configuration example of a conventional random access semiconductor memory device.

FIG. 10 is a timing diagram illustrating an operation of a conventional random access semiconductor memory device.

FIG. 11 is a configuration diagram of a system to which a conventional random access semiconductor memory device is applied.

12 is a first timing diagram for explaining an operation of the system of FIG.

FIG. 13 is a second timing diagram for explaining the operation of the system of FIG.

[Explanation of symbols]

1.1 RAS pin 1.2 CAS pin 1.3 Address pin 1.4 WE pin 1.5 OE pin 1.6 Data input / output pin 1.7 ROW address buffer 1.8 COLUMN address buffer 1.9 ROW decoder 1・ 10 COLUMN decoder 1 ・ 11 memory cell array 1 ・ 12 write control circuit 1 ・ 13 read control circuit 1 ・ 14 data input buffer 1 ・ 15 data output buffer 3 ・ 1 RAS terminal 3 ・ 2 CAS terminal 3 ・ 3 address terminal 3 4 WE terminal 3 5 OE terminal 3 6 data input terminal 3 7 data output terminal 3 8 ROW address buffer 3 9 COLUMN address buffer 3 10 ROW decoder 3 11 COLUMN decoder 3 12 memory cell array 3 .13 write control circuit 3.14 read Control circuit 3 ・ 15 Data input buffer 3 ・ 16 Data output buffer 5.1 RAS terminal 5.2 CAS terminal 5 ・ 3 Address terminal 5.4 WE terminal 5.5 OE terminal 5.6 Data input / output terminal 5.7 ROW address buffer 5.8 COLUMN address buffer 5.9 ROW decoder 5 ・ 10 COLUMN decoder 511 memory cell array 5.12 write control circuit 5.13 read control circuit 514 data input buffer 515 data output buffer 7 1 RAS terminal 7 2 CAS terminal 7 3 address terminal 7 4 WE terminal 7 5 OE terminal 7 6 data input terminal 7 7 data output terminal 7 8 ROW address buffer 7 9 COLUMN address buffer 7 10 ROW Decoder 7.11 COLUMN Decoder 7 ・ 12 Memory cell array 7 ・ 13 Write control circuit 7 ・ 14 Read control circuit 7 ・ 15 Data input buffer 7 ・ 16 Data output buffer 9.1 RAS terminal 9.2 CAS terminal 9.3 Address terminal 9.4 WE terminal 9.5 OE terminal 9.6 Data input / output terminal 9.7 ROW address buffer 9.8 COLUMN address buffer 9.9 ROW decoder 9/10 COLUMN decoder 9/11 Memory cell array 9/12 Write control circuit 9/13 Read Control circuit 9/14 Data input buffer 9/15 Data output buffer 11.1 Random access semiconductor memory device in conventional example 11.2 Random access semiconductor memory device in conventional example 11.3 Random access semiconductor memory device in conventional example

Claims (4)

[Claims] 1. A random access semiconductor memory device having a plurality of data input / output terminals, and having an independent read control circuit for each data input / output terminal. 2. A read control circuit having a plurality of data input / output terminals and independent for each data input / output terminal, and a write control circuit independent for each data input / output terminal. Random access semiconductor memory device. 3. A random access semiconductor memory device having a plurality of data output terminals, and an independent read control circuit for each data output terminal. 4. A read control circuit having a plurality of data input terminals and the same number of data output terminals, and an independent read control circuit for each data output terminal, and an independent write control circuit for each data input terminal. A random access semiconductor memory device having: