JPH05341996A - Digital computer and program restoring method - Google Patents

Abstract

PURPOSE:To provide a digital computer and a program restoring method capable of reducing the kind of instructions. and simplifying an instruction decoder circuit and decreasing memory size required after the instruction is executed. CONSTITUTION:An address and internal state saving part 1 which saves a code to identify Input from-subroutine SR, and required operating state data when the subroutine is inputted and saves a code to identify the input from interrupt AI and the required operating state data when the interrupt is inputted, and an address and internal state restoring part which reads out saving data by receiving the same restoration instruction RI and performs restoration from the subroutine or the interrupt corresponding to an identification code are provided, and the restoration from the subroutine or the interrupt can be performed by using the same restoration instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital computer for performing, for example, artificial intelligence information processing, natural language processing, mathematical expression processing, etc., and more particularly to processing for a return instruction during subroutine processing and interrupt processing.

[0002]

2. Description of the Related Art Generally, in a digital computer,
Execution control is given to the main program by a call from the operating system, and the subprogram is called from here. A subprogram is a program that, when the same processing is repeated many times in one program, makes that processing an independent program, and calls it by a calling instruction when necessary to perform the processing. It is composed of a so-called subroutine, which is a set of processing procedures.

Normally, when a subroutine call instruction is issued, the return address information is saved and saved in a predetermined save area, and the main routine proceeds to a program based on a subroutine. As the return address data, the value of a program counter (PC) is stored. When there is a return instruction from the subroutine, the saved return address data is taken out, the value of PC is returned to the original value before the subroutine call instruction was issued, and the main routine called from the called subroutine is programmed. Progress is returned.

Further, in a computer, when a power supply abnormality, a computer malfunction, an external signal reception, an input / output operation completion, a program error, etc. occur, the processing of the program currently being executed is interrupted, and the operating system interrupts. A so-called interrupt is performed in which control is transferred to the control routine. At the time of interrupt processing, the return address data from the interrupt and the data related to the internal state of the computer when the interrupt occurs are saved and saved. If it is possible to continue processing, the program interrupted by the occurrence of an interrupt was interrupted by the return address data and the data related to the internal state of the computer when the interrupt occurred, based on the return instruction. The program restarts from that point.

[0005]

By the way, in the conventional digital computer, when returning from the subroutine to the main routine, the value of the program counter may be returned to the original value, but when returning from the interrupt, Since it is necessary to return to the state before the interrupt occurs, each restoration process is performed based on a different restoration instruction. Thus, in the conventional digital computer,
Since different return instructions are used for returning from a subroutine and for returning from an interrupt, the hardware configuration for instruction decoding becomes complicated, the cost increases, and the memory size required for the instructions increases. There are drawbacks.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the number of types of instructions, simplify the instruction decoding circuit, and reduce the memory size required after the instruction and the program restoration. To provide a method.

[0007]

In order to achieve the above object, in the digital computer of the present invention, means for saving a code for identifying the input from the subroutine and the necessary operating state data at the time of the input of the subroutine, and an interrupt To have a means for saving the code identifying the input from the interrupt and the necessary operation state data at the time of input, and a means for receiving the same restoration instruction, reading the saved data, and returning from the subroutine or interrupt according to the identification code. I chose

In the digital computer of the present invention, the operating state data saved at the time of inputting a subroutine and the operating state data saved at the time of inputting an interrupt have the same data format, and these operating state data are input from the subroutine and interrupts. It is provided with a means for adding a code for discriminating which of the above inputs is the input and saving it.

In the digital computer of the present invention, the storage means and the contents of the program counter are used as address data at the time of the input of the subroutine, and at the time of the input of the interrupt.
The contents of the program counter are used as address data, the contents of the flag register and interrupt level register are used as internal state data, and a code for identifying the input instruction that caused the save operation is added to these data. A means for evacuating to the storage means is provided.

In the digital computer of the present invention, means for receiving the return instruction, reading the save data from the storage means, extracting address data from the read save data and setting it in the program counter, and detecting the identification code from the read save data. However, when the saved data is data at the time of interruption, the internal state data is extracted and set in the flag register and the interrupt level register.

In the data restoration method of the present invention, a code for identifying the input from the subroutine when the subroutine is input and the necessary operation state data are saved, and a code for identifying the input from the interrupt and the necessary operation are input when the interrupt is input. The state data and are saved, and the same return instruction is used to return from a subroutine or interrupt.

[0012]

According to the digital computer of the present invention, when the subroutine is input, the code for identifying the input from the subroutine and the necessary operation state data are saved. on the other hand,
At the time of inputting an interrupt, a code identifying the input from the interrupt and necessary operation state data are saved. Here, when the subroutine is input and when the interrupt is input, the save data is read in response to the same return instruction, and the return operation from the subroutine or the interrupt is performed according to the saved identification code.

According to the digital computer of the present invention, the operation state data saved when the subroutine is input and the operation state data saved when the interrupt is input are saved in the same data format. At the time of saving the data, a code for identifying which of the input from the subroutine and the input from the interrupt is added to the operation state data.

According to the digital computer of the present invention, when a subroutine is input, the contents of the program counter are saved as address data together with the identification code in the storage means. On the other hand, when an interrupt is input, the contents of the program counter are used as address data, and the contents of the flag register and interrupt level register are saved in the storage means as internal state data together with the identification code.

According to the digital computer of the present invention, the save data is read in response to the return instruction. Address data is extracted from the read and saved data by the address extraction means, and the data is set in the program counter. Further, the identification code detecting means detects the identification code from the read and saved data, and as a result of this detection,
When the saved data is data at the time of interrupt, the internal state data is extracted and set in the flag register and the interrupt level register together with the setting operation of the address data in the program counter.

According to the data restoration method of the present invention, when the subroutine is input, the code for identifying the input from the subroutine and the necessary operation state data are stored. On the other hand, when an interrupt is input, a code for identifying the input from the interrupt and necessary operating state data are stored. When returning, the same return instruction is used to return from the subroutine or interrupt.

[0017]

1 is a block diagram of a parallel distributed computer system (hereinafter simply referred to as a computer system) using a symbol processing language to which the present invention is applied. The computer system is based on the architecture ACRE based on computational resources and evaluation. In architecture ACRE, calculation data at the time of execution of calculation is used as resources including memory management and communication function, and the process of executing calculation is recognized as an evaluation. ACRE is an architecture that embodies resource and evaluation mechanisms as calculation modules. A resource is a static representation of data, and internally performs processing such as resource management, but there is no need to be aware of it from evaluation. Evaluation is a dynamic behavior of a resource, which gives a change to the resource.

The processing element PE of the computer system, as shown in FIG. 1A, has an evaluation mechanism (evaluator) EU for executing high-speed symbol processing data operation, input / output and storage management. It consists of important resources RSC. Resource RSC
Is a data storage STR as a data storage location.
G and a resource manager RM as its management mechanism and communication function.

Further, in the architecture ACRE, the unit of parallel processing regarded as a computational resource is made to correspond to the resource in the architecture ACRE, and information is transmitted between the resources to improve the efficiency of parallel processing and the descriptiveness of the parallel processing system. Can be planned. At this time, the information communication based on the resource RSC facilitates the configuration of a system in which a dedicated engine or a general-purpose processor is incorporated as the processing element PE of the computer system. Figure 1
(B) shows an example of the system configuration.In this case,
Information communication between the processing elements PE is performed by the resource manager RM. In the figure, IR
C (Inter Resource Connection) indicates a connection part.

The evaluator EU is a VLIW (Very Long Instruction Word) controlled processor having a data width of 32 bits. The evaluator EU is an instruction cache (64 bits × 64 Kwo) for high-speed execution of compiled code of user-defined functions and methods.
rds) IC and masker (MSK), shifter (SFT) and AL for high-speed field calculation of data
U and multi-way branch function by data field value to speed up function and method call, and dispatch for multi-way branch ■ (Lookup) table DP
And a 64 Kwords control memory CM for the system stack SS of the evaluator EU, a 64 Kwords local memory LM for the user (frame) stack US and the register file RF when performing symbol processing calculations, and of the instructions It has a system controller SC that performs decoding, saves data in the system stack SS, and reads the data. The operations required for input / output and storage management are requested to be executed by the resource manager RM via the resource manager interface RMI / F.

The resource manager RM provides the evaluator EU with the functions of storage management, device management, process management, file management, input / output, and communication with other processing elements PE. For example, the workstation WS is applied to the resource manager RM, and realizes an interactive human interface environment at the time of application development and runtime on the X Window system of the workstation WS, for example. It has functions for incrementally correcting and compiling function definitions and method definitions, recovering from error status, and resuming execution, and provides input / output functions that enable dynamic interaction with the user when executing an application. In addition, the resource manager RM includes an evaluator interface EU I / F that is an interface with the evaluator EU, a communication interface CI / F for communicating with other processing elements PE during parallel processing, and a main memory of the data storage STRG. It has a pointer manipulator PM as an accelerator for high-speed access of symbol processing data on the MM, and a diagnostic interface DI / F.

The memory management includes, for example, MODDS (Memory Or) which is a memory configuration / management system for symbol processing.
ganization for Linked Data Structures) is used. The memory management by MODLS has been evaluated as being 10 to 40 times faster in management of symbol processing data than the conventional virtual memory system.

The main memory MM of the data storage STRG is a dual port memory which can be directly accessed from the evaluator EU via the main memory interface MMI / F, and has function access such as exclusive access and reference count effective in symbol processing operation. I will provide a.
The main memory MM has a structure of 80 bits × 256 Kwords for expressing these control information and a 2-word pointer. The disk system of the workstation WS is used as the secondary storage SM of the data storage STRG.

FIG. 3 is a block diagram conceptually showing a main part of the system controller SC in the evaluator EU of FIG. In FIG. 3, 1 is an address / internal state saving unit, 2 is an address / internal state restoring unit, PC is a program counter, FLG is a flag register indicating the internal state at the time of interrupt, and LVL is an interrupt indicating the internal state at the time of interrupt. A level register, SR is a subroutine call instruction, AI is an interrupt instruction, and RI is a return instruction decode output.

When the address / internal state saving section 1 receives a subroutine call instruction, the program counter PC
Format the contents of the Cystam Stack SS,
Specifically, when saved by the data format shown in FIG. 4 to be described later and receiving the interrupt instruction AI, the contents of the flag register FLG and the interrupt level register LVL are added to the system stack SS in addition to the contents of the program counter PC. It is saved according to the data format shown in FIG.

FIG. 4 shows an example of a data format stored in the system stack SS when the address / internal state saving unit 1 receives a subroutine call instruction and an interrupt instruction. The saved data is 3 as shown in FIG.
It consists of 2 bits. A return address, that is, the value of the program counter PC is saved in the 16-bit A field of 0th to 15th bits. 16-18
The F field consisting of 3 bits up to the bit is an internal state stored in the flag register FLG at the time of interruption,
That is, the contents of the flag register FLG are saved. Two
In the L field consisting of 3 bits from the 0th to the 22nd bit, the internal state saved in the level register LVL at the time of interrupt, that is, the contents of the interrupt level register LVL is saved. The I field consisting of the 1st bit of the 23rd bit indicates whether or not the contents of the flag register FLG and the interrupt level register LVL have been saved.
Specifically, "1" indicates that the contents of the flag register FLG and interrupt level register LVL have been saved, and "0" indicates that the contents of the flag register FLG and interrupt level register LVL have been saved. Indicates that there is no.

The address / internal state restoration unit 2 receives the decode output RI of the restoration instruction, and the value of the program counter PC as the restoration address saved in the system stack SS at the time of calling the subroutine or the program at the time of the interrupt occurrence. The value of the counter PC, the contents of the flag register FLG and the interrupt level register LVL are read, and the program counter PC and the flag register F are read.
The LG and the interrupt level register LVL are restored.

FIG. 5 is a block diagram showing a configuration example of the address / internal state restoration unit 2. Reference numeral 21 is a return address extraction circuit, 22 is a save information detection circuit, 23 is an internal state extraction circuit, 24 and 25 are gate switches, and 26 is an AND circuit. The return address extraction circuit 21 extracts A from the save data read from the system stack SS.
The field data, that is, the return address (value of the program counter PC) data is extracted. The save information detection circuit 22 detects whether the data of the I field is “1” or “0” from the save data read from the system stack SS, and the high level (“1”) corresponding to the level is detected. ) Or a low level (“0”) signal is output to the AND circuit 26. The internal state extraction circuit 23 extracts the data of the F field and the L field, that is, the internal state data at the time of interruption from the saved data read from the system stack SS. Gate switch 2
When the return instruction decode output RI is input at a high level, the reference numeral 4 sets the return address extracted by the return address extracting circuit 21 in the program counter PC. Upon receiving the high level output of the AND circuit 26, the gate switch 25 sets the internal state data extracted by the internal state extracting circuit 23 in the flag register FLG and the interrupt level register LVL. AND circuit 26
Is the save information detection circuit 22 and the return instruction decode output RI.
And a signal having a level corresponding to the result is output to the gate switch 25.

Next, the data saving operation at the time of a subroutine call or an interrupt and the return operation at the time of a return instruction according to the above configuration will be described with reference to the flowcharts of FIGS. 6 and 7.

For example, as shown in FIG.
When the subroutine call instruction SR is input to the internal state saving unit 1 (S1), the address / internal state saving unit 1 extracts the value of the program counter PC and sets the value in the A field (S2). When the I field is set to "0" (S3), 3 shown in FIG.
It is stored in a predetermined area of the system stack SS in a 2-bit format (S4).

On the other hand, when the interrupt instruction AI is input to the address / internal state saving unit 1 (S5), the address / internal state saving unit 1 extracts the value of the program counter PC and sets the value in the A field. (S6), the contents of the flag register FLG are set in the F field, the contents of the interrupt level register LVL in the L field (S7, S8), and the I field is set to "1" (S9). 3 shown in FIG.
It is stored in a predetermined area of the system stack SS in a 2-bit format (S4).

Here, as shown in FIG. 8, when the restore instruction decode output RI is input at a high level to the address / internal state restoring unit 2 (S10), it is stored in the system stack SS by the procedure of FIG. The saved data is read (S
11). The read save data is input to the return address extraction circuit 21, the save information detection circuit 22, and the internal state extraction circuit 23, respectively.

The return address extraction circuit 21 extracts the A field data, that is, the return address (the value of the program counter PC) data from the save data read from the system stack SS (S12). At this time, the high-level return instruction decode output RI is input to the gate switch 24 and the gate switch 24 is in the open state, so the extracted return address is set in the program counter PC (S13).

The save information detection circuit 22 detects whether the data in the I field is "1" or "0" from the read save data, and the high level ("1") corresponding to the level is detected. Alternatively, a low level (“0”) signal is output to the AND circuit 26 (S14). When the value of the I field is "1", the output of the AND circuit 26 is high level, and when the value of the I field is "0", the AND circuit 26 is high.
Is output to the gate switch 26 at a low level. The gate switch 26 is opened when the output of the AND circuit 26 is input at a high level, and is kept closed when input at a low level. At this time, the internal state extraction circuit 23 extracts the F field data and the L field data from the read save data (S15). F
When extracting the data of the field and L field, I
When the value of the field is "0" (S16), it is a return instruction of the subroutine, and it is determined that the internal state data is not saved in the read save data, and the flag register of the contents of the F and L fields. The FLG and the interrupt level register LVL are not set (S17). On the other hand, when the value of the I field is “1” (S16), it is an interrupt return instruction, and it is determined that the internal state data is saved in the read save data, and the extracted F and L fields are extracted. Is set in the flag register FLG and the interrupt level register (S18, S19).

As described above, according to this embodiment,
In addition to the address data (the value of the program counter PC) saved by a normal subroutine call instruction, the internal state data of the computer saved at the time of an interrupt is set with the address data saved by a normal subroutine call, Stored in a predetermined format, and at the time of storing, save with a code that identifies whether the saved data is due to a subroutine call instruction or an interrupt, and at the time of restoration, identify both by the value of the identification code. Since the data is restored by doing so, the restoration from the subroutine and the restoration from the interrupt can be realized by a single restoration instruction. As a result, there are advantages that the number of types of instructions can be reduced, the instruction decoding circuit can be simplified, and the memory size required after the instruction can be reduced.

[0036]

As described above, according to the present invention,
The number of instructions can be reduced, the instruction decoding circuit can be simplified, and the memory size required after the instruction can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system to which the present invention is applied.

FIG. 2 is a diagram showing a configuration example of a processing element according to the present invention.

3 is a configuration diagram conceptually showing a main part of a system controller in the evaluator EU of FIG.

FIG. 4 is a diagram showing an example of a data format stored in a system stack when an address / internal state saving unit according to the present invention receives a subroutine call instruction and an interrupt instruction.

FIG. 5 is a block diagram showing a configuration example of an address / internal state restoration unit according to the present invention.

FIG. 6 is a flowchart for explaining an operation of saving address data and internal state data according to the present invention.

FIG. 7 is a flowchart for explaining a restoring operation of address data / internal state data according to the present invention.

[Explanation of symbols]

 PE ... Processing element EU ... Evaluator RSC ... Resource RM ... Resource manager STRG ... Data storage IRG ... Coupling unit PC ... Program counter FLG ... Flag register LVL ... Interrupt level register 1 ... Address / internal state saving unit 2 ... Address / internal state restoration Part 21 ... Return address extraction circuit 22 ... Save information detection circuit 23 ... Internal state extraction circuit 24, 25 ... Gate switch 26 ... AND circuit

Claims (5)

[Claims] 1. A means for saving a code for identifying an input from the subroutine and a necessary operation state data at the time of inputting the subroutine, and a code for identifying an input from the interrupt at the time of inputting an interrupt and the necessary operation state data. A digital computer comprising means for saving and means for receiving the same return instruction, reading out the saved data, and returning from a subroutine or interrupt according to an identification code. 2. The same data format is used for the operation state data saved at the time of inputting a subroutine and the operation state data saved at the time of inputting an interrupt, and these operation state data have the same format as the input from the subroutine and the input from the interrupt. 2. A means for adding a code for identifying which input is input and saving the input.
The described digital computer. 3. The storage means and the contents of the program counter are used as address data when the subroutine is input, the contents of the program counter are used as the address data when the interrupt is input, and the contents of the flag register and the interrupt level register are set as internal states. 2. A means for saving the data as data, and adding a code for identifying the input instruction that causes the save operation to the data and saving the data in the storage means.
Alternatively, the digital computer according to claim 2. 4. A means for receiving the return instruction, reading the save data from the storage means, extracting address data from the read save data and setting it in the program counter, and detecting the identification code from the read save data, saving the save data. 4. The digital computer according to claim 1, further comprising means for extracting internal state data and setting it in a flag register and an interrupt level register in the case of interrupt data. 5. A code for identifying the input from the subroutine and the necessary operating state data are stored when the subroutine is input, and a code for identifying the input from the interrupt and the required operating state data are stored when the interrupt is input. , A program recovery method characterized in that the same recovery instruction is used to recover from a subroutine or interrupt.