JPH05336078A - Bit error rate measuring signal processing circuit for digital multiplex radio system - Google Patents

Abstract

PURPOSE:To properly measure a path by arranging data in parallel in order from head data for serial conversion of a parallel/serial conversion means to output these data to a reception-side bit error measuring means. CONSTITUTION:When pseudo random data X0 to X3 of n series outputted from a transmission-side bit error measuring means 1 are converted into serial data, a first signal S1 is outputted to a serial/parallel conversion means 4 to convert data into serial data. A second signal S2 is outputted to a MODEM serial/ parallel conversion means 6, and data are arranged in parallel in order from head data X0. A third signal S3 is outputted to a MODEM 3 to perform initialization. A reception-side path uncertainty eliminating means 23 outputs parallel data outputted from a serial/parallel conversion means 5 to a bit error rate measuring means 2 by the conversion means 4. Then, respective paths coincide with each other in a BAR measurer 2 and the MODEM on the transmission side and the reception side, and the proper bit error rate or each path of a parallel string is measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for measuring a bit error rate in a digital multiplex radio system.

With the development of ISDN, a synchronous digital hierarchy having a structure capable of flexibly synchronously multiplexing an existing speed signal with various high speed service signals has been defined, in which a new synchronous interface has been standardized, and a digital signal conforming to the standard has been defined. Wireless devices are being developed.

The new synchronous interface of the digital radio equipment is 51.84Mb / s × n, and the modulation / demodulation method has been conventional.
8 psk, 16 QAM, 64 QAM, 256 QAM, etc.

Depending on the modulation / demodulation system, it is possible to realize 5
1.84 Mb / s is converted to S / P (serial / parallel) or P / S (parallel / serial) on the input side or output side of a modulator / demodulator (modem) and the information is transmitted at a reduced clock speed.

For this reason, the worst path of the clock of the modem (for example, in the case of 16QAM, four values of two series I channels and two series Q channels are input to the modem.
The lines through which the value passes are called path 1 to path 4, and the worst path among them is to be evaluated). When evaluating the error, S / P conversion means and P / S conversion means corresponding to the modem are prepared externally,
Although an error is to be seen, since the signal passes through the S / P conversion means and the P / S conversion means, the path between the bit error rate measuring device and the modem does not match and the inconvenience occurs.

Therefore, it is desired to connect the signal processing circuit for measuring the bit error rate between the bit error rate measuring device and the modem to eliminate such inconvenience.

[0007]

2. Description of the Related Art A block diagram of a conventional digital multiplex radio system is shown in FIG. 5, and a case of measuring a bit error rate for each path in this system will be described. However, this system handles 16QAM signals.

In this figure, 1 and 2 are bit error rate measuring instruments (BER measuring instruments) on the transmitting side and the receiving side, respectively.
Is a serial interface modem, 4 is P / S
The converters 5 are S / P converters.

As described in the field of industrial use, the P / S converter 4 and the S / P converter 5 are connected to the outside of the modem 3 and the bit error rate measuring devices on the transmitting side and the receiving side are used for each measurement. The bit error rates of the paths P1 to P4 are measured.

The modem 3 constitutes an S / P converter 6, a speed converter 7, a PLL circuit 8, an FEC encoder 9, a modulator 10, a transmitter (Tx) 11, and a demodulating device which constitute a modulating device. Receiver (Rx) 12, demodulator 13, waveform equalizer 13, FEC decoder 15, speed converter 16, PL
The L circuit 17 and the P / S converter 18 are provided.

The transmission-side BER measuring device 1 has four series of paths P.
1, P2, P3, P4 pseudo-random data X ₀ ,
Outputs X ₁ , X ₂ and X ₃ . The P / S converter 4 connected to the transmission side BER measuring device 1 converts the data X _{0 to} X ₃ input in parallel via the paths P1 to P4 into X ₀ ... X.
Converts to serial in order of ₃ and outputs.

[0012] The serial data X ₀ ... X ₃ is converted into parallel data X ₀ to X ₃ by the S / P converter 6, the speed at a rate converter 7 constant clock signal is controlled is supplied by the PLL circuit 8 To be converted. For example, the parallel data X _{0 to} X _{3 at} a speed of 12.96 Mb / s output from the S / P converter 6 is converted to 13.944 Mb / s.

After the FEC encoder 9 inserts the check data into the slots generated in the data string for each of the paths 1 to 4 by this speed conversion, it is modulated by the modulator 10 and converted into a radio frequency signal M1 by the receiver 11. It is converted and output.

The output radio signal M1 is transmitted to the receiver 1
2 and converted to an intermediate frequency by the demodulator 13
Demodulated by. Demodulated parallel data X _{0 to} X
₃ is subjected to waveform equalization processing by the waveform equalizer 14 and output. The processing is for relieving waveform distortion data that has deteriorated due to fading, for example, in the wireless section.

The parallel data X _{0 to} X ₃ output from the waveform equalizer 14 are decoded by the FEC decoder 15. The processing here is performed by parallel data X _{0 to} X _3.
When the main data and the check data in the above are checked, if no error occurs, the error data is sent as it is, and if an error occurs, the error occurrence location is corrected.

The parallel data X _{0 to} X ₃ output from the FEC decoder 15 are speed-converted to 12.96 Mb / s by the speed converter 16 controlled by the PLL circuit 17 and output.

Parallel data X subjected to this speed conversion
_{0 to} X ₃ are serial data X ₀ ... In the P / S converter 18.
The data is converted into X ₃ and further converted into parallel data X _{0 to} X ₃ by the S / P converter 5, and then output to the reception side BER measuring device 2.

[0018]

In the digital multiplex radio system described above, in order to measure the bit error rate at the parallel stage, since the modem 3 has a serial interface configuration, the modem 3 and each transmitting side are connected. And P / S between the BER measuring devices 1 and 2 on the receiving side.
The converter 4 and the S / P converter 5 must be connected.

Therefore, the serial data X ₀ ... X ₃ output from the P / S converter 4 and the parallel data X _{0 to} X ₃ output from the S / P converter 6 of the modem 3 include data. Inconsistencies may occur, and the P / of the modem 3
Serial data X ₀ ... X ₃ output from the S converter 18
And parallel data X ₀ output from the S / P converter 5
A mismatch may similarly occur with X ₃ .

That is, since the paths P1 to P4 are uncertain, the path P1 between the BER measuring devices 1 and 2 and the modem 3 is set.
There is a problem in that the bit error rate cannot be properly measured because P4 does not match.

The present invention has been made in view of the above circumstances, and the paths of the BER measuring device on the transmission side and the reception side and the modem are made to coincide with each other, and an appropriate bit error rate of each path of the parallel sequence is obtained. It is an object of the present invention to provide a signal processing circuit for measuring a bit error rate in a digital multiplex radio system capable of performing the above measurement.

[0022]

FIG. 1 shows the principle of the present invention. In this figure, parts corresponding to those of the conventional example shown in FIG.

Normally, in order to measure the bit error rate in the n-series stage (parallel stage) in the modem 3 having the serial interface configuration, since the modem 3 has the serial interface configuration, the modem 3 and each transmitting side are connected. A parallel-serial conversion means (P / S conversion means) 4 and a serial-parallel conversion means (S / P conversion means) 5 are connected between the receiving side bit error rate measuring means (BER measuring means) 1 and 2. There must be.

That is, conventionally, in the case of 16QAM, the transmitting side B
The n-series (parallel) pseudo-random data X ₀ , X ₁ , X ₂ , X ₃ output from the ER measuring means 1 is input to the modem 3 via the P / S converting means 4, and is output from the modem 3. By inputting the serial data to the receiving side bit error rate measuring means 2 via the S / P converting means 5,
The bit error rate can be measured for each n series (each parallel path).

A feature of the present invention is that when converting the n-series pseudo random data X ₀ , X ₁ , X ₂ , X ₃ output from the transmission side bit error rate measuring means 1 into serial data, Predetermined order (eg, X ₀ , X ₁ , X ₂ , X
The first signal S1 for conversion into ₃ ) is output to the P / S conversion means 4, and the P / S conversion means 4 is used when converting the serial data output from the P / S conversion means 4 into parallel data. Is the first data (X
₀ ), the second signal S2 for parallel arrangement is output to the modem serial / parallel conversion means 6, and the third signal S3 for modem initialization is output to the modem 3. And a signal processing circuit 22 for measuring the bit error rate on the transmission side, and an S / S connected to the modem 3.
P conversion means 5 and reception side bit error rate measurement means 2
Means for connecting between the parallel data output from the S / P conversion means 5 and the P / S conversion means 4
Are arranged in parallel in order from the first data (X ₀ ) when the n-series pseudo random data X ₀ , X ₁ , X ₂ , X ₃ output from the transmission side bit error rate measuring means 1 are converted into serial data. Signal processing circuit 24 for measuring the bit error rate on the receiving side, which is provided with a path uncertain removal means 23 on the receiving side for inputting to the bit error rate measuring means 2 on the receiving side.
It is configured by having and.

[0026]

According to the present invention described above, when the n-series pseudo-random data X ₀ , X ₁ , X ₂ , X ₃ output from the transmission side bit error rate measuring means 1 is converted into serial data, From the transmission side path uncertainties removing means 21 to P / S
By supplying the first signal S1 to the conversion means 4,
An order corresponding to the first signal S1, for example, X ₀ , X ₁ , X ₂ ,
Converted in the order of X ₃ .

Serial data X ₀ ... X ₃ input from the P / S conversion means 4 to the modem ₃ is parallel data X _{0 to} X.
When converted to ₃ , the second signal S2 is supplied from the transmission side path uncertain removal means 21 to the modem S / P conversion means 6 so that the P / S conversion means 4 can output the serial data X _0.
Is converted ... from the beginning data X ₀ when converted to X ₃ in the parallel data X ₀ ~X ₃ in the order. That is, the data X ₀ is output from the output end of the first bit of the modem S / P conversion means 6, the data X ₁ is output from the output end of the second bit, the data X ₂ is output from the output end of the third bit, and the data X ₂ is 4 bits. The data X ₃ is output from the output end of the eye.

In the modem 3, the transmission side path uncertain removal means 2
The modem 3 is initialized by arbitrarily outputting the first to third signals S3. As described above, the n-series pseudo-random data X ₀ , X ₁ , X ₂ , X ₃ output from the transmission-side bit error rate measuring means 1 is input to the modem 3 to output serial data output from the modem 3. is X ₀ ... X _3, is converted into parallel data X ₀ to X ₃ by the S / P converter 5, by arranging the first data X ₀ when the P / S conversion unit 4 is subjected to serial conversion in parallel in order Output to the bit error rate measuring means 2 on the receiving side.
That is, data arranged in parallel in the order of X ₀ , X ₁ , X ₂ , X ₃ is input to the bit error rate measuring means 2.

Conventionally, the serial data X ₀ ... X ₃ output from the P / S converter 4 and the parallel data X _{0 to} X ₃ output from the modem S / P converter 6 do not match each other. A similar mismatch occurs between the serial data X ₀ ... X ₃ output from the modem P / S converter 18 and the parallel data X _{0 to} X ₃ output from the S / P converter 5. Therefore, the bit error rate may not be measured properly.

However, in the present invention, as described above, in the modem S / P conversion means 6, parallel data is sequentially arranged from the head data X ₀ when the P / S conversion means 4 converts the serial data X ₀ ... X _3. Converted to X _{0 to} X ₃ ,
Also, in the receiving side path uncertainty removing means 23, the parallel data X _{0 to} X ₃ are arranged in parallel in order from the head data X ₀ when the P / S converting means 4 performs serial conversion, and the bit error rate is measured. Since the data is input to the means 2, the mismatch does not occur unlike the conventional case.

Therefore, it is possible to properly measure the bit error rate of each path in the parallel stage.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a transmitting side path uncertainty removing means provided in a transmitting side bit error rate measuring signal processing circuit in a digital multiplex wireless system according to an embodiment of the present invention. In this figure, parts corresponding to the respective parts of the principle diagram shown in FIG. 1 are designated by the same reference numerals, and description thereof will be omitted.

Transmitting side path uncertainty removing means 21 shown in FIG.
Is a PLL circuit 30, delay flip-flops with set / reset (hereinafter referred to as DFF) 31, 32, switches 33, 34, 35, 36, a one-shot pulse generation circuit 37, a shift register 38, and an AND gate 3.
And 9 are provided.

The PLL circuit 30 includes a phase detector 40, a low pass filter 41, a voltage controlled oscillator 42, and a 1/4.
It is composed of a frequency dividing circuit 43, and multiplies the clock signal CLK of a predetermined speed by 4 and outputs it.

For example, the phase detector 40 detects a phase error between the 12.96 Mb / s clock signal CLK and the signal output from the 1/4 frequency divider circuit 43, and the detected error signal is detected by the low-pass filter 41. 51.84 Mb by being supplied to the voltage controlled oscillator 42 via
The clock signal CLK1 of / s is output.

Then, the clock signal CLK1 is divided into 1/4 by the 1/4 divider circuit 43, and the phase error between the divided signal and the clock signal CLK is taken, thereby obtaining 51.84 Mb / s. Locked clock signal C
LK1 is output from the PLL circuit 30.

The clock signal CLK1 output from the PLL circuit 30 is supplied to the clock ends CK of the DFFs 31 and 32 and the clock end of the shift register 38. The shift register 38 shifts the input signal to the data input terminal D by an arbitrary stage and outputs it, and the data input terminal D receives the one-shot pulse WP output from the one-shot pulse generation circuit 37. It is being supplied.

Further, the one-shot pulse generating circuit 37
Outputs a one-shot pulse WP when the reset signal RS is supplied, and this pulse WP outputs the shift register 3
8 is supplied to the modem 3, the reset pulse (third signal) S3 is supplied to the modem 3. The modem 3 is initialized by this supply.

On the other hand, the pulse PP1 output at the shift timing by being shifted from the other output end of the shift register 38 is supplied to one input end of the AND gate 39 and the clock end CK of the DFFs 31 and 32. ..

The clock signal CLK1 is supplied to the other input end of the AND gate 39, and the second signal S2, which is the result of the logical product with the pulse PP1, is output to the S / P conversion means 6. As a result, the timing when the S / P conversion means 6 performs parallel conversion is set.

The pulse PP1 output from the other output terminal of the shift register 38 is passed through the switch 33 to DF
F31 is supplied to the set end S, is supplied to the reset end R of the DFF 31 via the switch 34, is supplied to the set end S via the switch 35, and is supplied via the switch 36 to D
It is supplied to the reset terminal R of the FF32.

The connection between each DFF 31 and 32 is made by the DFF 3
The output terminal Q of 1 is connected to the data terminal D of the DFF 32, and D
The inverting output terminal QX of the FF32 is connected to the data terminal of the DFF31.

Therefore, by turning on any of the switches 33 to 36, "00", "01", "1"
Since the first signal S1 that changes between 0 and 11 is output to the P / S conversion means 4, the transmission side BER measurement means 1 outputs P.
The data X _{0 to} X ₃ supplied to the / S conversion means 4 are selected in arbitrary order and output as serial data X ₀ ... X ₃ .

That is, by turning on any of the switches 33 to 36, the head data converted serially by the P / S conversion means 4 and the head data converted parallel by the S / P conversion means 6 are generated. The timing of can be adjusted.

For example, the beginning of the serial data is X₀ When
And the beginning of the parallel data is X₀ Can be output as
it can. Therefore, conversion is performed by the P / S conversion means 4 as in the conventional case.
Serialized data X₀... X ₃And S / P conversion means 6
Converted parallel data X₀~ X₃And a discrepancy occurs
It disappears.

Next, referring to FIG. 3, the receiving side path uncertainty removing means will be described. However, in this figure, portions corresponding to the respective portions of the principle diagram shown in FIG. 1 are designated by the same reference numerals, and description thereof will be omitted.

Receiving side path uncertainty removing means 23 shown in FIG.
Is a 4-bit DFF 51, 52 and a 4-1 conversion type multiplexer (MUX) 53, 54, 55, 56.
And a path control circuit 57.

The 1st to 4th bit input terminals D1 to D4 of the DFF 51 are S / P conversion means 5 in paths P1 to P4.
Are connected to the output ends of the 1st to 4th bits.
Further, the output terminal Q1 of the first bit of the DFF 51 is connected to the MUX.
The input end A of 53, the input end B of the MUX 54, the input end C of the MUX 55, and the input end D of the MUX 56 are connected, and the output end Q2 of the second bit is the input ends D5 and MUX5 of the DFF 52.
4 is connected to the input end A, the input end B of the MUX 55 and the input end C of the MUX 56, and the output end Q3 of the third bit is a DFF.
52 input end D6, MUX55 input end A, MUX56
Is connected to the input terminal B of the
It is connected to the input terminal D7 of the FF 52 and the input terminal A of the MUX 56.

The output end Q5 of the DFF 52 is connected to the input end D of the MUX 53, the output end Q6 is connected to the input end C of the MUX 53, the input end D of the MUX 54, and the output end Q7 is M.
Input end B of UX53, input end C of MUX54, MUX5
5 is connected to the input terminal D.

The output terminals E1 to E4 of the MUXs 53 to 56 are connected to the receiving side BER measuring means 2. However, MU
Connection lines between the output terminals E1 to E4 of X53 and the receiving side BER measuring means 2 are defined as paths P1 to P4.

The input terminals A to D of the MUXs 53 to 56 are also provided.
The data supplied to is selected according to the selection signals S5 and S6 output from the path control circuit 57.

In the selection signals S5 and S6, S5 is an upper bit, and the data supplied to the input terminals A of the MUXs 53 to 56 is selected and output by "00" of S5 and S6, and "0" is output.
"1" to input terminal B of MUX53-56, "10" to MU
Input terminal C of X53-56, MUX53-5 with "11"
The data supplied to the input terminal D of 6 is output.

The path control circuit 57 will now be described with reference to FIG.
I will explain. The path control circuit 57 shown in FIG.
Path error detection circuits 61, 62, 63, 64 and DFF6
5, a AND gate 66, a synchronization protection circuit 67, and a counter 68.

The path error detection circuits 61 to 64 are composed of an n-stage shift register 69 and a comparison circuit 70. The shift register 69 is the MUX 53-5 shown in FIG.
The data sent via the paths P1 to P4 connected to the output terminals E1 to E4 of 6 are held up to 1 to n stages and output in parallel.

The comparison circuit 70 determines whether or not the data output in parallel is normal. The comparison data is stored in advance in the comparison circuit 70, and the comparison data is compared with the data output from the shift register 69. If the comparison result is correct, data “1” is output, and if it is incorrect, “0” is output. Is output.

The data output from each comparison circuit 70 is D
The data is held in the FF 65 and output. The output data of the DFF 65 is supplied to the disable terminal DE of the counter 68 via the AND gate 66, and the fourth bit output data of the DFF 65 is supplied to the synchronization protection circuit 67.

The synchronization protection circuit 67 outputs a pulse to the clock terminal CK of the counter 68 when data "0" is input m times, and outputs "0" in other cases. Counter 68
Is, when "0" is supplied to the enable end EN,
Each time a pulse is supplied to the clock terminal CK, it counts up by one, and this count causes "0".
Selection signals S6 and S5 that change by cycling through "0" to "11"
Is output to each MUX 35-56 shown in FIG. When "1" is supplied to the enable end EN, the counter 68 stops the counting operation.

In FIG. 3, for example, S / P conversion means 5
But the parallel data X ₀ serial data X ₀ ... X ₃ sent from the P / S conversion unit 18, the head as X ₀
Suppose that it was converted to X ₃ . That, S / P converting means is output data X ₀ to the output path P1 of 5, the data X ₁ in the path P2 is, data X ₂ in the path P3 is a data X ₃ is output to the path P4.

In this case, the parallel arrangement is the same as when the S / P conversion means 6 on the input side of the modem 3 shown in FIG. 2 converts the serial data X ₀ ... X ₃ into parallel data X _{0 to} X ₃ .

The DFF 51 shown in FIG. 3 has paths P1 to P4.
It holds and outputs the parallel data X _{0 to} X ₃ sent via. The data X _{0 to} X ₃ output from the output terminals Q1 to Q4 of the DFF 51 are supplied to the input terminals A of the MUXs 53 to 56.

Assuming that the selection signals S5 and S6 of "00" are output from the path control circuit 57, the MUXs 53 to 5 are
The data X _{0 to} X ₃ supplied to the input terminal A of 6 are selected and output to the receiving side BER measuring means 2.

In this case, each data X _{0 to} X is arranged in an appropriate array.
_{Since 3} is input to the receiving side BER measuring means 2, the bit error rates of the paths P1 to P4 are properly measured. On the other hand, it is assumed that, for example, the S / P conversion means 5 converts the serial data X ₀ ... X ₃ sent from the P / S conversion means 18 into parallel data with the head X ₃ .

In this case, since the parallel conversion timing is delayed from the proper timing by one, the data X ₃ is output to the output path P1 of the S / P conversion means 5, and the data X ₀ is transferred to the path P2. Data X ₁ is on P3, and path P is
Therefore, the data X ₂ is output to 4. However, X in combination of X ₃ is correct at this time (X ₀ ~X ₃₎ advanced one time than the combination of the data (X ₀ ~X _{3)
Is 3} .

The DFF 51 has its parallel array X₃ , X
₀ , X₁ , X₂ Data is retained and output, so each output
The output data of the output terminals Q1 to Q4 are arranged in the order. this
In this case, the DFF52 is the second to fourth bits of the DFF51.
X output from the eye₀ , X ₁ , X₂ Data of 1
Input from the input terminals D5 to D7 of the third bit to the third bit
Since it is held, X is output from the output terminals Q5 to Q7 of the DFF 52.
₀ , X₁ , X₂ Will be output.

Here, in the same way as described above, the path control circuit 5
When selection signals S5, S6 of "00" is output from the 7, from MUX53～56, data X ₃ being supplied to the input terminal _{A, X 0, X 1,} X 2 are output.
That is, the data X ₃ is output to the output path P1 of the MUXs 53 to 56.
There is output, the data X ₀ to path P2, data X ₁ in the path P3 is, the data X ₂ is output to the path P4.

This parallel arrangement is used for the modem 3 shown in FIG.
The S / P conversion means 6 on the input side of the serial data X ₀ ... X
_This is different from the parallel array when ₃ is converted into parallel data X _{0 to} X ₃ . In other words, if this is left as it is, an appropriate bit error rate cannot be measured.

However, in this case, looking at the data array supplied to the input terminals D of the MUXs 53 to 56, X ₀ , X
It is a correct array of ₁ , X ₂ , and X ₃ . This is because the output terminals Q5 to Q7 of the DFF 52 output the data of X ₀ , X ₁ , and X ₂ and the output terminal Q1 of the DFF 51 outputs the data of X ₀ .

That is, the data X ₀ , X ₁ , X ₂ , X ₃ supplied to the input terminals D of the MUXs 53 to 56 should be selected. Currently, data X ₃ the output path P1~P4 of MUX53~56, X _0, but X _1, X ₂ are transmitted, which is the same parallel arrangement order, to the path control circuit 57 shown in FIG. 3 Is entered.

When the data X ₃ is input to the shift register 69 of the path error detection circuit 61 shown in FIG. 3 via the path P1, the shift register 69 takes n bits of the data X ₃ and outputs it to the comparison circuit 70. To do.

The comparison circuit 70 stores comparison data corresponding to the data X ₀ to be originally transmitted on the path P1, and the data X ₃ sent from the shift register 69.
Compare with.

As a result of this comparison, it is determined that the data X ₃ sent via the path P1 is not correct, so that the comparison circuit 70 outputs "0" data. Similar processing is performed in the other path error detection circuits 62 to 64, and the data of "0" is output. However, the comparison circuit of the path error detection circuit 62 stores the comparison data corresponding to the data X ₁ that should originally be transmitted through the path P2, and the comparison circuit of the path error detection circuit 63 originally transmits the path P3. It is assumed that the comparison data corresponding to the data X ₂ to be transmitted and the comparison data corresponding to the data X ₃ to be originally transmitted through the path P 4 are stored in the comparison circuit of the path error detection circuit 64.

When “0” output from each of the path error detection circuits 61 to 64 is held in the DFF 65 and output, “0” is output from the AND gate 66 and is supplied to the enable end EN of the counter 68. As a result, the counter 68 enters the counting operation state.

Since "0" is also input to the synchronization protection circuit 67, a pulse signal is output to the counter 68 when "0" is input m times. This makes the counter 6
8 counts up. If the selection signals S6 and S5 output from the counter 68 change from "00" to "01" by this up-counting, the MUX 53 shown in FIG.
The data supplied to the input terminals B of .about.54 are selected.

In this case, the input terminals of the MUXs 53 to 54 are currently
Data X supplied to B₂ , X ₃ , X₀ , X₁ Out
Will be forced. That is, incorrect parallel array
Data X₂ , X₃ , X₀ , X₁ Will be output
Therefore, in the path control circuit 57 of FIG.
The same operation is repeated.

[0075] With this repetitive operation, when the selection signal S5, S6 of "11" is output from the path control circuit 57, the data X ₀ of the correct parallel sequences being supplied to the input terminal D of the current MUX53～54, X ₁ , X ₂ and X ₃ are selected and output.

Therefore, in the BER measuring means 2 on the receiving side,
The proper bit error rate measurement.
Become. As described above, according to this embodiment, the modem
In the S / P conversion means 6 of No. 3, the P / S conversion means 4 is
Real data X₀... X₃Data X when converted to ₀ 
Parallel data X in order₀~ X₃Is also converted to
In the receiving side path uncertain removal means 23,
X₀~ X₃However, the P / S conversion means 4 performs serial conversion.
First data X when₀ Are arranged in parallel in order from
Since it is input to the bit error rate measuring means 2,
There is no data discrepancy like
Properly measure the bit error rate from 1 to P4
You can

Although the case of 16 QAM has been described above as an example, the same idea can be applied to the case of 256 QAM, for example.

[0078]

As described above, according to the present invention,
There is an effect that the respective paths of the BER measuring device on the transmitting side and the receiving side and the modem are made to coincide with each other, and an appropriate bit error rate of each path of the parallel sequence can be measured.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block configuration diagram of a transmission side path uncertainty removing means provided in a transmission side bit error rate measuring signal processing circuit in a digital multiplex wireless system according to an exemplary embodiment of the present invention.

FIG. 3 is a block configuration diagram of a receiving side path uncertainty removing means provided in a transmitting side bit error rate measuring signal processing circuit in a digital multiplex wireless system according to an exemplary embodiment of the present invention.

FIG. 4 is a block configuration diagram of the path control circuit shown in FIG.

FIG. 5 is a block diagram of a conventional digital multiplex wireless system.

[Explanation of symbols]

 1 bit error rate measuring means on transmitting side 2 bit error rate measuring means on receiving side 3 modem 4 parallel / serial converting means 5 serial / parallel converting means 6 modem serial / parallel converting means 18 modem parallel / serial converting means 21 transmission side path uncertain removal means 22 transmission Side bit error rate measurement signal processing circuit 23 Reception side path uncertain removal means 24 Reception side bit error rate measurement signal processing circuit

Front page continued (72) Inventor Takanori Iwamatsu 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kenzo Kobayashi 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture (72) Invention Satoshi Aikawa 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (4)

[Claims] 1. A modem having a serial interface configuration
The transmission side bit error rate measuring means (1) is connected to the input side of (3) through the parallel-serial conversion means (4), and the serial-parallel conversion means (5) is connected to the output side of the modem (3). The receiving side bit error rate measuring means (2) is connected to the transmitting side bit error rate measuring means (1) to output n-series pseudo-random data (X ₀ , X ₁ , X ₂ , X ₃ ). The parallel-serial conversion means
It is input to the modem (3) via (4) and the serial data output from the modem (3) is sent to the receiving side bit error rate measuring means (2) via the serial-parallel conversion means (5). In a digital multiplex wireless system configured to be able to measure the bit error rate for every n series by inputting, n series of pseudo-random data ((n) output from the transmitting side bit error rate measuring means (1) X ₀ , X ₁ , X ₂ , X ₃ ) is converted into serial data, the first signal (S1) for converting in a predetermined order is output to the parallel-serial conversion means (4), First data when conversion means (4) performs serial conversion
Second signal for parallel arrangement in order from (for example, X ₀ ).
(S2) is output to the modem serial-parallel conversion means (6), and a third signal (S3) for modem initialization is output to the modem (3). A transmission side bit error rate measurement signal processing circuit (22), a serial-parallel conversion means (5) connected to the modem (3), and a reception side bit error rate measurement means (2). Means (23) connected between the parallel data output from the serial-parallel conversion means (5), serial data converted by the parallel-serial conversion means (4) to the head data (X ₀ ) Are arranged in parallel in this order and the receiving side bit error rate measuring means (2)
And a signal processing circuit (24) for receiving-side bit error rate measurement, which comprises a receiving-side path uncertainty removing means (23) for outputting to a bit-error-rate measuring signal processing in a digital multiplex wireless system circuit. 2. The transmission side path uncertainty removing means (21) multiplies and locks a system clock signal (CLK) by n,
A PLL circuit (30) that outputs this as a first clock signal (CLK1), and a one-shot pulse generation circuit (37) that outputs a one-shot pulse (WP) by a reset signal (RS) that is optionally input.
And, when the one-shot pulse (WP) is input, outputs the third signal (S3), shifts the clock signal (CLK1) by a predetermined number of stages, and outputs this as the second clock signal (PP1). And a shift register (38) for operating the first clock signal (CLK1) and selecting the second clock signal (PP1) by the switch means (33, 34, 35, 36) to set or reset end. A flip-flop (31, 32) with a set / reset function that outputs the first signal (S1) by supplying the first clock signal (CLK1) and the second clock signal (PP1)
2. A signal processing for bit error rate measurement in a digital multiplex radio system according to claim 1, further comprising: an AND gate (39) for taking a logical product of and and outputting this as the second signal (S2). circuit. 3. The receiving side path uncertainty removing means (23)
When the parallel data output from the serial-parallel conversion means (5) is four series of parallel data, the first to fourth paths (P1, P2, P3, P
4) a first flip-flop (51) to which the first to fourth bit input terminals (D1, D2, D3, D4) are connected, and the second bit output terminal of the first flip-flop (51) (Q2)
The 1st bit input end (D5) is connected to, the 3rd bit output end (Q3) is connected to the 2nd bit input end (D6), and the 4th bit output end (Q4) is connected to the 3rd bit The second flip-flop (52) connected to the input terminal (D7) of the first flip-flop and the first bit output end (Q1) of the first flip-flop (51) connected to the first bit input end (A), The second bit input end (B) is connected to the third bit output end (Q7) of the second flip-flop (52), and the third bit output end (Q6) of the second flip-flop (52) is connected to The input end (C) of the bit is connected, and the output end (Q of the first bit of the second flip-flop (52)
2) of the first flip-flop (51) and the first multiplexer (53) which is connected to the input terminal (D) of the fourth bit and which selects and outputs any one of the 4-bit input data. The 1st bit input end (A) is connected to the 1st bit output end (Q2), and the 2nd bit input end (B) is connected to the 1st bit output end (Q1) of the first flip-flop (51). The third bit output end (Q7) of the second flip-flop (52) is connected to the third bit input end (C), and the second bit output end (Q) of the second flip-flop (51) is connected.
The second multiplexer (54) to which the fourth bit input terminal (D) is connected to 6) and the first bit input terminal (A) to the third bit output terminal (Q3) of the first flip-flop (51). ) Is connected, the second bit output end (Q2) of the first flip-flop (51) is connected to the second bit input end (B), and the first bit output end of the first flip-flop (51) is connected. The third bit input terminal (C) is connected to (Q1), and the third bit output terminal (Q) of the second flip-flop (52) is connected.
The third multiplexer (55) to which the 4th bit input terminal (D) is connected to 7) and the 1st bit input terminal (A) to the 4th bit output terminal (Q4) of the 1st flip-flop (51). ) Is connected, the second bit input end (B) is connected to the third bit output end (Q3) of the first flip-flop (51), and the second bit output end of the first flip-flop (51) is connected. (The input terminal (C) of the third bit is connected to Q2, and the output terminal (Q of the first bit of the first flip-flop (51)
The fourth multiplexer having the 4th bit input terminal (D) connected to 1) and each of the 1st to 4th multiplexers (53 to 56) select and output any one of the 4-bit input data. The selection signals (S5, S6) for the operation of the first to fourth multiplexers (53 to 56)
2. A bit error rate in a digital multiplex wireless system according to claim 1, further comprising a path control circuit (57) for outputting to first to fourth multiplexers (53 to 56) in accordance with data outputted from Signal processing circuit for measurement. 4. The path control circuit (57) includes: a first path error detection circuit (61) for detecting an error in data output from the first multiplexer (53); and a second multiplexer (54). A second path error detection circuit (62) for detecting an error in output data; a third path error detection circuit (63) for detecting an error in data output from the third multiplexer (55); The fourth pass error detection circuit (64) for detecting an error in the data output from the four multiplexer (56) and the respective output data of the first to fourth pass error detection circuits (61 to 64) are held and output. Flip-flop (65), AND gate (66) that ANDs each output data of flip-flop (65) and outputs, and m bits of arbitrary output data of flip-flop (65) is taken The data is the data when the error was detected. In case of the sync protection circuit (67) that outputs a pulse signal and the AND result including the data when the error is detected is output from the AND gate (66) and supplied, the enable state In this case, the counter is configured to perform a count operation when the pulse signal is supplied and output the selection signal (S5, S6) having a value corresponding to the count number. A signal processing circuit for measuring a bit error rate in a multiplex wireless system.