JPH05336004A - Echo canceller - Google Patents

Abstract

PURPOSE:To reduce the capacity of a RAM while keeping the echo suppression performance by providing the RAM in response to a signal symbol series divided while bridging over breaks of divided signal symbol series. CONSTITUTION:An input signal Sn is delayed sequentially by delay devices 12-1-12-7 to obtain plural signal symbol series S0-S7, they are divided into the series S0-S3 and the series S4-S7, they are respectively inputted to RAMs 13-1, 13-3 as their addresses and the series S2-S5 bridging over them are inputted to a RAM 13-2 as their addresses. Then output data of the RAMs 13-1-13-3 added by an adder 14 are sent to a receiver side adder 10 as an pseudo echo e' and the pseudo echo e' is subtracted from the reception signal. A correction circuit 15 corrects the data of the relevant RAM based on the result of subtraction. Thus, the deterioration in the performance is recovered by adding the RAM having the signal symbols series bridged over the divided signal symbol series as its addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an echo canceller used, for example, in an ISDN subscriber line transmission type transceiver.

[0002]

[Prior Art] Operation services have begun in earnest.
In SDN, existing 2 line subscriber line and 4 line ISD
It is necessary to interface bidirectionally with N-compatible extensions. This is a 64 line ISDN compatible extension.
This is because the existing subscriber line is a transmission line consisting of a twisted pair line with a maximum length of about 7 km, which consists of a transmission line of about 160 kbps including two information signal channels of kbps and a control signal channel.

At present, an echo canceller (E) is used as one of the methods for bidirectional transmission using the existing subscriber line.
C) A transmission method is known.

FIG. 4 is a block diagram showing the configuration of a bidirectional interface circuit using an echo canceller as an example.

As shown in the figure, on the transmission side, the transmission circuit encodes the transmission data into an appropriate code format, the transmission filter 2 shapes the waveform, and then the D / A conversion circuit 3
Is converted into an analog signal and transmitted to the subscriber line side through the hybrid circuit 4.

On the receiving side, the analog signal that has passed through the subscriber line is input to the A / D conversion circuit 5 via the hybrid 4.
Then, after being converted into a digital code and parallel-shaped by the reception filter 6, the automatic equalization circuit 7 compensates the attenuation and distortion of the signal generated in the transmission path, and the decoding circuit 8 decodes it to obtain the reception data. ..

By the way, generally, in the hybrid circuit 4, the transmission / reception signals are not completely separated due to the imperfections of the circuit, and a part of the transmission signals wraps around to the reception side. That is, since the received signal contains an echo, an echo canceller 9 for removing the echo is provided in this circuit.

In the echo canceller 9, a pseudo echo e '(n) is generated from the transmission signal S (n) from the encoding circuit 1 and the echo e (n) which spills to the receiving side is eliminated by subtraction by the subtractor 10.

Now, as the echo canceller 9, as shown in FIG.
A RAM table reference type echo canceller as shown in FIG. (Reference: "Image Information Engineering and Broadcasting Technology", The Television Society of Japan, May 1991, pp. 35-3
This is the transmission symbol sequence S0 (n) to S5 (n) as the address of the RAM 91,
The echo amount e ′ (n) generated for each symbol sequence is stored in the RAM 9
The echo e (n)
Is to suppress. In this case, the number of taps that can completely overlap the echo including the non-linear component is set to 5.

In such an echo canceller 9, the number of taps N must be increased when the echo tail is long, which means that the memory address length is increased in the RAM table reference type echo canceller. That is, in the RAM table reference type echo canceller, as the number of taps increases, the capacity of the RAM 91 rapidly increases. For example, in the AMI code and the 2B1Q code, 2 bits are required as an address for each symbol, and in particular, in the 2B1Q code in which the echo tail becomes long and the number of required taps increases because the DC component is included, the memory capacity becomes enormous as the tap length increases. However, it is difficult to realize. Further, since the echo information is written in all the addresses of the RAM 91, there is a drawback that the convergence time becomes longer when the memory capacity of the RAM increases.

Therefore, as shown in FIG. 6, the signal symbol sequences S0 (n) to S5 (n) are converted into two signal sequences S, for example.
A method of reducing the total memory capacity by dividing into 0 (n) to S2 (n) and S3 (n) to S5 (n) and providing RAMs 91a and 91b to each is considered.

With this method, however, the memory capacity of the RAM can be greatly reduced, but the echo suppression performance of the echo canceller is remarkably high because it is not possible to take into account the non-linear echo extending between the symbols obtained by dividing the signal symbol sequence. There is a problem of deterioration.

[0013]

As described above, the conventional RA
In the M-table reference echo canceller, since the memory capacity of the RAM becomes huge when the number of taps is increased, it is considered that the signal symbol sequence is divided and the RAM is provided for each divided signal symbol sequence. Since it is no longer possible to consider the nonlinear echo that extends between the symbols of the signal symbol sequence, there is a problem that the performance of the echo canceller is significantly deteriorated.

Therefore, an object of the present invention is to provide an echo canceller capable of reducing the memory capacity of the RAM as much as possible while maintaining the original echo suppression performance.

[0015]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a RAM table reference type echo canceller which eliminates echoes sneaking around from a transmitting side to a receiving side. Delay means for generating a symbol sequence, and at least two divisions R each having an address of each signal symbol sequence group obtained by dividing the plurality of signal symbol sequences into at least two groups
Auxiliary RAM having AM and each signal symbol series in the vicinity of a break between adjacent signal symbol series groups as an address
An adding means for adding outputs of the respective divided RAMs and the auxiliary RAM to generate a pseudo echo for removing the echo; a subtraction result obtained by subtracting the pseudo echo from a reception signal and the divided RAM or the auxiliary RAM. And a correction means for correcting the data in each RAM based on the output.

[0016]

According to the present invention, the RA corresponding to the signal symbol sequence divided across the breaks of the divided signal symbol sequence.
Since M is provided, the total RAM capacity can be reduced while maintaining the echo suppression performance of the echo canceller.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a RAM table reference type echo canceller according to an embodiment of the present invention.
This echo canceller is used, for example, as the echo canceller 9 shown in FIG.

In the figure, reference numeral 11 denotes an input terminal to which the transmission signal S (n) is input. The transmission signal S (n) input to the input terminal 11 is delayed by the delay units 12-1 to 12-7.
Sequentially delayed by a plurality of signal symbol sequences S0
(N) to S7 (n). These signal symbol sequences are divided into two before and after, and the signal symbol sequences S0 (n) to
S3 (n) is input as the address of the first RAM 13-1, and the signal symbol sequences S4 (n) to S7 (n) are the second address.
Is input as the address of the RAM 13-2. Also, the signal symbol sequence S2 spanning these signal symbol sequences
(N) to S5 (n) are input as addresses of the third RAM 13-3.

Then, the output data of each of the RAMs 13-1 to 13-3 are added by the adder 14, and the addition result is sent to the adder 10 on the receiving side as a pseudo echo e '(n), and from the received signal. The pseudo echo e '(n) is subtracted.

Each of the correction circuits 15-1 to 15-3 corresponds to the corresponding R based on the subtraction result obtained by subtracting the pseudo echo e '(n) from the received signal and the output of the corresponding RAM 13-1 to 13-3.
Correct the data of AM 13-1 to 13-3.

Now, when considering a 7-tap echo canceller with the transmission path signal 2B1Q code, the conventional RAM table reference type echo canceller as shown in FIG.
As shown in (a), there are 48 signal arrangements for ^eight signals, and the memory capacity of the RAM is required to be 64K. When this is divided into two as shown in FIG. 2B, FIG.
As described above, the RAM capacity is 0.5 K at 4 ⁴ × 2, and the memory capacity of the RAM is significantly reduced. However, in this case,
Since the address of the rear RAM is determined irrespective of the arrangement of the previous signals, it is not possible to consider the non-linear echo spanning the divided signal symbol sequences, and the performance is significantly deteriorated.

Therefore, as shown in FIG. 1, the signal symbol sequence S2 spanned between the signal symbol sequences divided into front and rear.
A RAM 13-3 having (n) to S5 as addresses is added. In this case, the RAM capacity is 4 ⁴ as shown in FIG.
Although x3 = 1.5K, the deterioration of the performance of the echo canceller caused by the discontinuity of the signal symbol sequence can be recovered.

Therefore, with the echo canceller of the present invention, the performance close to that of the original undivided echo canceller of the original RAM can be obtained by adding the minimum RAM.

In the above embodiment, the signal symbol sequence S0 (n) to S7 (n) is divided into two signal strings,
The addresses of the first RAM 13-1 and the second RAM 13-2 are made to correspond to each other, and the signal symbol series spanning two signal symbol series is made to correspond to the address of the third RAM 13-3. The division method is not limited to this. For example, for longer signal symbol sequences,
The RAM can be expanded by dividing it into two or more signal symbol sequences to correspond to the RAM, and by associating the RAM address with an arbitrary number of signal symbol sequences that straddle the signal symbol sequences divided before and after.

[0026]

As described above, according to the present invention,
The memory capacity of the entire RAM can be reduced while maintaining the echo suppression performance of the echo canceller.

[Brief description of drawings]

FIG. 1 is a block diagram of an echo canceller according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the effect of the present invention.

FIG. 3 is a diagram for explaining calculation of a memory capacity of a RAM.

FIG. 4 is a block diagram showing a configuration of an echo canceller transmission system in an ISDN subscriber line.

FIG. 5 is a block diagram showing a conventional RAM table reference type echo canceller.

FIG. 6 is a block diagram showing a conventional divided RAM table reference type echo canceller.

[Explanation of Codes] 12-1 to 12-7 ... Delay device 13-1 ... First RAM 13-2 ... Second RAM 13-3 ... Third RAM 14 ... … Adders 15-1 to 15-3 …… Correcting circuit

Claims (1)

[Claims] 1. A RAM table reference type echo canceller for removing an echo sneaking around from a transmission side to a reception side, a delay means for sequentially delaying a transmission signal to generate a plurality of signal symbol sequences, and the plurality of signal symbol sequences. At least two divided RAMs each having an address of each signal symbol sequence group obtained by dividing at least two groups, and an auxiliary RAM having each signal symbol sequence near the break between the adjacent signal symbol sequence groups as an address An addition means for adding outputs of the respective divided RAMs and the auxiliary RAM to generate a pseudo echo for removing the echo; a subtraction result obtained by subtracting the pseudo echo from a reception signal and the divided RAM or the auxiliary RAM. Correction means for correcting the data in each of these RAMs based on the output. Echo canceller to be.