JPH05335935A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide an integrated circuit able to reduce power consumption without deterioration in the speed performance and increase in a standby current. CONSTITUTION:The semiconductor integrated circuit consists of integrated circuit blocks (BLK1, BLK2) a signal wire (SIG1) for signal transmission between them, a circuit (DRV1) driving the signal wire at a low amplitude, and a reception circuit (REC2) converting the low amplitude into a high amplitude. The drive circuit uses an NMOS (TN2) for a charging purpose and uses a PMOS (TP2) for a discharging purpose and in which a high level of a low amplitude signal is set to be VCC-VTN and a low level thereof is set to be VSS-VTP. Thus, a voltage level of a large parasitic capacitance is reduced and the power consumption of the integrated circuit is reduced. Furthermore, even in the standby state, no through-current is in existence between power supplies (between VCC and VSS) and a leak current to the signal wire is decreased as time, then a low standby current is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a high speed and highly integrated semiconductor integrated circuit composed of fine elements.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (LSI = Large Scale)
Higher performance has been achieved by increasing the scale and speed of the integration, but the increase in power consumption has become a major problem. In particular, a reduced instruction set computer (RISC = Reduced Instruction Set Compute)
r) Chips are becoming more prominent. Currently, 5V is the mainstream power supply voltage for LSIs, but an example of reducing it to 3.3V to reduce power consumption is Digest of Technical Papers, 1992.
EE International Solid State
Circuits Conference, pp. 106-107 (1992) (Digest of Technical Papers, 1992 IEEE
International Solid-State Circuits Conference, pp.
106-107, February 1992). However, the power consumption in this case is 30 W, and the air cooling limit generally called has already been reached. In the future, in order to continue improving the performance of LSIs including RISC chips, it is necessary to further reduce the power supply voltage.

[0003]

On the other hand, however, it has been pointed out that the power supply voltage has a lower limit due to physical restrictions. Regarding this constraint, IEE Journal of Solid State Circuits, Vol. 9, No. 5, pp. 256-267 (197).
4) (IEEE Jounal of Solid-State Circuits, vol.9, N
o.5, pp.256-267, October 1974). As shown therein, the low current characteristic of the MOS transistor has a so-called subthreshold characteristic in which the drain current decays exponentially with respect to the gate voltage. This coefficient is called a subthreshold coefficient (tailing coefficient), and is a value of about 80 mV / 1 digit at room temperature. Therefore, if the gate threshold voltage is decreased in proportion to the decrease in the power supply voltage, a minute DC current flows even during the transistor cutoff period, which causes a problem of increasing current consumption during standby. Therefore, in the conventional CMOS circuit, when the power supply voltage is lowered, the threshold voltage cannot be lowered below a certain value. For the practical lower limit, see Proceedings of Technical Papers 1989 International Symposium on BLU.
Technology Systems and Applications, 188-192 (1989) (Proceedings o
f Technical Papers, 1989 International Symposium on
VLSI Technology, Systems and Applications, pp.18
8-192, May 1989), and Proceedings of the
Symposium on Row Temperature Electronics and High Temperature Superconductors, pp. 55-69 (1987) (Proceed
ings of the Symposium onLow Temperature Electronic
s and High Temperature Superconductors, pp.55-69, O
ct. 1987). The value is about 0.35 to 0.55V. The lower limit of the power supply voltage at this time is practically about 1.5 V, and if the voltage is further lowered, there is a problem that the delay time remarkably increases.

An object of the present invention is to enable high-speed and stable operation even with a signal amplitude lower than the lower limit of the power supply voltage, which is conventionally the lower limit, without increasing the current consumption during standby, and it is possible to achieve both low power consumption and high-speed performance. Another object of the present invention is to provide a semiconductor integrated circuit.

[0005]

The above-mentioned object is to make the signal amplitude inside the integrated circuit plural, to drive the main signal wiring with a small amplitude, and to convert from a small signal amplitude to a large signal amplitude with a small standby current. This can be achieved by providing an amplitude conversion circuit. Further stable operation can be achieved by using complementary small amplitude signals.

[0006]

Since the amplitude of the internal signal of various integrated circuits can be reduced, the charge / discharge current of the signal wiring (bus) can be reduced and the power consumption can be reduced. Moreover, since the peak current can be reduced, the reliability of the signal wiring can be improved and the noise can be reduced.
In addition, the charging / discharging time of the signal wiring (bus) can be reduced, and the speed can be increased. Furthermore, by using complementary signals, it is possible to enhance the common-mode noise removal capability. As a result, low power consumption can be achieved without being restricted by the lower limit of the power supply voltage, which is a problem in the conventional circuit system, and high integration, high speed, and low power consumption can be satisfied at the same time.

[0007]

1 is an embodiment for explaining the basic concept of a CMOS integrated circuit according to the present invention.

In FIG. 1, the CMOS integrated circuit chip includes a plurality of circuit blocks such as BLK1 and BLK2.
It is composed of signal wiring for transmitting signals between them.
In the example of FIG. 1, the output of BLK1 is connected to the signal wiring SIG1.
Is transmitted to the input of BLK2. Each circuit block includes a signal receiving unit (for example, REC2 in the drawing) that receives a signal with a small amplitude from another circuit block and converts it into a signal with a large amplitude, and a signal processing unit that processes a signal with a large amplitude (for example, FIG. Medium INV1, INV2), a drive circuit that outputs a signal of small amplitude to the signal wiring (for example, DRV in the figure)
1) and. Of these, the signal processing units (for example, INV1 and INV2 in the figure) are provided with power supply voltages VCC and V
It operates by SS and its signal amplitude is (VCC-VSS)
Becomes On the other hand, the drive circuit DRV1 is composed of an N-channel MOS transistor TN2 and a P-channel MOS transistor TP2, but unlike a normal CMOS inverter, this drive circuit DRV1 charges the source-follower operation N-channel MOS transistor TN2 and The P channel MOS transistor in operation discharges. In this example, the back gate of TN2 is VSS and the back gate of TP2 is VCC.
, Respectively, but both may be connected to the output SIG1. The signal receiving unit REC2 includes N channel MOS transistors TN3 and P that form a transfer gate.
It is composed of a channel MOS transistor TP3, an N-channel MOS transistor pair TN4 and TN5 whose gates and drains are cross-connected, and a P-channel MOS transistor pair TP4 and TP5. In addition, the transfer gate TN
The voltage VCC is applied to the gate of No. 3, and the voltage VSS is applied to the gate of TP3. In this embodiment, the gate threshold voltage of the N-channel MOS transistor is 0.5 V when the back gate and the source are connected, and the gate threshold voltage of the P-channel MOS transistor is −V when the back gate and the source are connected. It is set to 0.5V.

The operation of the circuit shown in FIG. 1 will be described with reference to FIG. In this example, VCC = 3.0V, VSS =
The case of 0V will be described, but the value is not limited to these values. Now, consider a case where the output N1 of the inverter INV1 in the circuit block BLK1 changes from 0V to 3V at time t0 and from 3V to 0V at time t3. Before time t0, that is, while the terminal N1 is 0 V, the transistor TN2 is non-conductive and TP2 is conductive, and the output of the drive circuit, that is, the potential of the signal line SIG1 is -VTP. Here, VTP is the gate threshold voltage of the P channel MOS transistor TP2. In this example, VTP when the back gate is 2V higher than the source
Is reduced to -1V due to the substrate effect. Therefore, the voltage of SIG1 becomes 1V when N1 is 0V. Now, at this time, the transfer gate TN which constitutes the receiving circuit REC2
Gate-source voltage of 3 is 2V, transistor TP3
Since the gate-source voltage of -1 becomes -1 V, TN3 becomes conductive and TP3 becomes non-conductive. Since the driving capability of the transistor TN3 is designed to be sufficiently larger than that of TP4,
The terminal N2 is at 1V which is equal to the input SIG1, and the transistor TP5 is conductive. On the other hand, since the voltage of the terminal N3 is 1 V or less, the transistor TN5 is non-conductive, and the terminal N4 is 3 V. Therefore,
The transistor TN4 is conducting and the terminal N3 is consequently set to 0V. In these transistors, the gate-source voltage of TP3 is -1V, which is equal to the gate threshold voltage, so a minute current called the subthreshold current flows, and the voltage of SIG1 decreases slightly with time. However, this effect will be described later. Now, at time t0, the terminal N1 changes from 0V to 3V.
Consider the case where it changes to V. Then, the transistor TN
2 becomes conductive and TP2 becomes non-conductive, and VCC-VTN is output to the output of the drive circuit, that is, the signal line SIG1. Here, VTN is an N-channel MOS transistor T
It is the gate threshold voltage of N2. In this example, the VTN when the back gate is lower than the source by 2V is increased by the substrate effect to 1V. Therefore, the voltage of SIG1 becomes 2V when N1 is 3V. At the same time, the receiving circuit R
Since the gate-source voltage of the transfer gate TN3 constituting the EC2 is 1 V and the gate-source voltage of the transistor TP3 is -2 V, TN3 is almost non-conductive and TP3 is conductive. By designing the driving capability of the transistor TP3 to be sufficiently larger than that of TN4, the terminal N3 becomes 2V, which is equal to the input SIG1, and the transistor TN5 becomes conductive. On the other hand, when the input SIG1 becomes 2V, the voltage of the terminal N2 rises to about 2V.
Therefore, the transistor TP5 becomes non-conductive, and the terminal N4 becomes 0V. As a result, the transistor TP4 becomes conductive,
The terminal N2 is pulled up to 3V at time t2. Similarly, when the terminal N1 changes from 3V to 0V at time t3, the signal line SIG1 changes from 2V to 1V and the terminal N4 changes from 0V to 3V.

As described above, the circuit block BLK1 shown in FIG.
The signal amplitude of 3V in the signal is converted into a signal having an amplitude of 1V, and the signal is converted to 3V again by the circuit block BLK2
Can be converted into a signal amplitude of Generally, most of the power consumption of an integrated circuit is consumed by charging and discharging a signal line (bus) provided for exchanging signals between circuit blocks. Therefore, reducing the voltage amplitude of this signal line is extremely effective in reducing the power consumption of the entire integrated circuit. In this embodiment, the amount of charge required to charge and discharge the load capacitance CW of the signal line SIG1 once can be reduced to one third. As a result, current consumption and power consumption can be reduced to about one third. In addition, when compared at the same operating speed, the peak current of the signal line and power supply line that occurs due to charging and discharging of the signal line capacity can be reduced to about one-third, and the metal wiring that constitutes the signal line and power supply line can be reduced. The reliability of can be improved. Furthermore, the noise of the power supply generated due to the resistance of the power supply line can be reduced to about one third, and an integrated circuit with more stable operation can be provided. By thus reducing the signal amplitude of the main signal line, it is possible to realize an integrated circuit with low power consumption and low noise while maintaining high speed.

By the way, in the circuit of this embodiment shown in FIG. 1, when the voltage of the signal line SIG1 is LOW, that is, 1 V,
The gate-source voltage of the transistors TP2 and TP3 is -1 V, which is equal to the gate threshold voltage, so that a minute current called a subthreshold current flows.
As a result, in the operation of holding the LOW level for a long time, such as increasing the operation cycle time, SI
The voltage of G1 drops slightly. Similarly, when the voltage of the signal line SIG1 is HIGH, that is, 2V, the gate-source voltage of the transistors TN2 and TN3 becomes 1V,
Since it matches the gate threshold voltage, the voltage of SIG1 slightly increases due to the subthreshold current in the operation of holding the HIGH level for a long time.

The operation in such a case will be described with reference to FIG. Now, consider the case where the voltage of the terminal N1 is maintained at 3V from time t6 to time t7. Transistor TN2,
The subthreshold coefficient of TN3 is 100 mV / digit, and the total of the subthreshold currents at time t6 is 10 n.
Assuming A, the voltage change of SIG1 during Δt (= t7-t6) is

[0013]

[Equation 1]

Is represented by CW = 2pF, Δt = 2m
If s, ΔV = 0.2V, and SIG1 and N
The voltage of 3 rises from 2V to about 2.2V. Time t
After 7, when the voltage of N1 starts to change again, the voltages of SIG1 and N3 reciprocate between 1V and 2V. Further, during the period from time t8 to t9 (Δt = 2 ms), when the voltage of the terminal N1 is maintained at 0V, the voltages of SIG1 and N3 decrease from 2V to about 1.8V as in the previous case. The total subthreshold current of the transistor at time t7 or t9 is about 100 pA. That is, since the operating current in the standby state where the signal does not change decreases with time, this method can prevent the standby current from increasing.

FIG. 4 shows another embodiment of the CMOS integrated circuit according to the present invention. The basic configuration is similar to the example of FIG. 1, but the configuration of the drive circuit DRV3 is different from the previous example. The drive circuit DRV3 includes a CMOS inverter INV4, N-channel MOS transistors TN6 to TN8 and a P-channel M.
It is composed of OS transistors TP6 to TP8. SIG
The gate of the transistor TN6 driving 2 is TN7 and T
The gates of N8 and TP6 are driven by TP7 and TP8, respectively. For example, when the input N5 of DRV3 is HIGH, the output N6 of INV4 is LO.
It becomes W, and TN7 and TP8 are conductive, and TN8 and TP7 are non-conductive. As a result, the gate of TN6 goes to VSS and T
Since the gate of P6 is connected to SIG2 respectively,
TN6 becomes non-conductive and TP6 becomes conductive. This makes SI
Although the potential of G2 rises, it rises only to VCC-VTP because the gate and drain of TP6 are connected. Here, VTP is the absolute value of the threshold value of the P-channel MOS transistor. Similarly, input N of DRV3
When 5 is LOW, N6 becomes HIGH, TN7 and TP8 become non-conductive, and TN8 and TP7 become conductive. As a result, the gate of TN6 is at SIG2 and the gate of TP6 is at V
Since it is connected to CC respectively, TN6 conducts and TP
6 becomes non-conductive. As a result, the potential of SIG2 becomes VTN.
Descend to. As described above, in the case of FIG. 1, when the voltage level of the signal line is HIGH, VCC-VTN, LOW
In contrast to VTP at that time, in the present embodiment of FIG. 4, they become VCC-VTP and VTN, respectively. The input logic threshold voltage of the receiving circuit REC4 is
Similar to the OS inverter, the larger the VTP, the lower the LOW side,
The higher the VTN, the higher the fluctuation toward the HIGH side. Therefore, considering that the threshold voltage of the transistor fluctuates due to variations in various manufacturing conditions, it is better that the voltage level of the signal line and the input logic threshold voltage of the receiving circuit shift in the same direction as in this embodiment. It is possible to enhance resistance to element variations. In this embodiment as well, as in the previous embodiment, the voltage of the signal line during standby is determined by charging or discharging by the subthreshold current of the transistor, so the standby current can be made a sufficiently low value.

FIG. 5 shows another embodiment of the CMOS integrated circuit according to the present invention. The basic configuration is the same as that of the example of FIG. 1, but the configurations of the drive circuit and the receiving circuit are slightly different from those of the previous example. The drive circuit DRV5 is similar to a normal CMOS inverter configuration, but the absolute value of the threshold voltage of the transistor forming the inverter is smaller than that of the transistor used in the signal processing circuit, and instead of VCC as the power supply voltage. The difference is that VSLO is used instead of VCLO and VSS. In addition, the signal receiving circuit REC6
Uses a transistor having a low threshold voltage for each of the transfer gates TN21 and TP21, and the voltage applied to those gates is VC instead of VCC.
The difference is that VSLI is used instead of LI and VSS. This structure is described in Japanese Patent Application No. 2-76880 and Japanese Patent Application No. 3-29847, but in this embodiment, V
Different internal voltage generating circuits are used for CLO, VCLI, VSLO, and VSLI, and their configurations are devised. In addition, VCLO and VCLI, VSLO and VS
The LIs have almost equal voltage values.

An example of an internal voltage generating circuit suitable for the embodiment of FIG. 5 is shown in FIG. This internal voltage generation circuit of FIG. 6 divides an external power supply voltage, generates a reference voltage VRL and VRS, and a voltage divider circuit DIV and a reference voltage VRL as inputs, and generates an internal voltage VCLO of almost the same value as that. Similarly to the buffer BUF1 provided to drive the internal power supply, V
Buffer BUF that generates SLO, VCLI, VSLI
2 to BUF4 and smoothing capacitors C1 to C6 connected between each external power source and internal power source. Of these, the voltage dividing circuit DIV is composed of resistors R1 to R3. The buffer BUF1 includes a differential amplifier circuit OP1, a P-channel MOS transistor TP40, and a bias current source resistor R4 as a load. The buffer BUF2 includes a differential amplifier circuit OP2 and an N-channel MO.
S-transistor TN40 and bias current source resistor R5
It consists of and. BUF3 is again BUF1 and B
The UF4 has the same configuration as the BUF2. In the case of the above configuration, if VSS = 0V, the output voltages VRL and VRS of the voltage dividing circuit DIV are

[0018]

[Equation 2]

It becomes As described above, by appropriately selecting the values of R1 to R3, the internal reference voltages VRL and VRS can be set to optimum values. In the present embodiment, the internal reference voltage is generated by resistance division of the external power supply voltage, but the present invention is not limited to this, and any other means can be used as long as it is a means for generating a voltage between VCC and VSS. It doesn't matter. Now, the operation of BUF1 will be described. BU
F1 applies the input VRL to the inverting input of the differential amplifier circuit OP1 and directly feeds back the output VCLO to the non-inverting input, and constitutes a so-called voltage follower that obtains an output voltage almost equal to the input voltage. For example, when the output VCLO decreases due to the load current, the gate voltage of the TP40 decreases, the conduction resistance of the TP40 decreases, and the output is increased. On the other hand, when the output VCLO rises, the gate voltage of TP40 rises, TP40 becomes non-conductive, and the output is pulled down by the bias current source resistor R4. The power supply VCLO is used for charging the load capacitance, as can be easily seen from the embodiment of FIG.
A higher drive capability is required for increasing O, but a lower drive capability is required for lowering O. Therefore, the value of the bias current source resistor R4 is set sufficiently high to suppress the standby current. For example, V
If CLO = 1.5 V and R4 = 1.5 MΩ, the standby current flowing through R4 has a small value of 1 μA. Similarly, for BUF2, the value of R5 is set to a sufficiently large value to reduce the standby current. BUF3 is BUF1
The BUF4 has basically the same configuration as the BUF2.

Now, the effect of applying the internal voltage generating circuit of FIG. 6 to the integrated circuit of FIG. 5 will be described. In FIG. 5, first, when VSLO and VSLI are equal and the voltage of the signal line SIG3 is LOW, the transistor TP
The gate-source voltage of 21 becomes 0V. For this reason,
The voltage of SIG3 decreases due to the subthreshold current. At this time, since VSLO has a low charging capability, the potential of SIG3 decreases to the point where the charging current and the subthreshold current are balanced. Therefore, the standby current matches the minute bias current flowing through the resistor for bias current source in the internal voltage generating circuit, and the standby current of the entire chip can be suppressed to a small value. Similarly, when the voltage of the signal line SIG3 is HIGH, the potential of SIG3 rises to the point where the subthreshold current of the transistor TN21 and the bias current of VCLO balance each other, so that the standby current of the entire chip can be kept small. The other operations are almost the same as those of the embodiment shown in FIGS. As described above, VCLI and VCL
By driving O, VSLI, and VSLO with different buffers, it is possible to prevent an increase in standby current.

Another embodiment of the internal voltage generating circuit suitable for the embodiment of FIG. 5 is shown in FIG. This internal voltage generation circuit includes buffers BUF10 to BUF1 provided to drive internal voltages VCLO, VSLO, VCLI, VSLI.
3. Smoothing capacitor C1 connected between each internal power supply and external power supply
It is composed of 0 to C13. Of these, buffer B
The UF10 is composed of a P-channel MOS transistor TP50 for load charging and a bias current source resistor R10, and the buffer BUF11 is composed of an N-channel MOS transistor TN50 for load discharging and a bias current source resistor R11. BUF12 is also BUF10 and BUF
13 is basically the same as the BUF 11. As in the example of FIG. 6, the bias current source resistance is set to a sufficiently high value so that the standby current does not increase. In this example, the P-channel MOS transistor is used on the charging side and the N-channel MOS transistor is used on the discharging side, but an N-channel MOS transistor may be used on the charging side and a P-channel MOS transistor may be used on the discharging side. Now, in the case of FIG. 7, each internal voltage is

[0022]

[Equation 3]

[0023]

[Equation 4]

[0024]

[Equation 5]

[0025]

[Equation 6]

[0026] Where VTP is P channel MO
S-transistor and VTN are N-channel MOS transistors and absolute values of their threshold voltages. Also in this case, similarly to the example of FIG. 6, VCLO and VCLI are similar in that the driving capability during charging is increased, and VSLO and VSLI are enhancing the driving capability during discharging. Compared with the example in FIG.
Although it is inferior in terms of (1) the degree of freedom in setting the voltage value and (2) the driving capability, it has the advantage that it can be realized by a simple circuit. In this embodiment, an internal voltage having a difference of a threshold voltage from the external power supply voltage is generated, but the circuit is configured by combining another MOS transistor generating such a voltage and a resistor. Further, as long as the circuit configuration is such that the driving capability at the time of charging and the driving capability at the time of discharging are asymmetrical, the same effect can be expected by applying to the embodiment of FIG. 5, not limited to the circuit shown here. be able to.

FIG. 8 shows another embodiment of the low-amplitude CMOS integrated circuit according to the present invention. The present embodiment provides an integrated circuit with improved resistance to disturbances such as noise and power supply fluctuations and variations in element characteristics by using complementary signal pairs. In the figure, the CMOS integrated circuit chip is BLK
7, a plurality of circuit blocks such as BLK8, and a signal line pair for transmitting a signal between them. In the example of this figure, the output of BLK7 is connected to the signal line pair SIG4, SIG4B.
Is transmitted to the input of BLK8. Each circuit block receives a complementary signal of a small amplitude from another circuit block and converts it to a complementary signal of a large amplitude (for example, REC8 in the figure), and outputs a complementary signal of a small amplitude to the signal line pair. Drive circuit (for example, DRV7A in the figure,
DRV7B), and a signal processing unit for processing a signal of large amplitude, and a furnace. Among these, the drive circuit and the signal processing unit are the same as those in the embodiment of FIG. The complementary signal receiving unit REC8 includes N-channel MOS transistors TN62 and TN63 having a low threshold voltage and a P-channel MOS transistor TP6 having a low threshold voltage.
2, TP63, N-channel MOS transistor TN64
~ TN67, P-channel MOS transistor TP64 ~
And TP67. Here, unlike the previous embodiment, the element sizes of TP64 and TP65 are almost equal,
The element sizes of TN64 and TN65 are also made substantially equal. By doing so, even if the voltages of the gate terminals (for example, N34 and N35) of the cross-coupled transistors change in the same phase (common mode), if the voltage difference is maintained, it is difficult for the information to be inverted and the malfunction occurs. The effect that does not occur is obtained.

Next, the operation will be described with reference to FIG.
Here, VCC = 3V, VSS = 0V, VCL
The case where O = VCLI = 2V and VSLO = VSLI = 1V will be described, but the values are not limited to these values, and VCC> V
CLO>VSLO> VSS and VCC>VCLI> V
Other voltage combinations may be used as long as the relationship of SLI> VSS is established. For example, consider a case where the input N30 of the drive circuit DRV7A changes from VCC to VSS and the input N31 of the drive circuit DRV7B changes from VSS to VCC at time t0. Similar to the embodiment of FIG. 5, the drive circuit operates and SIG4 changes from VSLO to VCLO, SIG4B.
Changes from VCLO to VSLO. This allows N3
2 from VSLO to VCLO, N35 from VCLO to V
As it approaches SLO, N33 changes from VCC to VSLO, and N34 changes from VSS to VCLO. As a result, the voltage of N32> the voltage of N33, N
34 voltage> N35 voltage, TN65 and TP64
Is more strongly conducted, N35 is driven to VSS and N32 is driven to VCC. As a result, TN64 and TP65 become non-conductive. At the same time, TN66 and TP67 conduct, and TN6
7 and TP66 become non-conductive, complementary signal output N36 becomes V
SS and N37 become VCC. Thus, the input SIG
4 and SIG4B are converted into large amplitudes respectively, and N3
7 and N36. Thus, according to this embodiment,
Complementary low-amplitude input signals can be converted to similarly complementary, large-amplitude signals. Also, input SIG4 and SI
Even if the voltage of G4B changes in the same phase, malfunction does not occur, and it is possible to provide an integrated circuit excellent in noise resistance.

FIG. 10 shows another embodiment of the receiving circuit for converting a small amplitude complementary input signal into a large amplitude complementary output signal. This circuit can be used instead of REC8 in the embodiment of FIG. In the figure, TN70 to TN7
Reference numeral 3 is a low threshold voltage N-channel MOS transistor, TP70 to TP73 are low threshold voltage P-channel MOS transistors, TN74 and TN75 are N-channel MOS transistors, and TP74 and TP75 are P-channel MOS transistors. Next, the operation of this circuit will be described. For example, consider a case where SIG5 is HIGH and SIG5B is LOW. The voltage level of SIG5 is V (S
IG5), the voltage level of SIG5B is V (SIG5
B) If the threshold voltage of the low-threshold voltage N-channel MOS transistor is VTNL and the threshold voltage of the low-threshold voltage P-channel MOS transistor is VTPL, between these values,

[0030]

[Equation 7]

The following relationship is established. At this time, TN70, TP71, TN73, and TP72 become conductive, OUT5B is on the VSS side, and OUT5 is VCC.
Driven to the side. As a result, TP75 and TN74 become conductive, OUT5B becomes VSS and OUT5 becomes VCC. Similarly, when SIG5 is LOW and SIG5B is HIGH,

[0032]

[Equation 8]

If the following relation is established, OUT5B is VS
S and OUT5 become VCC. Thus, in this embodiment, the output is inverted when the difference between the pair of complementary input signals exceeds a certain reference value. This reference value can be set to an appropriate value depending on the threshold voltage of the MOS transistor. In the input circuit of the present embodiment, as is apparent from the above equation, the output state is determined only by the voltage difference between the complementary input signal pairs, so that malfunction may occur even if in-phase voltage fluctuations occur in the input signal pair. It has the characteristic of being less likely to occur. In other words, this input circuit can be regarded as an equivalent differential amplifier circuit. Also, unlike the previous embodiment, it also has the feature that the intermediate voltage VCLI or VSLI is not required in the input circuit. It also has the advantage that there are few restrictions on the layout of the circuit.

FIG. 11 shows another embodiment of a receiving circuit for converting a complementary input signal having a small amplitude into an output signal having a large amplitude. This circuit can be used instead of REC8 in the embodiment of FIG. 8 as in the case of FIG.
This circuit differs from the previous embodiment in that the outputs are not complementary but single (single-ended). In the figure, TN8
0 is a low threshold voltage N channel MOS transistor, TP80 is a low threshold voltage P channel MOS transistor, TN81 and TN82 are N channel MOS transistors, and TP81 and TP82 are P channel MOS transistors. This input circuit has the same configuration as the input circuit REC6 in the embodiment of FIG. 5, but instead of applying the intermediate voltage to the gate of the low threshold voltage MOS transistor, it applies a signal complementary to the input. However, it is different. For example, SIG5 is HIGH, SIG5B
Considering the case where is LOW,

[0035]

[Equation 9]

If the following condition is established, TP80 becomes conductive,
TN80 becomes non-conductive, and as a result, TN82 becomes conductive and OUT5B becomes VSS. Similarly, SIG5 is LO
Considering the case where W and SIG5B are HIGH,

[0037]

[Equation 10]

If the following condition is established, the TN80 is conductive,
TP80 becomes non-conductive, and as a result, TP82 becomes conductive and OUT5B becomes VCC. Also in this embodiment, FIG.
Similar to the case of 0, the output is inverted when the difference between the pair of complementary input signals exceeds a certain reference value. This reference value can be set to an appropriate value depending on the threshold voltage of the MOS transistor. Further, similarly to the previous embodiment, since the output state is determined only by the voltage difference between the complementary input signal pairs, there is a feature that malfunction does not easily occur even if the in-phase voltage fluctuation occurs in the input signal pair.

Although the present invention has been described in detail with reference to the embodiments, the scope of application of the present invention is not limited to these. For example, although the case where an LSI is configured by CMOS transistors has been mainly described here, an LSI using a bipolar transistor or a junction FET, and an LSI in which an element is formed on a substrate other than silicon, for example, gallium arsenide, etc. However, it can be applied as it is.

[0040]

According to the present invention described above, it is possible to perform signal transmission with a low amplitude without increasing the current during standby, and since it is also excellent in noise resistance, high integration is achieved. Accordingly, it is possible to provide an LSI that operates at high speed without causing an increase in power consumption, which is a problem.

[Brief description of drawings]

FIG. 1 is a block diagram of a low-amplitude CMOS integrated circuit according to the present invention.

FIG. 2 is a timing diagram illustrating the operation of the embodiment of FIG.

3 is a timing diagram illustrating the operation of the embodiment of FIG.

FIG. 4 is a configuration diagram of another embodiment of a low-amplitude CMOS integrated circuit according to the present invention.

FIG. 5 is a configuration diagram of another embodiment of a low-amplitude CMOS integrated circuit according to the present invention.

FIG. 6 is a configuration diagram showing an embodiment of means for generating the internal voltage of FIG.

FIG. 7 is a configuration diagram showing another embodiment of the means for generating the internal voltage of FIG.

FIG. 8 is a configuration diagram of another embodiment of a low-amplitude CMOS integrated circuit according to the present invention.

9 is a timing diagram illustrating the operation of the embodiment of FIG.

10 is a configuration diagram of another embodiment of the input circuit used in FIG.

FIG. 11 is a configuration diagram of another embodiment of the input circuit used in FIG.

[Explanation of symbols]

CHP1 to CHP4 ... Integrated circuit chips, BLK1 to BL
K8 ... Integrated circuit block, INV1 to INV8, INV
9A, INV9B ... Inverter, DRV1, DRV3,
DRV5, DRV7A, DRV7B ... Driving circuit, REC
2, REC4, REC6, REC8 to REC10 ... Receiving circuit, DIV ... Voltage dividing circuit, BUF1 to BUF4, BUF
10-BUF13 ... Buffer, R1-R7, R10-R
13 ... Resistors, OP1 to OP2 ... Differential amplifier circuits, C1 to C
6, C10 to C13 ... Smoothing capacitance, CW ... Wiring parasitic capacitance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/017 8941-5J

Claims (12)

[Claims] 1. A CMOS circuit that operates at a first signal amplitude and at least a CMOS circuit that operates at a second signal amplitude, respectively. At least a high level of the first signal amplitude is higher than a high level of the second signal amplitude. Large, the low level of the first signal amplitude is set smaller than the low level of the second signal amplitude, and the difference between the high level of the first signal amplitude and the high level of the second signal amplitude is an NMOS transistor or a PMOS transistor. Is almost equal to the absolute value of the threshold voltage of
A semiconductor integrated circuit characterized in that the difference between the low level of the first signal amplitude and the low level of the second signal amplitude is substantially equal to the absolute value of the threshold voltage of either the NMOS transistor or the PMOS transistor. 2. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit, wherein the second signal amplitude is 1 volt or less. 3. The semiconductor integrated circuit according to claim 2,
A semiconductor integrated circuit, wherein the first signal amplitude is equal to a difference between a maximum value and a minimum value of a power supply voltage supplied from the outside. 4. The semiconductor integrated circuit according to claim 1, 2 or 3, wherein the current consumption during standby is 1/100 or less of the operating current at the maximum operating frequency. 5. The semiconductor integrated circuit according to claim 1, 2, 3 or 4, further comprising at least one means for inputting a second signal amplitude and outputting a first signal amplitude, said means. , A source to the input, a drain to the first terminal, a first conductivity type MOS transistor having a gate connected to the first power supply, an input to the source, a drain to the second terminal, a gate to the second power supply A second conductivity type MOS transistor, a gate to the first terminal, a second conductivity type MOS transistor having a drain connected to the output, a gate to the output, a first
Second-conductivity-type MOS transistor whose drain is connected to the terminal, the second-terminal is gate, the first-conductivity-type MOS transistor whose output is connected to the drain, the output is gate, and the second terminal is connected to the drain First conductivity type M
A semiconductor integrated circuit comprising at least an OS transistor. 6. The semiconductor integrated circuit according to claim 5, wherein the voltage difference between the first power supply and the second power supply is equal to the first signal amplitude. 7. The semiconductor integrated circuit according to claim 5, further comprising at least one means for inputting the first signal amplitude and outputting the second signal amplitude, said means having a gate for input and an output. A drain, a second conductivity type MOS transistor having a source connected to a third power supply, and a gate to an input, a drain to an output, and a first conductivity type MOS transistor having a source connected to a fourth power supply. A semiconductor integrated circuit comprising at least. 8. The semiconductor integrated circuit according to claim 7, wherein the voltage difference between the third power supply and the fourth power supply is equal to the second signal amplitude. 9. The semiconductor integrated circuit according to claim 8, wherein the charge current of the third power supply during load change is 100 times or more larger than the discharge current, and the discharge current of the fourth power supply during load change is charged. A semiconductor integrated circuit which is 100 times or more larger than a current. 10. The semiconductor integrated circuit according to claim 1, wherein the integrated circuit comprises a plurality of integrated circuit blocks and signal transmission means between the integrated circuit blocks. Is an input circuit that converts an input signal having a second signal amplitude into a first signal amplitude that is higher than that, a circuit group that performs signal processing at the first signal amplitude,
An output circuit for driving the first signal amplitude of the circuit group and having a second signal amplitude equal to the input signal of the integrated circuit block to the outside of the integrated circuit block. Includes at least one signal line for one signal, and the amplitude of the signal line is set to the second value.
A semiconductor integrated circuit having the signal amplitude of 1. 11. The semiconductor integrated circuit according to claim 10, wherein the signal transmission means includes at least a signal line pair consisting of one signal and two signal lines for transmitting a signal complementary thereto, and the signal line pair comprises a pair of signal lines. The semiconductor integrated circuit is characterized in that each of the signals has a second signal amplitude. 12. A semiconductor integrated circuit according to claim 1, wherein signal transmission / reception with the outside of the integrated circuit is performed with a second signal amplitude.