JPH05335567A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the electrostatic discharge resistance of a semiconductor device at large by protecting a control element weak to electrostatic discharge. CONSTITUTION:This device is constituted so that the static electricity applied to an input terminal G may not directly hit a control element 3, being equipped with a MOS-type power element 1, whose gate is connected to the input terminal G, a protective element 2, which is connected to the input terminal G and protects the gate of the MOS-type power element 2 from electrostatic discharge, a control element 3, which controls the gate potential of the MOS power element 1, and a delay element 9, which is connected between the gate electrode of the MOS-type power element 1 and the control element 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for protecting a control element used in an overcurrent protection circuit or an overtemperature protection circuit for a MOS type power element from electrostatic discharge.

[0002]

2. Description of the Related Art As a conventional semiconductor device, for example, there is a device described in Japanese Patent Laid-Open No. 64-68005. FIG. 5 is a circuit diagram showing a MOS type power device provided with the overcurrent protection means described in the above publication. However, parts not related to the present invention are omitted, and a protection element 2 for preventing gate breakdown of the MOSFET due to electrostatic discharge (ESD) is added. In FIG. 5, MO
The S-type power element 1 turns on and off the main current,
A current proportional to the main current flowing through the MOS type power element 1 flows through the mirror MOSFET 6. The current flows through the galvanic resistance 5, and when the value becomes excessive, the bipolar transistor serving as the control element 3 is turned on to lower the gate potential of the MOS type power element 1 and lower the main current. . The configuration so far shows the overcurrent protection function. Further, in order to prevent the gate oxide film from being destroyed by electrostatic discharge, a bidirectional Zener diode serving as a protection element 2 is connected between the gate pad G (input terminal) and the source S of the MOS type power element 1. When the charged capacitance C shown by the broken line in FIG. 5 touches the gate pad G, most of the static electricity flows through the protection element 2. However, the remaining static electricity charges the gates of the MOS type power element 1 and the mirror MOSFET 6 through the input resistor 4, and flows through the control element 3. At this time, the gate oxide films of the MOS power element 1 and the mirror MOSFET 6 may be destroyed, or the control element 3 may be destroyed. Therefore, it is necessary to design the protection element 2 sufficiently large.

FIG. 6 is a plan pattern layout diagram of the circuit shown in FIG. In FIG. 6, the protection element 2, the input resistance 4, and the control element 3 are all made of polycrystalline Si on the field oxide film.
It is formed in the film and is wired by an Al film such as 11 and 12 through a contact hole. Looking particularly at the path connected by the Al film 12, one end of the input resistor 4 is connected to the collector of the bipolar transistor which becomes the control element 3, and from there to the gate polycrystalline Si film 8 formed on the gate oxide film. It is connected. Reference numeral 7 is a gate pad.

[0004]

However, in such a conventional semiconductor device, its withstand capability against electrostatic discharge is the MOS type power element 1 and the mirror MOSFET.
The breakdown resistance of the gate oxide film of No. 6 and the breakdown resistance of the control element 3 are weaker. Therefore,
When the control element 3 is weak against electrostatic discharge, there is a problem that the entire semiconductor device becomes weak against electrostatic discharge. In the above description of the prior art, the overcurrent protection function is taken as an example, but another semiconductor device having a control element connected to the gate of a MOS power element,
For example, the same problem occurs in a device having an overtemperature protection function.

The present invention has been made to solve the problems of the prior art as described above, and provides a semiconductor device in which the electrostatic discharge withstand capability of the entire semiconductor device is improved by protecting the control element which is weak against electrostatic discharge. The purpose is to

[0006]

In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the present invention, a protective element for protecting the gate of the MOS type power element for turning on / off the main current from electrostatic discharge is provided, and the gate electrode of the MOS type power element and the gate potential of the MOS type power element are controlled. A delay element (a delay element or a delay circuit including a resistance and an electrostatic capacitance) is connected between the control element and the control element.

[0007]

When a high voltage static electricity is applied to the gate pad, most of the static electricity flows through the protection element. Then, the remaining static electricity charges the gate of the MOS type power element and is also applied to the delay element. However, since the time constant of electrostatic discharge is generally extremely small, about several to several hundred ns, if the delay time of the delay element is set to be sufficiently longer than that, electrostatic discharge will not be applied to the control element. Therefore, it is possible to effectively protect the control element which is weak against electrostatic discharge. Further, since the delay time of the delay element required for electrostatic discharge protection is generally much shorter than the on / off control time of the MOS power element, there is no possibility of affecting the main current control of the MOS power element.

Further, as shown in the embodiment of FIG. 4, when the plane pattern arrangement is changed to form the delay element equivalently, electrostatic discharge of electrostatic discharge can be performed without providing a special delay element. The withstand amount can be improved.

[0009]

1 is a circuit diagram of an embodiment of the present invention.
First, the configuration will be described. The gate of the MOS power element 1 for turning on / off the main current is connected to the gate pad G (input terminal) via the input resistor 4 (resistance value R _i ). Further, the delay element 9 is connected to the gate of the MOS power element 1, and the control element 3 is connected via the delay element 9. The control element 3 is composed of, for example, a bipolar transistor,
The MOS power element 1 is protected by controlling the gate potential of the MOS power element 1 according to the signal Sg indicating an abnormal state such as overcurrent or overtemperature. Further, between the gate pad G and the source pad S, a protection element 2 for protecting the destruction due to electrostatic discharge is connected. In addition, in this embodiment, as the delay element 9, a low-pass filter including a series circuit of a resistor R _x and a capacitance C _x is illustrated.

Next, the operation will be described. When electrostatic discharge is applied to the gate pad G, most of the static electricity flows through the protection element 2. The remaining static electricity charges the gate capacitance C _i of the MOS power element 1 through the input resistor 4 and is applied to the delay element 9. However, since the time constant of electrostatic discharge is generally as small as several to several hundred ns, if the delay time (R _x C _x ) of the delay element 9 is designed to be sufficiently larger than the time constant of electrostatic discharge, electrostatic No discharge is applied to the control element 3. Since the control element 3 controls the gate potential via the resistor R _x in this embodiment, R _x may be made small in order not to impair the control characteristics of the control element 3. If the delay time R _x C _x is made sufficiently smaller than the gate delay time R _i C _i , the switching speed of the MOS power device 1 will not be slowed by the delay element 9.

Next, FIG. 2 is a circuit diagram of a second embodiment of the present invention, showing a case where the present invention is applied to the conventional example shown in FIG. In FIG. 2, the control element 3 is composed of a bipolar transistor, and the potential at the connection point between the mirror MOSFET 6 and the galvanic resistance 5 becomes the signal Sg. The protection function from electrostatic discharge is the same as in FIG.

Next, FIG. 3 is a circuit diagram of a third embodiment of the present invention. This embodiment is described in Japanese Patent Application No. 62-261804.
The case where the present invention is applied to the power transistor with the overtemperature protection function shown in FIG. In this embodiment, the temperature sensitive resistor 10 is used to detect the temperature of the MOS type power element 1, and when the temperature rises, the bipolar transistor serving as the control element 3 is turned on to control the gate voltage of the MOS type power element 1. It is designed to protect against over temperature. The protection function from electrostatic discharge is the same as in FIG.

Next, FIG. 4 is a plan pattern layout diagram of a fourth embodiment of the present invention. In this embodiment, the conventional planar pattern arrangement shown in FIG. 6 is modified and the delay element 9 is equivalently formed. In the arrangement shown in FIG. 4, the input resistor 4 is connected to the gate polycrystalline Si film 8 via the Al film 13, and the control element 3 is connected to the gate polycrystalline Si film 8 via the Al film 14. The input resistor 4 and the control element 3 are spatially separated from each other and are not directly connected by the Al film but are connected via the gate polycrystalline Si film 8 therebetween. There is. In this arrangement, the spreading resistance of the gate polycrystalline Si film 8 serves as the resistance component R _x of the delay means, and the gate capacitance serves as the input capacitance C _{i and} the capacitance C _x of the delay means. Therefore, with such an arrangement, without providing a special delay element,
The resistance to electrostatic discharge can be improved. The delay time τ in the above case can be approximated by τ = ε _ox ρ _s L ² / t _ox . Where ε _ox is the dielectric constant of the gate oxide film, t _ox is the gate oxide film thickness, and ρ _s is the gate polycrystalline Si.
The sheet resistance of the film, L, is the width of the gate polycrystalline Si film acting as the delay element 9 (see FIG. 4). Therefore, if the width L is increased, the delay time τ is increased, and it is possible to increase τ to a time constant of electrostatic discharge of several to several hundred ns or more.

In the above description, the gate of the MOS type power element 1 is connected to the gate pad G via the input resistor 4.
Although the case where the gate is directly connected to the gate pad G without interposing the input resistance is described above, the same effect can be obtained.

[0015]

As described above, according to the present invention, the control element for controlling the gate voltage of the MOS type power element is connected via the delay element, so that the electrostatic discharge can control the control element. Since it is not directly hit, destruction of the control element can be prevented even if a control element that is weak against electrostatic discharge is used, and thereby the breakdown resistance of the entire semiconductor device can be improved. Further, when the delay element is equivalently formed by devising the arrangement of the control element, the destruction of the control element due to electrostatic discharge is prevented as in the above without providing a special delay element. The effect that can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the present invention.

FIG. 4 is a plan pattern layout diagram of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of an example of a conventional device.

6 is a plan pattern layout diagram of the circuit of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... MOS type power element 2 ... Protection element 3 ... Control element 4 ... Input resistance 5 ... Galvanic resistance 6 ... Mirror MOSFET 7 ... Gate pad 8 ... Gate polycrystalline Si film 9 ... Delay element 10 ... Temperature sensitive resistance 11-14 ... Al film G ... Gate pad (input terminal) D ... Drain pad S ... Source pad _Rx ... Delay element resistance _Cx ... Delay element capacitance Sg ... Signal indicating abnormal state

Claims (1)

[Claims] 1. A MOS type power element having a gate connected to an input terminal directly or via a resistor; a protection element connected to the input terminal to protect the gate of the MOS type power element from electrostatic discharge. A semiconductor device comprising: a control element for controlling a gate potential of the MOS power element; and a delay element connected between the gate electrode of the MOS power element and the control element.