JPH05335553A - Electrostatic induction type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an electrostatic induction type semiconductor device having excellent turn-off characteristics by varying a channel width of a channel region. CONSTITUTION:An electrostatic induction type semiconductor device comprises a wide part 3a and a narrow part 3b provided along a longitudinal direction of a cathode layer 3 on the layer 3, a wide part 4a and a narrow part 4b provided on a gate layer 4, or a narrow part 5a and a wide part 5b formed on a channel region 5 in combination therewith.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static induction type semiconductor device such as a static induction transistor or a static induction thyristor.
Particularly, it relates to the structure of the control electrode portion.

[0002]

2. Description of the Related Art In recent years, in the field of power semiconductors, there has been an increasing demand for devices capable of coping with higher frequencies from the viewpoint of high efficiency and low noise of applied devices. Static induction transistor (SIT) and static induction thyristor (SI thyristor)
The electrostatic induction type semiconductor device represented by is PCIM '
88 (J Nishizawa APPLICATION OF THE POWER STATIC
INDUCTION (SI) DEVICES Proc of PCIM'88 CONFERENC
E, 1-12, 1988) and the like, excellent high frequency characteristics are recognized for other power devices. However, these devices have a drawback in that a large current must be drawn from the gate at the time of turn-off, and the gate circuit becomes more complicated than that of a MOS type semiconductor.

Therefore, the emitter (cathode) of the SIT (SI thyristor) is the drain of the N-channel MOSFET, and the gate of the SIT (SI thyristor) is the MOSF.
It has been reported that a high-speed SI thyristor can be easily driven as a voltage-controlled device by connecting it to the source of ET (called cascode connection) (B.
J. Baliga Solid-St. Electron 25 No. 5 PP
345-353, 1982).

FIG. 4 shows a schematic structure of a conventional static induction thyristor. This static induction thyristor is a P ⁺ layer which is a P type semiconductor layer (anode layer which is a main electrode portion).
1, an N ⁻ layer (base layer) 2 that is an N-type semiconductor layer, a P layer (gate layer that is a control electrode portion) 4 that is a P-type semiconductor layer formed on the base layer 2, and adjacent to the gate layer 4. to N ^- layer which is formed on the N ⁺ layer (cathode layer is a main electrode portion)
It is composed of three. Here, P ⁺ layer 1 and N ⁻ layer 2
And the P layer 4 form a transistor, the N ⁻ layer 2, the P layer 4 and the N ⁺ layer 3 form an electrostatic induction transistor, and further the P layer (gate layer) 4 and the N ⁺ layer (cathode layer) 3 are formed. The channel region 5 is formed at a portion located between them.

FIG. 5 shows an example of cascode connection of an electrostatic induction thyristor, 6 is an electrostatic induction thyristor, 7 is an N-channel MOSFET, 8 is a Zener diode,
A is an anode electrode, K is a cathode electrode, and G is a gate electrode.

Generally, SIT and SI thyristors are roughly classified into a normally-off type that can block the voltage between the anode and the cathode without applying a gate reverse bias and a normally-on type that cannot block the voltage.

In the cascode connection as shown in FIG. 5, even if (1) a normally-on type SI thyristor is used, the circuit as a whole exhibits a normally-off characteristic.
Further, (2) in the circuit configuration of FIG. 5, it is not possible to supply a sufficient on-gate current to the SI thyristor. Therefore, if a normally-off type SI thyristor is used, the turn-on characteristics deteriorate.

For these reasons, normally-on type SI
A thyristor is used.

As the structure of the gate and cathode of the SI thyristor, a method of alternately arranging a P-type gate diffusion layer and an n-type gate diffusion layer in a strip shape as shown in FIG. 4 is widely used. The normally-on type and the normally-off type are mainly determined by the adjacent gate spacing (channel width), and the characteristics change to a normally-off type when the channel width is narrowed and a normally-on type when the channel width is widened.

[0010]

[Problems to be Solved by the Invention] Normally-on SI
Since the depletion layer generated by the internal electromotive force does not spread over the entire surface of the channel region, the thyristor exhibits excellent characteristics similar to the forward characteristics of the diode at the time of turn-on, and is suitable for the above cascode connection. However, unless a relatively large reverse voltage is applied between the gate and cathode, the current cannot be interrupted and the channel width is wide, so current concentration is likely to occur during the turn-off process, resulting in a normally-off type SI. There was a problem that the breaking resistance was inferior to that of thyristors. Therefore, it has been difficult to make a cascode module of SI thyristor capable of interrupting a current of 200 A or more.

As described above, the SIT or SI thyristor employs a method of arranging a large number of strip-shaped gates and cathodes. However, in the prior art, the width of each gate and cathode is increased in order to operate all regions uniformly. And the intervals have been constant. However, in practice, it is difficult to electrically increase the in-plane uniformity due to variations in the manufacturing process such as concentration and lifetime, and differences in the distance from the electrode terminals (differences in resistance to the terminals). It greatly hindered the improvement of the breaking current of normally-on type SIT and SI thyristor.

The present invention has been made in view of the above problems, and an object thereof is to provide an electrostatic induction type semiconductor device having excellent turn-off characteristics by changing the channel width of a channel region. .

[0013]

In order to achieve the above object, the present invention provides a semiconductor device having at least one junction between at least two semiconductor layers having different polarities, and at least two main electrode portions. The semiconductor device includes a control electrode portion which is provided in one semiconductor layer of the semiconductor element and has a semiconductor layer of the same polarity or of a different polarity from the one semiconductor layer, and between the control electrode portion and a main electrode adjacent to the control electrode portion. In the semiconductor device in which the channel region is formed, the width of the channel region is varied widely.

[0014]

According to the electrostatic induction type semiconductor device of the present invention, during the turn-off process, the current flowing through the narrow channel portion of the channel region is first interrupted, then the current is dispersed in the wide region, and finally, The current flowing through the wide part is cut off.

[0015]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows an electrostatic induction thyristor according to an embodiment of the present invention. In this embodiment, the width of the cathode layer 3 which is the main electrode portion is constant, and the gate layer 4 which is the control electrode portion. A wide portion 4a and a narrow portion 4b are formed in the channel region 5, and a narrow portion 5a and a wide portion 5b are formed in the channel region 5. This creates channel widths D and d, where D>
It becomes d. As an example, D = 8 μm and d = 4 μm.

FIG. 2 shows an electrostatic induction thyristor according to another embodiment of the present invention. In this embodiment, the width of the gate layer 4 is constant and the cathode layer 3 is formed with a wide portion 3a and a narrow portion 3b. Then, a narrow portion 5a and a wide portion 5b are formed in the channel region 5.

Further, FIG. 3 shows an electrostatic induction thyristor according to still another embodiment of the present invention, in which a wide portion 3a and a narrow portion 3b are formed in the cathode layer 3, and the gate layer 4 and the cathode layer 3 are formed. The wide portion 4a and the narrow portion 4b are formed to face the wide portion 3a and the narrow portion 3b, respectively, and the narrow portion 5a and the narrow portion 5b are formed in the channel region 5.
Therefore, the breaking resistance, the turn-off characteristic, and the turn-on characteristic are improved with almost no reduction in the effective area.

According to each of the electrostatic induction type thyristors shown in FIGS. 1 to 3, in the turn-off process, the current flowing through the narrow portion 5a of the channel region 5 is first cut off, and the wide portion 5 is cut off.
The current is dispersed in the region b, and finally the current flowing through the wide portion 5b is cut off. Therefore, it is possible to obtain the same blocking performance as that of increasing the number of channels without reducing the effective cathode area.

In order to smoothly disperse the current in the wide channel region in the turn-off process, the wide channel width (D) / narrow channel width (d) needs to be 1.2 or more. Although the electrostatic induction thyristor is described in FIGS. 1 to 3, similar effects and advantages can be obtained in the case of the electrostatic induction transistor. Further, in the above-described embodiment, the case where the channel width is changed to two types has been described, but the same action and effect can be expected even if three or more types are changed.

According to the electrostatic induction type semiconductor device of the above embodiment, the current concentration at turn-off is relaxed as compared with the conventional structure shown in FIG. 4, so that the breaking resistance is improved by 20% or more. In addition, in the turn-on process, a wide channel width region becomes a region where ignition is likely to occur, so that the initial firing region is dispersed and the turn-on characteristic is improved. Further, the manufacturing can be facilitated because the manufacturing can be easily performed by changing the diffusion mask pattern without changing the manufacturing process.

[0022]

As described above, according to the present invention, the anode layer made of the P-type semiconductor is formed on one main surface of the N base layer made of the N-type semiconductor, and the main surface opposite to the main surface is formed. Self-extinguishing semiconductor (SI thyristor) in which gates made of P-type semiconductor and cathode layers made of N-type semiconductor are alternately arranged on the surface, or N-type semiconductor on one main surface of N base layer made of N-type semiconductor A self-arc-extinguishing type semiconductor device (SIT) in which a drain layer made of P-type semiconductor and a source layer made of N-type semiconductor are alternately arranged on the main surface opposite to the main surface. Since the width of the channel region of the semiconductor device changes in the longitudinal direction, and the width and width of the semiconductor device are at least two types, wide and narrow, it is possible to obtain an electrostatic semiconductor device having excellent cutoff resistance and excellent turn-off and turn-on characteristics. Door can be.

[Brief description of drawings]

FIG. 1 is a front perspective view of an electrostatic induction type semiconductor device according to an embodiment of the present invention.

FIG. 2 is a front perspective view of an electrostatic induction semiconductor device according to another embodiment of the present invention.

FIG. 3 is a front perspective view of an electrostatic induction type semiconductor device according to still another embodiment of the present invention.

FIG. 4 is a front perspective view of a conventional static induction semiconductor device.

FIG. 5 is a cascode connection diagram of an electrostatic induction thyristor and a MOSFET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Anode layer 2 ... Base layer 3 ... Cathode layer 3a ... Cathode layer wide part 3b ... Cathode layer narrow part 4 ... Gate layer 4a ... Gate layer wide part 4b ... Gate layer narrow part 5 ... Channel region 5a ... narrow part of channel region 5b ... wide part of channel region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 29/804 (72) Inventor Fuki Haba 2-1-1-17 Osaki, Shinagawa-ku, Tokyo Stock Association Shameidensha

Claims (2)

[Claims] 1. A semiconductor element having at least one junction between at least two semiconductor layers having mutually different polarities, at least two main electrode portions, and one semiconductor layer provided on one semiconductor layer of the semiconductor element. In a semiconductor device in which a channel region is formed between the control electrode portion and a main electrode adjacent to the control electrode portion, the width of the channel region being a control electrode portion having a semiconductor layer of the same polarity or different polarity. An electrostatic induction type semiconductor device characterized in that it is configured to have a wide and narrow change. 2. The static induction semiconductor device according to claim 1, wherein the width of an arbitrary channel region changes in the longitudinal direction of the channel region, and at least the width of the channel region is wide or narrow. Static induction semiconductor device.