JPH05335425A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a method for foming a multilayered interconnection of high reliability, by preventing an insulating layer from being formed on a contact hole bottom part when it is cleaned, and improving the coverage of a wiring buried in a contact hole of vertical shape. CONSTITUTION:An insulating layer 6 is formed on a first conducting layer 5 formed on a substrate. A contact hole 7 is formed in the layer 6. A metal layer 8 is formed on the side wall of the contact hole 7. The substrate is irradiated with an etching beam from the vertical direction, and the bottom part of the contact hole 7 is subjected to surface treatment by ion milling. The substrate is inclined to the incidence direction of the etching beam, and only the metal layer 8 formed on the side wall of the contact hole 7 is etched, and the metal of the etched metal layer 8 is buried in the bottom part of the contact hole 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a surface treatment method for a bottom portion of a contact hole and a contact hole wiring embedding method in a multilayer wiring structure of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor integrated circuits has improved, contact holes formed in an interlayer insulating layer have been miniaturized, and the reliability of aluminum wiring formed by filling the miniaturized contact holes has become a serious problem. It was The fine contact hole itself can be realized by anisotropic etching. However, as the contact hole becomes finer, the aspect ratio becomes large, so that the coverage of the aluminum wiring formed there is extremely deteriorated.

As a method of preventing the deterioration of the covering property, a method of tapering a contact hole is known. Also,
The bottom of the contact hole is cleaned using an argon ion sputter etching method to remove the oxide formed on the surface of the lower layer aluminum wiring exposed in the contact hole, and then the contact hole is filled to form the upper layer aluminum wiring. The method is widely used.

[0004]

When argon ion sputter etching is performed to clean the bottom of the contact hole, insulators (atoms) sputtered at the tapered portion of the side wall of the contact hole are redeposited on the bottom of the contact hole. To form a thin insulating layer,
This may cause a contact failure between the lower layer wiring and the upper layer wiring. And the amount of this redeposition depends on the taper angle,
The maximum is around 60 to 70 °. Note that this tendency becomes more remarkable as the contact holes become finer. Further, when heat treatment (450 ° C.) is performed after sputter etching, the contact resistance tends to rapidly increase when the taper angle is 70 ° or less.

As the degree of integration is further increased in the future, the tapered shape of the contact hole is also restricted, and it becomes necessary to use the contact hole whose side wall is vertical. Therefore, a technique for forming a wiring having good coverage even in a vertical contact hole is desired.

An object of the present invention is to prevent an insulating layer from being formed at the bottom of the contact hole at the time of cleaning the bottom of the contact hole, and also in the case of a vertically shaped contact hole, the coverage of the wiring embedded therein is improved. Thus, it is to provide a method for forming a highly reliable multilayer wiring.

[0007]

The above-mentioned object is to form an insulating layer (6) on a first conductive layer (5) formed on a substrate (1) and to contact this insulating layer (6). After forming a hole (7) and forming a metal layer (8) on the side wall of the contact hole (7), an etching beam is vertically incident on the substrate (1) to contact the contact hole (7). Is subjected to a surface treatment by ion milling, and then the substrate (1) is inclined to the side wall of the contact hole (7) by inclining the substrate (1) with respect to the incident direction of the etching beam to an angle at which the bottom of the contact hole is not etched. Only the formed metal layer (8) is etched, and the metal of the etched metal layer (8) is embedded in the bottom of the contact hole (7),
Semiconductor device comprising a step of filling the contact hole (7) having the metal of the metal layer (8) buried in the bottom to form a second conductive layer (9) on the insulating layer (6). It is achieved by the manufacturing method of.

It is preferable that the surface treatment step of the bottom of the contact hole (7) and the step of embedding a metal in the bottom of the contact hole (7) are successively performed in the same reaction vessel. The first conductive layer (5) is often a silicon layer or an aluminum layer, and the second conductive layer (9) is often an aluminum layer. The metal layer (8) is preferably made of a metal selected from the group of refractory metals such as titanium, tungsten, molybdenum and tantalum, or a nitride of this metal.

[0009]

As shown in FIG. 1A, a metal layer 8 is formed on the side wall of the contact hole 7 formed in the insulating layer 6, and argon ions are vertically applied to the substrate 1 by using an ion milling method. When the surface treatment of the bottom of the contact hole 7 is performed by irradiating the beam, the edge of the upper side wall of the contact hole 7 is covered with the metal layer 8. Therefore, even if this edge is etched, the bottom of the contact hole 7 is etched. Even if it is redeposited, since the redeposit is a metal, a contact failure does not occur between the upper layer wiring (not shown) formed by filling the contact hole 7 and the lower layer wiring 5.

Subsequently, as shown in FIG. 1B, the substrate 1 is formed on the side wall of the contact hole 7 by inclining the substrate 1 with respect to the incident direction of the argon ion beam so that the bottom of the contact hole 7 is not etched. When the metal layer 8 present is sputter-etched, the sputtered metal atoms are redeposited on the bottom and side walls of the contact hole 7 and buried in the bottom of the contact hole 7 as shown in FIG.

As a result of the above, the bottom of the contact hole 7 is cleaned, and the coverage of the upper wiring formed on the insulating layer 6 by filling the contact hole 7 becomes extremely good.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of forming a multi-layer wiring according to an embodiment of the present invention will be described below with reference to the drawings.

Referring to FIG. 2, a diffusion layer 2 is formed on a partial region of a silicon substrate 1, and then a silicon dioxide layer 3 is formed on the entire surface to a thickness of 1.0 μm. A contact hole is formed in the silicon dioxide layer 3 on the diffusion layer 2. 4 is formed.

By using a sputtering method, the contact hole 4 is filled up, an aluminum layer 5 is deposited on the silicon dioxide layer 3 to a thickness of 7,000 Å, and this is patterned to form a lower layer wiring.

A silicon dioxide layer 6 having a thickness of 1.0 μm is formed on the entire surface by a CVD method, and a contact hole 7 having a diameter of 1.0 μm is formed in the silicon dioxide layer 6 on the lower wiring 5 by a photolithography method. Form.

A titanium nitride (TiN) layer having a thickness of 1000 Å is formed on the silicon dioxide layer 6 including the side wall of the contact hole 7. Then, using a plasma etching method, 100 SCCM of chlorine gas is supplied to the reaction chamber to set the pressure in the reaction chamber to 1.0 mTorr, and a plasma discharge force of 300 W is applied to perform plasma etching to remove the side wall of the contact hole 7. The titanium nitride layer is removed from the removed region to form a titanium nitride layer 8 on the side wall of the contact hole 7.

The subsequent steps will be described below with reference to FIG. 1 in which the vicinity of the contact hole is enlarged. Note that FIG.
The same members as the members shown in FIG. See FIG. 1A. Using an ion milling method, the substrate is irradiated with an argon ion beam at a right angle to remove the oxide film from the lower wiring 5 exposed at the bottom of the contact hole 7. At this time, the upper end portion of the titanium nitride layer 8 formed on the side wall of the contact hole 7 is sputtered and the contact hole 7
A thin deposit on the bottom of the.

Next, referring to FIG. 1 (b), the substrate 1 is tilted at an angle such that the bottom of the contact hole 7 is not etched, and the substrate 1 is 2.5 to 4.0 mA / c.
The titanium nitride layer 8 formed on the side wall of the contact hole 7 is sputter-etched by irradiating an argon ion beam having a current density of m ² . In addition, so that the entire circumference of the side wall of the contact hole 7 is sputter-etched,
The substrate 1 is rotated about the center line AA ′ of the contact hole 7 as a rotation axis. In addition, in this embodiment, the angle φ formed between the substrate 1 and the ion beam incident direction is 39
If the angle is less than 0 °, the bottom of the contact hole 7 is not etched.

1C, the titanium nitride layer 8 sputter-etched is deposited on the bottom of the contact hole 7, and the contact hole 7 is embedded in the shape shown in FIG. 1C.

Referring to FIG. 3, by using the sputtering method, an aluminum layer 9 is formed on the silicon dioxide layer 6 by filling the contact hole 7, and the aluminum layer 9 is patterned to form an upper layer wiring 9 connected to the lower layer wiring 5.

[0021]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the metal layer is formed on the side wall of the contact hole to perform the surface treatment on the bottom portion of the contact hole. Insulation does not redeposit on the surface. Further, since the metal formed on the side wall of the contact hole is sputter-etched to fill the bottom of the contact hole with the metal, the coverage when the contact hole is filled and the upper layer wiring is formed is good, and the reliability is high. Multilayer wiring is formed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a multilayer wiring forming process according to the present invention.

FIG. 3 is an explanatory diagram of a multilayer wiring forming process according to the present invention.

[Explanation of symbols]

 1 Substrate 2 Diffusion Layer 3.6 Insulation Layer (Silicon Dioxide Layer) 4.7 Contact Hole 5 First Conductive Layer (Aluminum Layer) 8 Metal Layer (Titanium Nitride Layer) 9 Second Conductive Layer (Aluminum Layer)

Claims (4)

[Claims] 1. An insulating layer (6) is formed on a first conductive layer (5) formed on a substrate (1), and a contact hole (7) is formed in the insulating layer (6). A metal layer (8) is formed on a sidewall of the contact hole (7), an etching beam is incident on the substrate (1) in a vertical direction, and the bottom of the contact hole (7) is surface-treated by ion milling; The substrate (1) is tilted with respect to the incident direction of the etching beam to an angle at which the bottom of the contact hole is not etched, and only the metal layer (8) formed on the sidewall of the contact hole (7) is etched. The metal of the etched metal layer (8) is embedded in the bottom of the contact hole (7), the metal of the metal layer (8) is embedded in the contact hole (7) embedded in the bottom, and the insulating layer is formed. The second on 6)
2. A method of manufacturing a semiconductor device, comprising the step of forming a conductive layer (9). 2. The step of surface-treating the bottom of the contact hole (7) and the step of embedding a metal in the bottom of the contact hole (7) are performed continuously in the same reaction vessel. Item 1. A method of manufacturing a semiconductor device according to item 1. 3. The semiconductor according to claim 1, wherein the first conductive layer (5) is a silicon layer or an aluminum layer, and the second conductive layer (9) is an aluminum layer. Device manufacturing method. 4. The metal layer (8) is made of a metal selected from the group of refractory metals such as titanium, tungsten, molybdenum and tantalum, or a nitride of the metal. Or the method for manufacturing a semiconductor device according to the item 3.