JPH05334257A - Parallel processor - Google Patents

Abstract

PURPOSE:To improve a processing speed by comparing the predicted value of a transmission time at the time of compression with that at the time of non-compression based on a communication amount at the transmission start time of a communication line and the size of data to be transmitted, and transmitting the data whose communicating time is shorter, together with compression information. CONSTITUTION:In the transmission and reception of the data between parallel processor, at the time of a transmission start, the communication amount of a serial transmission line 13 is observed by a communication amount observing circuit 11, and the compression transmitting time required for compressing and transmitting the communication amount and the non-compression transmitting time required for non-compressing and transmitting it are predicted. At that time, the predicted transmitting time at the time of compression is the total of a predicted compression processing time, predicted communicating time, predicted compression/extension judgement processing time and predicted extending time. Then, the processing time at the time of compression is compared with that at the time of non- compression, and the data whose communicating time is shorter, are selected, and transmitted. At the parallel processor at a reception side, the received data are judged by a compression/ non-compression judgement signal 14 or the like received together with the received, data and received being extended when the data are the compressed data, and received as they are when the data are the non-compressed data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing device for large-scale processing such as image processing, signal processing and database processing.

[0002]

2. Description of the Related Art A conventional parallel processor is shown, for example, in Transputer Data Book manufactured by INMOS Division of SGS Thomson. FIG. 7 is a block diagram of this conventional parallel processor, in which 31 is a central processing unit, 32 is a floating point arithmetic unit for performing floating point arithmetic, and 33 is a serial data transfer for connection with other parallel processors. Link interface for enabling the above, 34 is an input to a system service device such as power input, ground ground, clock input, reset signal, 35 is a system service device for processing the input, 36 is an on-chip memory , 37 is an external memory interface that controls the connection of the parallel processor to an external memory, 38 is an external memory bus that connects the external memory interface and the external memory, 39 is an event processing device that processes an external event, 40 is an internal bus.

FIG. 8 is a diagram in which a plurality of parallel processors shown in FIG. 7 are connected in a grid. In FIG. 8, 41-
49 is the parallel processor shown in FIG. 7 and 41 is the position (p
-1, q-1) parallel processor, 42 is position (p, q
-1) parallel processor, 43 is position (p + 1, q-
1) parallel processor, 44 is a parallel processor at position (p-1, q), 45 is a parallel processor at position (p, q), 46 is a parallel processor at position (p + 1, q), 47
Is a parallel processor at position (p-1, q + 1), 48 is a parallel processor at position (p, q + 1), and 49 is a position (p +
1, q + 1) parallel processors, and 50 is a signal line connecting the link interfaces 33 of the parallel processors shown in FIG.

FIG. 9 shows an image processed by the system configured as shown in FIG. 8. In the figure, two vertical broken lines and two horizontal broken lines form nine images. The divided image area indicates an area of processing which each parallel processor is in charge of. In FIG. 9, 51 is a position (p-1, q-
1) the image area processed by the parallel processor, 52 the image area processed by the parallel processor at position (p, q-1),
53 is the image area processed by the parallel processor at position (p + 1, q-1), 54 is the image area processed by the parallel processor at position (p-1, q), and 55 is the parallel processor at position (p, q). Image region to be processed, 56 is position (p + 1,
q) the image area processed by the parallel processor, 57 is the image area processed by the parallel processor at position (p-1, q + 1), 58 is the image area processed by the parallel processor at position (p, q + 1), and 59 is the position This is an image area processed by the (p + 1, q + 1) parallel processor. In FIG.
Reference numerals 60 and 61 denote three-dimensional solid figures displayed in FIG.

The operation of the conventional parallel processor configured as described above will be described below. Figure 7
The parallel processor is loaded with a program from the outside via the link interface 33, and stores the program in the external memory connected to the outside of the parallel processor via the on-chip memory 36 or the external memory interface 37. The processing in the processor is CP
It is performed by U31 and FPU32. System services such as power input, ground grounding, clock input, and reset signal are provided by the system service device 35.
Although the parallel processor can operate by itself, it is designed on the premise that it is connected to each other as shown in FIG. 8 by the link interface 33 and functions. The parallel processors 41 to 49 connected in a grid pattern as shown in FIG. 8 operate while exchanging information with each other via the link interface 33. The image of FIG. 9 is divided into a plurality of image areas 51 to 59, and the parallel processors 41 to 49 are in charge of processing. At this time, information is exchanged between the parallel processors 41 to 49, which is also performed via the link interface 33. For example, when sending information from the parallel processor 41 to the parallel processor 49, there are several routes. For example, the parallel processors 41 → 42 → 43 →
Information will be sent from 46 to 49 through the three parallel processors. In this way, a plurality of processes that can be processed at the same time are processed in parallel to complete the process of FIG. 9 in which the image of FIG. 10 is divided into nine.

[0006]

However, in the above configuration, since the parallel processors are connected by the link line for serial data transfer, the information transmission to the parallel processors in the four directions is performed. Was very time consuming. In particular, when a plurality of data are transmitted and received using the same link line, it takes a long time, so that the whole processing time is not accelerated by the parallel processing.

In view of the above points, the present invention is a parallel processor having a function of operating by connecting a plurality of each other, and in transmitting and receiving data between the parallel processors,
Based on the communication volume at the start of transmission of the communication line used for transmitting and receiving data and the size of data to be transmitted, it is necessary to calculate the compressed transmission time required for compressed transmission and the uncompressed transmission time. Let's receive by comparing with the predicted value of the uncompressed transmission time and transmitting by the shorter communication time, and means for indicating the information that the data to be transmitted and received is compressed data or uncompressed data. It is intended to provide a parallel processor characterized by including means for decompressing data to be compressed data according to the value of the information and receiving it, and receiving uncompressed data as it is. To do.

[0008]

SUMMARY OF THE INVENTION The present invention is a parallel processor having a function of operating by connecting a plurality of them to each other, and in transmitting and receiving data between the parallel processors,
Based on the communication volume at the start of transmission of the communication line used for transmitting and receiving data and the size of data to be transmitted, it is necessary to calculate the compressed transmission time required for compressed transmission and the uncompressed transmission time. Let's receive by comparing with the predicted value of the uncompressed transmission time and transmitting by the shorter communication time, and means for indicating the information that the data to be transmitted and received is compressed data or uncompressed data. According to the value of the information, the parallel processor is provided with means for decompressing compressed data and receiving it, and receiving uncompressed data as it is.

[0009]

According to the present invention, due to the above-mentioned configuration, the data transfer rate between parallel processors is increased and the overall processing speed is improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a configuration example of a parallel processor in one embodiment of claim 1 of the present invention, FIG. 2 is a communication format of one embodiment in claim 2, and FIG. 3 is a transmission in the parallel processor of the present invention. 5 is a flowchart showing the operation at the time of data reception, FIG. 4 is a flowchart showing the operation at the time of data reception, and FIG.
Is a diagram for explaining the operation when compressed and sent.
FIG. 6 is a diagram for explaining the operation in the case of non-compressed transmission.

In FIG. 1, 1 is a central processing unit, 2 is a floating point arithmetic unit for performing floating point arithmetic, 3 is a link interface for enabling data transfer with other parallel processors, 4 is power input, Inputs to the system service device such as ground ground, clock input, reset signal, etc., 5 is a system service device for processing said input,
Reference numeral 6 is an on-chip memory, 7 is an external memory interface that controls connection to the external memory of the parallel processor, 8 is an external memory bus that connects the external memory interface and the external memory, and 9 is an event from the outside. An event processing device, 10 is an internal bus, 11 is a communication state observing circuit, 12 is a serial reception line from the outside of the parallel processor of the communication lines of this embodiment, and 13 is the parallel of the communication lines of this embodiment. A serial transmission line from the outside of the processor, 14 is a compression / non-compression determination signal according to claim 1, 15 is a predicted transmission time when compressed and transmitted, and a predicted transmission time when uncompressed. It is a predictor that determines if it is short. In FIG. 4, τ1 (α) is the predicted compression / expansion determination time, which is the time estimated to be required to determine whether the received data is compressed data or uncompressed data. Where τ1 (α)
Is a constant value regardless of the data amount α. τ2 (β)
Is a predicted compression processing time, which is a time value predicted to be required to compress the data amount β of data. τ3
(Γ, ε) is an estimated communication time, which is a time value estimated to be required to transmit data of the data amount γ under the communication amount ε. τ4 (δ) is a predicted decompression processing time, which is a time value predicted to be necessary for decompressing the data of the data amount δ.

The operation of the parallel processor of this embodiment constructed as above will be described below. The parallel processor of FIG. 1 is loaded with a program from the outside via the link interface 3, and stores the program in the external memory connected to the outside of the parallel processor via the on-chip memory 6 or the external memory interface 8. The processing is performed by the CPU 1 and the FPU 2.
System services such as power input, ground grounding, clock input, and reset signal are performed by the system service device 5. The parallel processors can operate by themselves, but it is premised that they are connected to each other by the link interface 3 and function. A four-way link interface 3 is provided to communicate with four parallel processors.

During this communication, as shown in FIG. 3, at the time of transmission, the communication state observing circuit 11 observes the communication amount ε of the serial transmission line 13, which is a communication line, and sends it to the predictor 15. The predictor 15 receives the communication amount ε, and calculates a predicted transmission time when compressed and transmitted when compressed and a predicted time when uncompressed when transmitted without compression.
The predicted transmission time T at the time of compression is, as shown in FIG. 4, predicted compression processing time τ2 (β), predicted communication time τ3 (γ, ε),
It is calculated by the sum of the predicted compression / expansion determination processing time τ1 (α) and the predicted expansion time τ4 (δ). In addition, the predicted transmission time T ′ when not compressed is τ3 ′ (γ, ε) as shown in FIG.
It becomes the value of. The processing time T at the time of compression and the processing time T ′ at the time of non-compression are compared, and the one having the shorter communication time is selected, and when compressed and transmitted, the central processing unit 1 compresses and transmits, and the uncompressed. When sending by, send it as is.

At the time of compressed transmission, compression / non-compression determination signal 1
4 is set to a value meaning compression, and when uncompressed transmission is compressed /
The non-compression determination signal 14 is set to a value meaning non-compression.

In FIG. 4, the first bit of the communication format is set to a value meaning compression when compressed and a value meaning noncompression when uncompressed, and the data to be transmitted is compressed data or uncompressed data. Indicates

In the parallel processor on the receiving side, the compression /
As shown in FIG. 4, either the non-compression determination signal 14 or the compression / decompression flag 20 determines whether the received data is compressed data or non-compressed data.
It is decompressed and received, and uncompressed data is received as it is.

As described above, according to this embodiment, the data transfer speed is increased in the communication between the parallel processors, and the overall processing speed can be improved.

[0018]

As described above, a parallel processor having a function of operating by connecting a plurality of each other,
In data transmission / reception between the parallel processors, a prediction of a compression transmission time required when compressed and transmitted based on a communication amount at a transmission start time of a communication line used for transmitting / receiving data and a data size to be transmitted. Compare the value with the predicted value of the uncompressed transmission time required when transmitting with uncompressed,
A means for transmitting in a shorter communication time, a means for indicating the data to be transmitted / received is compressed data or uncompressed data, and the data to be received according to the value of the information, By providing a means to decompress compressed data and receive it, and to receive uncompressed data as it is, the communication speed between parallel processors is increased, the overall processing speed is improved, and its practical effect is great. ..

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel processor according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a communication data format in the parallel processor.

FIG. 3 is a diagram showing a flow of processing when transmitting the same data.

FIG. 4 is a diagram showing a flow of processing when receiving the same data.

FIG. 5 is a diagram for explaining the operation when the data is compressed and transmitted.

FIG. 6 is a diagram for explaining an operation when data is transmitted without being compressed.

FIG. 7 is a block diagram of a conventional parallel processor.

FIG. 8 is a diagram in which a plurality of conventional parallel processors are connected in a grid pattern.

FIG. 9 is a diagram showing an image processed by a conventional system.

FIG. 10 is a diagram showing a conventional three-dimensional figure.

[Explanation of symbols]

 1 central processing unit 2 floating point arithmetic unit 3 link interface 4 input to system service unit 5 system service unit 6 on-chip memory 7 external memory interface 8 external memory bus 9 event processing unit 10 internal bus 11 communication state observation circuit 12 serial reception Line 13 Serial transmission line 14 Compressed / non-compressed judgment signal 15 Predictor

Claims (2)

[Claims] 1. A parallel processor having a function to operate by connecting a plurality of each other, and in transmitting and receiving data between the parallel processors, at the start of transmission of a communication line used for transmitting and receiving data. Based on the communication volume and the data size to be transmitted, compare the predicted value of the compressed transmission time required for compressed transmission with the predicted value of the uncompressed transmission time required for uncompressed transmission, and A means for transmitting in the shorter one, and a signal line indicating information whether the data to be transmitted and received is compressed data or uncompressed data,
Depending on the value of the signal line, the data to be received is expanded if it is compressed data and received, if it is uncompressed data,
A parallel processor having means for receiving as it is. 2. A parallel processor having a function of operating by being connected to each other, wherein data is transmitted and received between the parallel processors at a transmission start point of a communication line used for transmitting and receiving data. Based on the communication volume and the data size to be transmitted, compare the predicted value of the compressed transmission time required for compressed transmission with the predicted value of the uncompressed transmission time required for uncompressed transmission, and A means for transmitting in the shorter one, a data format to be transmitted and received, a communication format having a flag indicating whether it is compressed data or uncompressed data, and the data to be received according to the value of the flag, A parallel processor, characterized in that it comprises means for decompressing compressed data and receiving it, and receiving uncompressed data as it is.