JPH05334192A - Cpu address translation system - Google Patents

Abstract

PURPOSE:To make an effective use of a program resource prepared corresponding to a plurarity of memory management systems by translating one part of values in advance so as to make an accurate logic address translation in the other system. CONSTITUTION:A CPU 1 reads a base address by referring to a segment information block 2 indicated by a segment register 11 when a segment and an offset are specified, makes a linear address by adding the valid offset to translate it into a physical address by referring to a page table 3. In the case of shifting a system from a segmentation paging system to the other system, the CPU 1 saves information in the segment register 11, rewriting it to a base address value in the segment information block 2. In the other system, the segment register 11 can use the offset as a based modification register, normally performing the address translation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU address conversion system for use in a computer or the like and switching a plurality of systems to execute memory management.

[0002]

2. Description of the Related Art In the conventional CPU address conversion method, only one method during segmentation or paging is realized. Or, some of the methods can be switched. Such a conventional CPU address conversion method has a paging mechanism and a segmentation mechanism, and may further include a real address virtualization mechanism for realizing a memory management method in which a segment indication value linearly corresponds to an address space. .. By having these mechanisms, it is possible to dynamically switch the memory management system.

When operating the segmentation / paging method, the segmentation mechanism and the paging mechanism are simultaneously selected. Then, the segment instruction register in the CPU is validated to store a pointer to the segment information block in the memory, the management address is converted into a linear address according to the in-block information, and further converted into a physical address by the page table.

In the case of operating only the paging method, the segmentation mechanism and the segment register are invalidated. Or select a segmentation mechanism,
All segments point to the entire linear address space so that the logical address and the linear address match, and the paging mechanism refers to the page table to convert the linear address into a physical address.

Further, in the real address virtualization mechanism, the contents of the segment designation register are linearly converted into a linear address or a physical address.

[0006]

As described above, the conventional C
In the PU address conversion method, the meaning of the logical address changes when the memory management method is dynamically changed, and especially the conversion method of the value stored in the segment instruction register changes. Therefore, when passing data on the real memory between programs of different memory management methods by using a logical address, even if the same linear address space is shared,
Logical address translation processing on the program side is required.
In addition, in some cases, even segment information block generation processing is required, and there is a problem that the degree of dependence on a memory management method other than the self program is large and the processing itself becomes an overhead.

The present invention solves the problems in the prior art as described above, and makes it possible to effectively utilize the program resources created corresponding to a plurality of memory management methods.
It is intended to provide a PU address conversion method.

[0008]

In order to achieve the above object, the CPU address conversion method of the present invention represents a pointer to a segment information block when a segmentation mechanism is selected and transits to a non-selected state. In this case, the segment register that represents the base address in the corresponding block and is used for the base modification, and the linear address that the program uses as the offset when the segmentation mechanism is selected. When the real address virtualization mechanism is selected, it is used as a segment indication register in that mode and contains the value linearly corresponding to the linear address, and the value after linear conversion when transitioning to the unselected state. Represents the virtual model And a de-segment register.

[0009]

In the CPU address conversion system of the present invention as described above, the conventional segment designation uses the base address in the segment information block through the segmentation mechanism by designating the segment register.

When a paging linear address is used, the linear address can be virtualized into an offset by designating a dedicated segment indicator. The logical address in the real address virtualized state uses the virtual segment register as the segment value with offset-based modification, and the segment is virtualized by specifying the dedicated segment indicator for the linear address.

In the paging system, the segment register of the segment value in another system or the virtual segment register is designated as the base modification register,
Virtualize to linear address with offset.

In the real address virtualized state, the segment register designation in the segmentation / paging method is a base modification register, and the segment designation is virtualized by using a segment specifier dedicated to the linear address. Uses a linear address dedicated segment indicator to specify the segment and virtualizes it as an offset.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the CPU address conversion system of the present invention will be described with reference to the drawings. 1, 2, and 3 show the contents of each process in the embodiment. 1, 2, and 3, this example includes a CPU 1, a segment information block 2, and a page table 3. CPU
1 is the segment register 11 and the linear address-corresponding segment information 12 which is referred to when the linear address dedicated segment indicator is designated as a logical address,
A virtual segment register 13 is provided.

Next, the processing in the configuration of this embodiment will be described. During execution of the segmentation / paging method shown in FIG. 1, the program normally uses the segment register 11 to specify a segment. CP
When the segment and offset are designated, U1 reads the base address by referring to the segment information block 2 pointed to by the segment register 11, adds the effective offset to make it a linear address, and refers to the page table 3 to convert it to a physical address. .. Then, when shifting from the segmentation / paging method to another method, the CPU
1 saves the information in the segment register 11 and rewrites it to the base address value in the segment information block 2. In another method, the segment register 11 can use the offset as a base modification register, and the address is normally converted.

Next, when the paging method shown in FIG. 2 is executed, the logical address is equal to the linear address, and C
The PU 1 directly translates the effective linear address into the physical address in association with the page table 3. In the case of shifting to another system, the linear address can be regarded as an offset within the segment that represents the entire linear address space, so the linear address corresponding segment information 1 in which the base address of the segment indicates the beginning of the linear address space
2 is designated as a segment by using the segment indicator dedicated to the linear address. By this specification, the address is normally converted by using the linear address as the offset.

In the real address virtualized state shown in FIG. 3, a segment value of a normal logical address is linearly converted into a segment base address, and an offset is added to the page table 3 as a linear address to be converted into a physical address. The virtual segment register 13 for storing the segment value is used by the CPU when the memory management method is changed to another memory management method.
The content is saved by 1 and replaced with the value after linear conversion. In other methods, the virtual segment register 13 has a value that is synonymous with the linear address, and the address is correctly converted by the above addressing method.

[0017]

As described above, according to the CPU address conversion method of the present invention, when a different memory management method is adopted, some values are set so that logical addresses in other methods are correctly converted in the method. Since the conversion is performed in advance, there is an effect that the program resources created corresponding to a plurality of memory management methods can be effectively used. That is, a program of a different memory management method can refer to the data on the real memory without changing the address specification when the data is transferred by using the logical address without executing the process by the program. Therefore, the dependence on the memory management method other than the self program is low, and the processing overhead can be erased on the program side.

[Brief description of drawings]

FIG. 1 is a block diagram showing processing contents when executing a segmentation / paging method in an embodiment of a CPU address conversion method of the present invention.

FIG. 2 is a block diagram showing the processing contents when the paging method is executed in the embodiment.

FIG. 3 is a block diagram illustrating processing contents in a real address virtualization state according to the embodiment.

[Explanation of symbols]

 1 CPU 2 Segment information block 3 Page table 11 Segment register 12 Linear address corresponding segment information 13 Virtual segment register

Claims (1)

[Claims] 1. A segment register used for the base modification by representing a pointer to a segment information block when the segmentation mechanism is selected, and representing a base address in the corresponding block when a transition to a non-selected state is made. , If the segmentation mechanism is selected, the program uses the linear address as an offset for the dedicated segment indicator for the linear address full space, and if the real address virtualization mechanism is selected, the segment indicator register in that mode And a virtual mode segment register that includes a value linearly corresponding to a linear address and that represents a value after linear conversion when a transition is made to a non-selected state and is used for the base modification. CPU address conversion method ..