JPH05330154A - Image processor - Google Patents

Abstract

PURPOSE:To lighten the processing burden of a CPU (a central processing unit) while carrying out data transfer at a high speed. CONSTITUTION:An image processor has an image processing circuit 102 executing various processing to image data, a first CPU 101 indicating processing content to the image processing circuit 102, an FIFO memory 104, in which one line section of image data is stored, a second CPU 107 transferring data stored to a frame buffer memory 110 and outputting data for outputting an image and a printer-DRAM control circuit 106 executing DRAM control, etc. The image processor is further composed of an FIFO control circuit 108 occupying the data bus of the second CPU 107 and transferring the data of the FIFO memory 104 to the frame buffer memory 110 through the printer-DRAM control circuit 106 for an occupying period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a digital copying machine, a facsimile machine, a printer, an image scanner, and more specifically, a first CP for instructing image processing.
The present invention relates to an image processing apparatus provided with a U and a second CPU for data transfer, and performing high-speed transfer from a memory storing data after image processing to a print buffer using a data bus of the second CPU.

[0002]

2. Description of the Related Art A block diagram of a control system in a conventional image processing apparatus is shown in FIG. In FIG. 3, 301 is a CPU that executes each control of the control system, 302 is an image processing circuit that executes MTF correction, correction processing such as dither pattern, and 3
Reference numeral 03 is an image sensor using a CCD (charge coupled device) or the like, which optically reads an original to be read and photoelectrically converts it.
A FIFO 304 stores image data for one line
A (First In First Out) memory 310 is a frame buffer memory (print buffer) that stores image data for print output or the like.

In the above, the CPU 301 is the FIFO
The data stored in the memory 304 is read and the CPU
It stores in the register in 301. After that, the operation of writing to the frame buffer memory 310 is repeatedly executed.

[0004]

However, in the conventional image processing apparatus as described above, since each control is executed by one CPU (301), the CP
There is a problem that the load on the U (301) increases and the data transfer speed is limited by the read / write cycle of the CPU (301), so that high-speed data transfer processing cannot be performed.

The present invention has been made in view of the above, and an object thereof is to reduce the processing load on a CPU (central processing unit) and to realize high-speed data transfer.

[0006]

In order to achieve the above object, the present invention provides an image processing means for inputting read image data and executing a predetermined process, and a processing content for the image processing means. First control means for instructing, data storage means for storing one line of the image data processed by the image processing means, image data stored in the data storage means, transferred to a print buffer, and image output Second control means for outputting data for use, printer control means for executing DRAM control and bitmap processing, and a data bus for the second control means, and the data storage means within the exclusive period. And a data storage control means for transferring the data of (1) to the print buffer via the printer control means.

The data storage means is a FIFO.
A (first in, first out) memory is desirable.

Further, it is desirable to execute the transfer for each line from the data storage means to the print buffer within a line start signal.

Further, the start of data transfer from the data storage means is determined based on the number of pixels to be written in the data storage means, and the second control means performs data write for the number of pixels in one line. It is desirable to perform data transfer by repeatedly executing.

Further, it is desirable to change the transfer start position of the data.

Further, it is desirable that the data bus from the data storage means is returned to the second control means based on an empty flag signal for detecting a state where there is no data in the data storage means.

Also, the first control means or / and
It is desirable that the data in the data storage means be cleared by outputting a reset signal from the second control means to the data storage means.

[0013]

The image processing apparatus according to the present invention separates only the data bus from the second control means, occupies the data bus exclusively for data transfer of the data storage means, and prints the image data stored in the data storage means. Transfer to buffer.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a control system of an image processing apparatus according to the present invention. 2 is a timing chart showing the operation of the control system according to the present invention. Figure 1
In FIG. 1, reference numeral 101 denotes a first CPU (central processing unit), which is connected to the image processing circuit 102 and executes setting of correction values for each image processing to the image processing circuit 102. Further, 102 is an image processing circuit that executes correction processing such as MTF correction and dither pattern, and 103 is an image sensor that uses a CCD (charge coupled device) or the like that optically reads an original document to be read and performs photoelectric conversion. ..

Reference numeral 104 denotes a FIFO (First In First Out) for storing image data for one line.
It is a first-in first-out memory and is connected to the data bus of the printer / DRAM control circuit 106 via the bus buffer 105. Further, 105 is a bus buffer, and 106 is a printer / DRAM control circuit having an address register and a data register. Every time data is latched in the data register, the address set in the address register is automatically incremented, and a frame buffer memory is provided. Has the function of accessing 110,
In addition, it is configured so that it can be expanded into a bitmap. 107
Is a second CPU that executes processing such as transferring the data in the FIFO memory 104 to the frame buffer memory 110 and outputting it as video data of the printer, and its address bus is the printer / DRAM control circuit 106.
And the FIFO control circuit 108.

A FIFO control circuit 108 generates a read clock from the FIFO memory 104 and bus control signals for the bus buffers 105 and 109.
Further, 109 is a bus buffer, and 110 is a frame buffer memory (print buffer) for accumulating image data for printing output or the like. Also, 111 is the first C
It is an AND circuit that executes an AND process of the RST1 signal and the RST2 signal from the PU 101 and the second CPU 107.

Reference numeral a in the drawing denotes WRC indicating a write clock synchronized with the read clock to the image sensor 103.
K signal, b is a FEMP signal for detecting the presence / absence of data in the FIFO memory 104, c is an RDCK signal indicating a read clock for reading data from the FIFO memory 104, d is an FSEL signal serving as a control signal for the bus buffers 105 and 109, e is an SIRQ signal that is an interrupt request, f
Is RST1 indicating a reset signal from the first CPU 101
A signal, g is an RST2 signal indicating a reset signal from the second CPU 107, and h is an SI signal indicating a reading start signal (line start signal) in the main scanning direction for each line.

Next, the operation of the control system of the image forming apparatus configured as described above will be described with reference to FIGS. When writing data in the FIFO memory 104, the image processing circuit 102 outputs the WRCK signal a and executes the writing process. At the same time, the image processing circuit 102
When the RCK signal a is counted and reaches a predetermined value,
The SIRQ signal e is output to the second CPU 107 to execute the interrupt request. Then, the second CPU 107 generates a predetermined address in response to the interrupt request.

The FIFO control circuit 108 decodes the address and decodes it into the FIFO memory 104.
An FEMP signal b for detecting the presence / absence state of data in the inside generates an FSEL signal d as a bus control signal and an RDCK signal c as a read clock. RDCK signal c
Is synchronized with the cycle clock of the second CPU 107, and the printer / DRA is active while the FSEL signal d is active.
Data is read from the FIFO memory 104 to the data bus of the M controller circuit 106. At this time, the second
The CPU 107 repeatedly executes the write operation on the data register of the printer / DRAM controller circuit 106.

As described above, when the data in the FIFO memory 104 is transferred to the frame buffer memory 110,
Only the data bus is separated from the second CPU 107, and the data bus is exclusively used by the FIFO memory 104. As a result, data can be transferred from the FIFO memory 104 to the frame buffer memory 110.

In the above, the FIFO memory 10
The data transfer for each line from 4 to the frame buffer memory 110 is executed within the SI signal h. by this,
Since the first CPU 101 and the second CPU 107 can receive and process instructions between lines, the CPU
Processing efficiency is improved.

Further, the start of data transfer from the FIFO memory 104 is determined based on the writing density (the number of pixels) to the FIFO memory 104, and the second CPU 107 repeats the data write for the number of pixels of one line. Perform data transfer. As a result, high-speed data transfer is realized and the processing load on the first CPU 101 is reduced.

If the start position of data transfer is changed, for example, it is possible to transfer data in the same operation even in the case of multi-valued data and binary data.

Further, in the above-mentioned configuration, when the data bus from the FIFO memory 104 is returned to the second CPU 107, it is executed based on the empty flag of the FEMP signal b which detects the state that there is no data in the FIFO memory 104. As a result, the first CPU 101 and the second CP
Since the U107 can clear the FIFO memory 104, the data bus can be returned to the second CPU 107 from any CPU.

Further, by sending a reset signal (RST1 / RST2) from the first CPU 101 or / and the second CPU 107 to the FIFO memory 104, the F
The data in the IFO memory 104 can be cleared. For this reason, the data bus can be returned to the second CPU 107 from any CPU.

[0026]

As described above, according to the image processing apparatus of the present invention, the image processing means for inputting the read image data and executing the predetermined processing, and the processing contents for the image processing means are described. First control means for instructing, data storage means for storing one line of image data processed by the image processing means, and image data stored in the data storage means are transferred to a print buffer for image output. Second control means for outputting the data, printer control means for executing the DRAM control and bitmap processing, and the data bus of the second control means, and the data storage means of the data storage means within the exclusive period. Since the data storage control means for transferring data to the print buffer via the printer control means is provided, the processing load on the CPU (central processing unit) is reduced. While, high speed data transfer is realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a control system of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart showing an operation example of the image processing apparatus shown in FIG.

FIG. 3 is a block diagram showing a control system of a conventional image processing apparatus.

[Explanation of symbols]

101 First CPU 102 Image Processing Circuit 103 Image Sensor 104 FIFO Memory 105 Bus Buffer 106 Printer / DRA
M control circuit 107 Second CPU 108 FIFO control circuit 109 Bus buffer 110 Frame buffer memory

Claims (7)

[Claims] 1. An image processing unit for inputting read image data to execute a predetermined process, a first control unit for instructing the image processing unit about processing contents, and an image processing unit for processing the image processing unit. Data storage means for storing one line of the image data, second control means for transferring the image data stored in the data storage means to a print buffer, and outputting data for image output, DRAM control and bit Printer control means for executing map processing,
Data storage control means for exclusively occupying the data bus of the second control means and for transferring the data of the data storage means to the print buffer via the printer control means within the exclusive period. Image processing device. 2. The image processing apparatus according to claim 1, wherein the data storage unit is a FIFO (First In First Out) memory. 3. The image processing apparatus according to claim 1, wherein transfer of each line from the data storage means to the print buffer is executed within a line start signal. 4. The start of data transfer from the data storage means is determined based on the number of pixels to be written in the data storage means, and the second control means writes data for the number of pixels in one line. The image processing apparatus according to claim 1, wherein the data transfer is performed by repeatedly executing the data transfer. 5. The image processing apparatus according to claim 4, wherein the transfer start position of the data is changed. 6. The data bus from the data storage means is returned to the second control means on the basis of an empty flag signal for detecting a state in which there is no data in the data storage means. Image processing device. 7. The first control means and / or the second control means
2. The image processing device according to claim 1, wherein the control unit outputs the reset signal to the data storage unit to clear the data in the data storage unit.