JPH05328311A - Multiple signal demodulator - Google Patents

Abstract

PURPOSE:To prevent picture quality from being degradated by removing a DC offset due to V sag or the like. CONSTITUTION:A multiple signal multiplexed to the upper and lower pictureless part of a video signal to be substantially a vertical high frequency component is regenerated by a multiple signal regenerating circuit 27 and then passes through a vertical band pass filter 28 to remove a DC offset component to be the main cause of V sag or the like. Then an LD signal (moving picture mode compensating signal) is supplied to a line interpolating circuit 20 as a compensation signal for a main part regenerative signal through a sequential conversion circuit 29 and a delay adjusting circuit 21 and then inputted to a Vh reproducing circuit 30 for obtaining a positive picture mode compensating signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for processing a wide-wide aspect ratio signal having an aspect ratio larger than that of a current television signal, and more particularly to a multiple signal demodulation device effective for demodulating a compensation signal. It is about.

[0002]

2. Description of the Related Art As a conventional method of compressing and converting a scanning line of a television signal, "1991 HDTVWORLD CO.
In "NFERENSC PROCEEDINGS", "A NEW SYSTEM OF NTEC-CONPATIBLE WIDE ASPECT
ADVANCED TElVISION NEW NTSCMODE 1.5 Aiko, Kimata,
Other (NTV) "is shown and a wide aspect TV system called an intermediate format is disclosed. The block circuits of the encoder section and the decoder section of this prior art are shown in FIG. 3 and FIG. 4 and FIG. The line conversion characteristics are shown.

In this technique, the vertical compression ratio is 6: 5,
The conventional effective scanning lines are compressed to 480 lines, which is 400 lines. For this reason, the vertical band in the transmission system is 400/2.
Up to (cph).

On the encoder side shown in FIG. 3, 525 lines /
Pre-filtering as shown in the moving image mode of FIG. 5A and the still image mode of FIG. Apply, vertical low-pass filter 301 and subtractor 3
02. The vertical low-pass filter 301 band-limits frequencies of 400/2 (cph) or less, and the band-limited output is input to the subtractor 302 and the 5/6 times compression circuit 305. In the subtractor 302, the band-limited signal that is the output of the vertical low-pass filter 301 is subtracted from the input signal, and the vertical high-frequency component Vh that is a frequency component of 400/2 (cph) or more is output from the subtractor 302. To be done.

The output of the subtractor 302 is the vertical shift circuit 3
It is input to 03 and is shifted to the frequency band of 400/2 (cph) or less. The output of the vertical shift circuit 303 is 5
It is input to the / 6 times compression circuit 304 and compressed into video signals for 400 lines.

On the other hand, the output of the vertical low pass filter 301 is input to the 5/6 times compression circuit 305. That is 400
The signal band-limited to / 2 (cph) is compressed into 400 video signals. The output of the 5/6 times compression circuit 305 is supplied to the LD generation circuit 306 and one terminal of the switch 309. The LD generation circuit 306 is a circuit that generates a difference signal (compensation signal) from the original scanning line before the interpolation when the interpolation scanning line is created from the scanning lines of 400 video signals. This LD signal is shown as in FIG.

The Vh signal and the LD signal are mixed by the mixing circuit 3
It is input to 07 and is adaptively mixed according to the movement of the signal. The output of the mixing circuit 307 is the horizontal low-pass filter 3
At 08, the band is limited to 0.8 (MHz) and is input to the selector circuit 309. The selector circuit 309 selects the output of the 5/6 compression circuit 305 in the main part of the screen,
In the upper and lower non-image parts, the output from the horizontal low-pass filter 308 is selected and derived. The output of the selector circuit 309 is input to the interlace conversion circuit 310 and is interlaced. Then, the next left / right processing encoder 3
11 is input. The left and right processing encoder 311 cuts the signal that hits the left and right parts of the screen and processes the signal of the main part so as to conform to the current system. The cut portion is multiplexed in the vertical overscan unit by the multiplexing process.

In addition, I. The Q signal is a 5/6 times compression circuit 31.
In 2, it is compressed into 400 signals and output. 5 /
The output of the 6 × compression circuit 312 is input to the interlace conversion circuit 313, and further the left / right processing unit encoder 311.
And is converted into a 4: 3 video signal.

In the decoder shown in FIG. 4, the video signal introduced from the input terminal 400 is separated by the separation circuit 401.
It is separated into a main part and an upper and lower non-image part. The main part is input to the left / right processing decoder 402, separated into Y / C, and subjected to processing corresponding to the reverse processing of the left / right processing encoder 311 on the encoder side. As a result, the side portion is demodulated. Hereinafter, the path of the Y signal will be described. The Y signal output from the left / right processing decoder 402 is
The sequential conversion circuit 403 converts the signal into a double speed signal. The output of the sequential conversion circuit 403 is input to the delay adjustment circuit 404, the line interpolation circuit 410, and the motion detection circuit 414. The output of the delay adjustment circuit 404 is input to the frame interpolation circuit 405, subjected to interpolation processing between frames, and further input to the mixing circuit 407 via the delay adjustment circuit 406. The signal of this system is a video signal in the still image mode. The line interpolation circuit 410 creates a progressive scanning video signal by line interpolation processing. Here, for the interpolation signal,
As will be described later, the reproduced LD signals are added and compensated. The compensated video signal is input to the mixing circuit 407 via the delay adjustment circuit 412 and the field switching circuit 413. This system is a video mode video signal,
It is also the signal of the first field. Line interpolation circuit 41
The output signal of 0 is also input to the LD generation circuit 409. Here, the LD signal is generated again as in the encoder side. The generated LD signal is used by the line interpolation circuit 4
It is input to 13 to compensate for the line interpolation signal.
The line interpolation circuit 408 performs line interpolation on the output of the delay adjustment circuit 404 to create a second field video signal. The output of the line interpolation circuit 408 is input to the mixing circuit 407 via the field switching circuit 413. This system also reproduces the video signal in the moving image mode, but it is for the second field.

That is, in the above system, when transmitting the LD signal, the LD signal is transmitted every other field so that the band has a margin. Therefore, the LD of the second field is transmitted.
Regarding the signal, the video signal of the first field is used again for L
A D signal is created and used for the second field.

The motion detection circuit 414 detects a motion signal and supplies the motion detection signal to the control terminal of the mixing circuit 407 via the delay adjustment circuit 415. As a result, the mixing circuit 407 switches between the output of the switching circuit 413 and the output of the delay adjusting circuit 406 to derive the output depending on the moving image mode and the still image mode.

On the other hand, the signals of the upper and lower non-picture portions separated from the separation circuit 401 are input to the multiple signal reproduction circuit 417,
Reproduced to the original vertical high frequency component. This reproduction signal includes the Vh signal in the still image mode and the LD signal in the moving image mode. Multiple signal reproduction circuit 4
The reproduction signal reproduced in 17 is subjected to double speed conversion in the sequential conversion circuit 419, and this is input to the preceding line interpolation circuit 410 via the delay adjustment circuit 411. The output reproduction signal of the delay adjustment circuit 411 is input to the Vh reproduction circuit 420. The Vh signal extracted by the Vh reproduction circuit 420 is a vertical high frequency component of the video signal in the still image mode. This component is input to the coefficient unit 421, multiplied by the coefficient by the motion detection signal indicating the status of the still image mode, and calculated as 6 /
It is input to the quintuple conversion circuit 422 and converted into the original 480 signals, that is, expanded in the vertical direction. Then, since the frequency is shifted in the vertical direction on the encoder side, it is returned to the original frequency band by the vertical shift circuit 423.

On the other hand, the video signal of the main part from the mixing circuit 407 is also converted into a signal for 480 lines by the 6/5 times conversion circuit 416. This signal and the previous vertical shift circuit 4
The output of 23 is added by the adder 424, and the original 480 Y signals are reproduced. The still image mode has a spectrum as shown in FIG. 5D, and the moving image mode has a spectrum as shown in FIG. 5E.

As described above, in the system in which the vertical high frequency components are converted to the upper and lower non-picture parts and multiplexed and transmitted as a multiplexed signal, the vertical (V) sag generated at the time of decoding causes
There is the problem that a direct current (DC) offset is added to the multiplexed signal. Since the video signal is normally sent by AC, it is necessary to adjust the pedestal to a fixed potential before A / D conversion, and a clamp circuit is used for this purpose.

FIG. 6 shows an example of the clamp circuit. The video signal at the input terminal 60 is a low pass filter (LPF).
The band is limited at 61, and is input to the capacitor C via the buffer amplifier 62. The fixed potential E is applied to the output terminal of the capacitor C via the clamp switch 63 and the resistor R. The clamp switch 63 is turned on at the timing of the clamp pulse, charges and discharges the capacitor C, and adjusts the pedestal level (DC potential) to a fixed potential. The DC reproduced video signal is input to the A / D converter 65 via the buffer amplifier 64 and digitized.

The characteristics of such a clamp circuit are substantially determined by the time constant of the capacitor C and the resistor R. If this time constant is set to a value that allows sufficient pull-in within one line, it will be stable against fluctuations in the image. However, designing such a time constant will cause D due to noise components when S / N deteriorates.
The C value will change. Therefore, a time constant that pulls in several lines is required.

Besides the S / N deterioration, there are other factors that influence the characteristics of the clamp circuit. For example, buffer amplifier 6
If the input / output impedance characteristics of Nos. 2 and 64 are not sufficient, a leakage current will be generated and the DC value will be changed.

In consideration of such points, the time constant is generally designed to be from several tens of lines to one field. For this reason, V sag may occur depending on the input image. That is, V sag occurs in an image in which the average luminance level changes in field units or the level changes abruptly even in the field.

FIGS. 2A and 2B show the state of DC offset due to the occurrence of V sag. FIG. 11A shows the screen state of the A / D conversion output when V sag occurs and the DC amplitude in the vertical direction. The vertical amplitude is
This is an example of gradually becoming smaller. Then, even on the screen, the brightness gradually decreases from the top to the bottom. Here, since a multiplex signal is present in the upper and lower non-image parts and is reproduced and added to the main part, the image after this addition is viewed as shown in FIG. 2B. That is, the area where the multiplex signal reproduced from the upper non-picture section is added (the upper side of the screen in the example in the figure) has a bright brightness, and the area where the multiplex signal reproduced from the lower non-picture section is added (the lower part of the screen Side) is dark, and this brightness change is extreme. If a DC offset occurs in the vertical high-frequency component obtained by demodulating the multiplexed signal, D
There is a problem that the image quality is deteriorated by the C offset.

[0020]

When a DC offset occurs as described above, in a system in which multiplex signals are multiplexed and transmitted in the upper and lower non-picture areas, when the multiplex signals are demodulated, the entire screen is greatly affected. Will be given. Therefore, the present invention removes DC offset due to V sag,
An object of the present invention is to provide a multiple signal demodulation device capable of preventing deterioration of image quality.

[0021]

According to the present invention, the number of scanning lines N
A television signal transmitted by compressing a television signal of a book into M (N> M) television signals, converting a compensation signal into a multiplexed signal, and multiplexing the remaining signals into (N-M) scanning lines. To reproduce the multiplexed signal, reproduce the compensation signal from the reproduced multiplexed signal, and reproduce the original N television signals based on the compensation signal and the M television signals. The signal demodulating device comprises low frequency component removing means for removing low frequency components from the reproduced compensation signal, and means for using the output of the low frequency component removing means as a compensation signal.

[0022]

According to the above means, the compensating signal which is originally the vertical high-pass component is passed through the vertical low-pass filter to obtain V.
The DC offset can be eliminated by removing the sag component (vertical low-pass component).

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The video signal processed by the encoder described in FIG. 3 is introduced to the input terminal 10. This video signal is separated by the separation circuit 1
At 1, the upper and lower non-image parts and the main part which is the central part thereof are separated. The signal of the main part is output to Y by the left / right processing decoder 12.
/ C separation and side part demodulation are performed. The interlaced Y signal obtained by the left / right processing decoder 12 is sequentially input to the conversion circuit 13 and double-speed converted. Sequential conversion circuit 1
The output of 3 is the delay adjustment circuit 14, the line interpolation circuit 20,
It is input to the motion detection circuit 24. The output of the delay adjustment circuit 14 is input to the frame interpolation circuit 15, subjected to interpolation processing between frames, and further input to the mixing circuit 17 via the delay adjustment circuit 16. The signal of this system is a video signal in the still image mode. The line interpolation circuit 20 creates a video signal for progressive scanning by line interpolation processing.
Here, the reproduced LD signal is added to and compensated for the interpolation signal as described later. The compensated video signal is input to the mixing circuit 17 via the delay adjustment circuit 22 and the field switching circuit 23. This system is a video signal in the moving image mode and a signal in the first field. The output signal of the line interpolation circuit 20 is the LD generation circuit 1
It is also entered in 9. Here, the LD signal is generated again as in the encoder side. The generated LD signal is input to the line interpolation circuit 18 to compensate the line interpolation signal. The line interpolation circuit 18 performs line interpolation on the output of the delay adjustment circuit 14 to create a video signal of the second field. Line interpolation circuit 18
Is output to the mixing circuit 17 via the field switching circuit 23. This system also reproduces the video signal in the moving image mode, but it is for the second field.

That is, in the above system, when transmitting the LD signal, the LD signal is transmitted every other field so that the band has a margin. Therefore, the LD of the second field is transmitted.
Regarding the signal, the video signal of the first field is used again for L
A D signal is created and used for the second field.

The motion detection circuit 24 detects an image motion,
The motion detection signal is passed through the delay adjustment circuit 25 to the mixing circuit 17
Is given to the control terminal of. As a result, the mixing circuit 17 switches between the output of the switching circuit 23 and the output of the delay adjusting circuit 16 to derive the output depending on the moving image mode and the still image mode.

On the other hand, the signals of the upper and lower non-picture parts separated from the separation circuit 11 are input to the multiple signal reproduction circuit 27 and reproduced to the original vertical high frequency components. This reproduction signal includes the Vh signal in the still image mode and L in the moving image mode.
The D signal will be included. This reproduced signal is input to the vertical bandpass filter 28, and the DC offset component that is the vertical low-pass component is removed. The signal from which the DC offset component has been removed is subjected to double speed conversion by the sequential conversion circuit 29, and this is input to the preceding line interpolation circuit 20 via the delay adjustment circuit 21. The output reproduction signal of the delay adjustment circuit 21 is input to the Vh reproduction circuit 30. The Vh signal extracted by the Vh reproduction circuit 30 is a vertical high frequency component of the video signal in the still image mode. This component is input to the coefficient unit 31, multiplied by the coefficient by the motion detection signal representing the situation of the still image mode, and input to the 6/5 times conversion circuit 32 to be converted into the original 480 signals, That is, it is extended in the vertical direction. Since the frequency is vertically shifted on the encoder side, it is returned to the original frequency band by the vertical shift circuit 33.

On the other hand, the video signal of the main portion from the mixing circuit 17 is also converted into a signal for 480 lines by the 6/5 times conversion circuit 26. This signal and the output of the vertical shift circuit 33 are added by the adder 34 to reproduce the original 480 Y signals. As described above, the still image mode has the spectrum as shown in FIG. 5D, and the moving image mode has the spectrum as shown in FIG. 5E.

2 (a), 2 (b) and 2 (c) show the signal level relationship for one field in the multiplex signal reproducing circuit 27 and the vertical low pass filter 28. As shown in FIG. In the figure, the left side is the television screen viewed from the front, and the right side shows the vertical amplitude. FIG. 10A shows the output after A / D conversion, and here shows an example in which V sag occurs. Further, the multiplexed signal is compressed in the horizontal direction and the vertical high frequency components of each line are arranged side by side in the upper and lower non-image parts and added.
It is assumed that the vertical high-frequency components corresponding to the half of the screen are multiplexed in the upper non-picture part and the vertical high-frequency components corresponding to the other half are multiplexed in the lower non-picture part. FIG. 7A shows that the level is gradually decreased from the top to the bottom of the screen due to the DC offset. FIG. 6B shows a case where this multiplex signal is demodulated. As shown on the right side, it can be seen that there is a step in the DC level at the center of the screen. If the signal in which such V sag occurs is used as it is, the image quality deteriorates. However, in this embodiment, the vertical bandpass filter 28 removes the DC offset as described above and extracts only the compensation signal which is the vertical high frequency component. As a result, as shown in FIG. 7C, the level change due to the DC offset does not occur in the vertical direction, and the image quality deterioration is prevented.

[0030]

As described above, according to the present invention,
DC offset due to V sag or the like can be removed to prevent deterioration of image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram shown for explaining the influence of DC offset on image quality.

FIG. 3 is a block diagram showing an encoder of a television signal transmission and reception system according to an intermediate method.

FIG. 4 is a block diagram showing a decoder of a television signal transmission and reception system according to an intermediate scheme.

5 is an explanatory diagram of a spectrum of a transmission signal of the system shown in FIGS. 3 and 4. FIG.

FIG. 6 is a diagram showing a clamp circuit used in a conventional receiver.

[Explanation of symbols]

11 ... Separation circuit, 12 ... Left / right processing decoder, 13, 29
... Sequential conversion circuit, 14, 16, 21, 22, 25 ... Delay adjustment circuit, 15 ... Interframe interpolation circuit, 17 ... Mixing circuit, 18, 20 ... Line interpolation circuit, 19 ... LD generation circuit, 24 ... Motion detection circuit , 27 ... Multiplex signal reproduction circuit, 2
8 ... Vertical band pass filter, 30 ... Vh reproduction circuit, 3
1 ... Coefficient unit, 32 ... 6/5 times conversion circuit, 33 ... Vertical shift circuit, 34 ... Addition circuit.

Claims (1)

[Claims] 1. A television signal of N scanning lines is compressed into a television signal of M (N> M), and then a compensation signal is converted into a multiplexed signal and the remaining (N−M) scanning lines. To receive the television signal multiplexed and transmitted, reproduce the multiplexed signal, reproduce the compensation signal from the reproduced multiplexed signal, and generate the original N signals based on the compensation signal and the M television signals. In a multiple signal demodulating device for reproducing a television signal of a book, a low-frequency component removing means for removing low-frequency components from the reproduced compensation signal and a compensation signal using the output of the low-frequency component removing means A multi-signal demodulation device comprising: