JPH0532784B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a digital data arithmetic circuit that aims to shorten the arithmetic processing time of fast Fourier transform by repeatedly performing four-point Fourier transform. [Background Art and Problems thereof] Generally, when attempting to numerically process a plurality of discrete digital sample values by Fourier transform, discrete Fourier transform (DFT) is used. Fast Fourier transform (FFT) is a calculation method that calculates this discrete Fourier transform at high speed.
For example, this is achieved by repeating two-point Fourier transform (butterfly operation). This two-point Fourier transform can be executed by performing pipeline processing using one or two coefficient memories, two data memories, two multipliers, and two adders/subtractors. In this case, for example, if the number of data is 2 ^N (N: natural number), fast Fourier transform can be achieved by repeating the two-point Fourier transform 1/22 ^N ·N times; Since it takes 4 steps, the total number of steps required is N.2 ^N+1 , which increases the processing time. [Object of the Invention] Therefore, the present invention has been made in view of the above-mentioned actual situation, and when performing fast Fourier transform, the calculation processing time can be reduced without increasing the number of arithmetic units (multipliers, adders/subtractors) or memories. An object of the present invention is to provide a digital data arithmetic circuit configured to shorten the process. [Summary of the Invention] In order to achieve the above-mentioned object, a digital data calculation circuit according to the present invention includes a first digital data calculation circuit that stores digital data based on digital sample values;
a second data memory; and at least one coefficient memory storing coefficients of the digital data;
first and second multipliers that multiply the coefficient by the digital data supplied from the first and second data memories; and data sequentially supplied from the first and second multipliers. a first register that stores the output data of the first adder/subtractor and supplies it to the second adder/subtractor at a predetermined timing; a second adder/subtracter that stores the output data of the adder/subtracter and supplies it to the first adder/subtracter at a predetermined timing;
The first and second data memories are configured to store output data of the first and second adders/subtractors, respectively. [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. For example, as shown in FIG. 1, the digital data calculation circuit according to the present invention includes a data memory DMA
is connected to register R2A and register R3A, register R2A is connected to multiplier MPYA, and register R3A is connected to multiplier MPYB. Also, data memory DMB is register R.
2B and register R3B, register R2B is connected to multiplier MPYB, and register R3B is connected to multiplier MPYA. The coefficient memory CMA is connected to a multiplier MPYA, which is connected to an adder ALUA, and the adder/subtractor ALUA is connected to a data memory DMA via a register R1A. Also, coefficient memory
CMB is connected to multiplier MPYB, and this multiplier
MPYB is connected to the adder/subtractor ALUB, and the adder/subtractor
ALUB is data memory via register R1B.
Connected to DMB. And further adder/subtractor
ALUA is an adder/subtractor via register R4B.
The adder/subtractor ALUB is connected to the adder/subtractor ALUA via the register R4A. Note that the above registers R1A, R1B, R2
It is assumed that clocks A, R2B, R4A, and R4B can all be controlled by a program. This embodiment uses the digital data calculation circuit configured as described above to perform four-point Fourier transform or two-point Fourier transform.
It attempts to achieve fast Fourier transform by repeatedly performing point Fourier transform. Therefore, the four-point Fourier transform will be explained first. First, complex number Ak+iak (k=0, 1, 2,
3, i=√−1), the four-point Fourier transform of the angle θ is a complex number
=0,1,2,3,i=√-1). X _k +ix _k = 1/4 (A ₀ + ia ₀ ) + 1/4e ^-i (θ + kπ/2) (A ₁ + ia ₁
) +1/4e ^-i (2θ+2kπ/2(A ₂ +ia ₂
) +1/4e ^-i (3θ+3kπ/2) (A ₃ +ia
₃ ) Then, the data string of 2 ^N data (N: natural natural number) is rearranged appropriately (using a method that extends the so-called bit reversal order), and the data is repeatedly subjected to 4-point Fourier transform (when N is an odd number, 2 N Fast Fourier transform is achieved by performing point Fourier transform (butterfly operation) once. Here, the case where N=4, that is, the number of data is 2 ⁴ =16, will be explained. data to be processed
First, the data numbers ₀ to ₁₅ of the subscript are written in 2-bit (so-called twit) units, that is, in quaternary notation, and the digits are reversed and arranged. This results in D ₀
~D ₁₅ can be rearranged as follows. D ₀ , D ₄ , D ₈ , D ₁₆ , D ₁ , D ₅ , D ₉ , D ₁₃ , D ₂ ,
_D6 , _D10 , _D14 , _D3 , _D7 , _D11 , _D15 . Then, the four-point Fourier transform defined by the first equation is repeatedly performed on these data. In other words, as shown in Figure 2, first four pieces of data are
A four-point Fourier transform is performed on D ₀ , D ₄ , D ₈ , and D ₁₂ with θ=0. Next, four data D ₁ , D ₅ ,
Similarly, 4-point Fourier transform is performed on D ₉ and D ₁₃ with θ=0. Below, the remaining data D ₂ , D ₆ ,
Four-point Fourier transformation is similarly performed on D ₁₀ , D ₁₄ and D _× D ₇ , D ₁₁ , D ₁₅ with θ=0. The above is the 4-point Fourier transform of the first pass. Subsequently, a four-point Fourier transform is performed for the second pass and subsequent passes. That is, among the 16 newly obtained data, D′ ₀ , D′ ₁ ,
For D′ ₂ , D′ ₃ θ=0, D′ ₄ , D′ ₅ ,
For D′ ₆ , D′ ₇ θ=π/8, for D′ ₈ , D′ ₉ , D′ ₁₀ , D′ ₁₁ θ=2π/8, and D′ ₁₂ , D′ ₁₃ , D′ ₁₄ , and D′ ₁₅ are each subjected to four-point Fourier transformation with θ=3π/8. In this way, when the number of data is 16, the Fourier coefficients Y ₀ to Y ₁₅ can be obtained by performing 4-point Fourier transform eight times. When rearranging the data, if N is an odd number, the highest data number in the subscript is expressed in binary and the others in 4, and then reversed so that the lowest is in binary and the others in 4. , then perform four-point Fourier transform on these data, and finally perform two-point Fourier transform. Next, an algorithm for performing the above-mentioned four-point Fourier transform will be specifically explained. First, regarding the 4-point Fourier transform when θ=0 in the first pass,
If the input is A _k (k=0, 1, 2, 3), the output is
X _k +ix _k (k=0, 1, 2, 3; i=√-1) is expressed by the following equation based on the first equation. X ₀ =1/4A ₀ +1/4A ₁ +1/4A ₂ +1/4A ₃ x 0 = ₀ X ₁ =1/4A ₀ -1/4A ₂ x ₁ =1/4A ₁ +1/4A ₃ X ₂ =1 /4A ₀ -1/4A ₁ +1/4A ₂ -1/4A ₃ x ₂ =0 X ₃ =1/4A ₀ -1/4A ₂ x ₃ =1/4A ₁ -1/4A ₃ ...Second formula Here, algorithms for performing these calculation processes are shown in FIGS. 3 to 10. Note that the input A _k is stored in the data memory DMA, the real part X _k of the output is stored in the data memory DMA, and the imaginary part x _k
are respectively stored in the data memory DMB. In addition, in Figures 3 to 10,
Steps 1 to 8 below are shown by thick solid lines, and steps 9 to 16 are shown by thick broken lines. Step 1 First, as shown in FIG. 3, data _A1 is sent from the data memory DMA to registers R2A and R3A, respectively. Step 2 As shown in Figure 4, register R
Data A ₁ from register R3A and coefficient 1/4 from coefficient memory CMA are sent to multiplier MPYA, and data A ₁ from register R3A and coefficient 1/4 from coefficient memory CMB are sent to multiplier MPYB for storage. Ru. At the same time, data A ₃ is transferred to the data memory.
The signals are sent from the DMA to registers R2A and R3A, respectively. Step 3 As shown in Figure 5, the multiplier
Multiplication of previously stored data in MPYA A ₁ ×
1/4 is performed, which is applied to the adder/subtractor ALUA, and the multiplication of the previously stored data in the multiplier MPYB.
A ₁ ×1/4 is performed, and these are sent to and stored in the adder/subtractor ALUB, respectively. At the same time, data _A3 from register R2A and coefficient memory CMA
The coefficient 1/4 from the register _R3A and the coefficient 1/4 from the coefficient memory CMB are sent to the multiplier MPYA and stored therein, respectively. Step 4 As shown in Figure 6, the multiplier
Multiplication of previously stored data in MPYA A ₃ ×
1/4 is performed and sent to the adder/subtractor ALUA, where it is added to the previously stored data A ₁ /4 and stored. At the same time, the previously stored data is multiplied by A ₃ ×1/4 in the multiplier MPYB, and this is sent to the adder/subtractor ALUB and stored. Step 5 As shown in Figure 7, the adder/subtractor
A subtraction A ₁ /4 - A ₃ /4 of the data previously stored in ALUB is performed and at the same time as this is stored, data A ₂ is sent from the data memory DMA to register R2A. Step 6 As shown in Figure 8, register R
Data A ₂ from data memory DMA and coefficient 1/4 from coefficient memory CMA are sent to multiplier MPYA for storage, while data A ₀ is sent from data memory DMA to register R2A. Step 7 As shown in Figure 9, register R
The data A ₀ from 2A and the coefficient 1/4 from the coefficient memory CMA are sent to the multiplier MPYA and stored, while at the same time the multiplication A ₂ × 1/4 of the previously stored data in the multiplier MPYA is carried out. This is sent to the adder/subtractor ALUA and stored. Step 8 As shown in Figure 10, the multiplier
Multiplication of previously stored data in MPYA A ₀ ×
1/4 is performed and sent to the adder/subtractor ALUA and stored. At the same time, subtraction of the previously stored data A ₃ /4 - A ₁ /4 is performed in the adder/subtractor ALUB and this is stored. . Step 9 Again, as shown in the third diagram, the previously stored data is added A ₀ /4 +A ₂ /4 in the adder/subtractor ALUA and is stored. Step 10 As shown again in FIG. 4, the previously stored data is subtracted A ₀ /4 - A ₂ /4 in the adder/subtractor ALUA and sent to the register R1A. At the same time, data A ₃ /4 - _{A 4} /4 from the adder/subtractor ALUB is sent to the register R1B. Step 11 As shown in FIG. 5 again, data A ₁ /4-A ₃ /4 from the adder/subtractor ALUB is sent to the register R1B. At the same time, data A ₀ /4 - A ₂ /4 or X ₁ from register R1A is transferred to data memory DMA, data A ₃ /4 - A ₁ /4 or x ₁ from register R1B is transferred to data memory DMB, Each is memorized. Step 12 Again as shown in FIG. 6, the data A ₀ /4 - A ₂ /4 or X ₃ from the register R1A is transferred to the data memory DMA, and the data A ₁ /4 - A ₃ /4 or x from the register R1B is transferred to the data memory DMA. ₃ are respectively stored in the data memory DMB. Step 13 As shown in FIG. 7 again, the previously stored data is added (A ₀ /4 + A ₂ /4) + (A ₁ /4 + A ₃ /4) in the adder/subtractor ALUA, and this is stored. be done. Step 14 Again, as shown in Figure 8, the previously stored data is subtracted (A ₀ /4 + A ₂ /4) - (A ₁ /4 + A ₃ /4) in the adder/subtractor ALUA, and this is stored in the register. At the same time as being sent to R1A, “0” is sent to the adder/subtractor
Sent from ALUB to register R1B. Step 15 Again, as shown in FIG. 9, the data (A ₀ /4+A ₂ /4)+(A ₁ /4+A ₃ /4) from the adder/subtractor ALUA is sent to the register R1A. At the same time, data (A ₀ /4 + A ₂ /4) - (A ₁ /4 + A ₃ /4), or X ₂ , from register R1A is transferred to the data memory DMA, and "0", or x ₂ , is transferred to the data memory DMB from register R1B. are stored respectively. Step 16 As shown in FIG. 10 again, the data from register R1A is (A ₀ /4 + A ₂ /4) + (A ₁ /4
+A ₃ /4), that is, X ₀ are respectively stored in the data memory DMB. In this way, the 4-point Fourier transform of the first pass is
It looks like it takes 16 steps to do it once, but
Step 1 of the next 4-point Fourier transform can be started when the operation of step 8 above is completed, so steps 9 to 16 described above and steps 1 to 8 of the next 4-point Fourier transform can be performed simultaneously and in parallel. . Therefore, in reality, four-point Fourier transformation can be performed once in eight steps. Next, for the 4-point Fourier transform after the second pulse, the input is A _k + ia _k (k=0, 1, 2, 3; i=
√−1), the output X _k +ix _k (k=0, 1,
2, 3; i=√-1) is expressed by the following equation based on the first equation. X ₀ =A ₀ /4+A ₁ /4cosθ+a ₁ /4sinθ+A ₂ /4cos2
θ +a ₂ /4sin2θ+A ₃ /4cos3θ+a ₃ /4sin3θ x ₀ =a ₀ /4+a ₁ /4cosθ−a ₁ /4sinθ+a ₂ /4cos2
θ −A ₂ /4sin2θ+a ₃ /4cos3θ−A ₃ /4sin3θ X ₁ =A ₀ /4−A ₁ /4sinθ+a ₁ /4cosθ−A ₂ /4cos2
θ −a ₂ /4sin2θ+A ₃ /4sin3θ−a ₃ /4cos3θ x ₁ = a ₀ /4−a ₁ /4sinθ−A ₁ /4cosθ−a ₂ /4cos2
θ +A ₂ /4sin2θ+a ₃ /4sin3θ+A ₃ /4cos3θ X ₂ =A ₀ /4−A ₁ /4cosθ−a ₁ /4sinθ+A ₂ /4cos2
θ +a ₂ /4sin2θ−A ₃ /4cos3θ−a ₃ /4sin3θ x ₂ =a ₀ /4−a ₁ /4cosθ+A ₁ /4sinθ+a ₂ /4cos2
θ −A ₂ /4sin2θ−a ₃ /4cos3θ+A ₃ /4sin3θ X ₃ =A ₀ /4+A ₁ /4sinθ−a ₁ /4cosθ−A ₂ /4cos2
θ −a ₂ /4sin2θ−A ₃ /4sin3θ+a ₃ /4cos3θ x ₃ = a ₀ /4+Aa/4sinθ+A ₁ /4cosθ−a ₂ /4cos2
θ +A ₂ / _4sin2θ -a ₃ /4sin3θ-A 3 /4cos3θ...Equation 3 Here, algorithms for performing these arithmetic operations are shown in FIGS. 11 to 24. In addition,
The real part A _k of the input is transferred to the data memory DMA, and the imaginary part
It is assumed that a _k is stored in the data memory DMB, a real part X _k of the output is stored in the data memory DMA, and an imaginary part x _k of the output is stored in the data memory DMB. Further, the following steps 1 to 14 are shown in thick solid lines in FIGS. 11 to 24, and steps 15 to 18 are shown in thick broken lines in FIGS. 11 to 14, respectively. Step 1 First, as shown in Figure 11, data _A1 is sent from the data memory DMA to registers R2A and R3A, respectively, and at the same time, the data
_a1 is sent from data memory DMB to registers R2B and R3B, respectively. Step 2 As shown in FIG. 12, data _a1 from register R3B and coefficient sinθ/4 from coefficient memory CMA are input to multiplier MPYA from data A1 from register R3A and coefficient sinθ/ ₄ from coefficient memory CMB. 4 are respectively sent to the multiplier MPYB and stored therein. Step 3 As shown in FIG. 13, data _A1 from register R2A and coefficient cos θ/4 from coefficient memory CMA are sent to and stored in multiplier MPYA, while at the same time they are stored in multiplier MPYA first. The data is multiplied by a ₁ ×sin θ/4, and this is sent to the adder/subtractor ALUA and stored. On the other hand, data a ₁ from register R2B and coefficient memory CMB
At the same time, _the coefficient cosθ/4 from be remembered. Also, data _A3 is transferred from data memory DMA to register R2A.
At the same time, data _a3 is sent from data memory DMB to registers R2B and R3B, respectively. Step 4 As shown in FIG. 14, data _a3 from register R3B and coefficient cos3θ/4 from coefficient memory CMA are sent to and stored in multiplier MPYA, and at the same time they are stored in multiplier MPYA first. The data is multiplied by A ₁ ×cosθ/4, and this is sent to the adder/subtractor ALUA.
An addition A ₁ cos θ/4+a ₁ sin θ/4 is performed and stored with the data previously stored within. On the other hand, data A ₃ from register R 3A and coefficient sin3θ/4 from coefficient memory CMB are sent to and stored in multiplier MPYB, and at the same time, in this multiplier MPYB, the previously stored data is multiplied by a ₁ × cosθ/4 is performed and sent to the adder/subtractor ALUB, where it is subtracted from the previously stored data a ₁ cosθ/4−A ₁ sinθ/
4 is performed and stored. Here, adder/subtractor
The data stored in ALUA and ALUB are defined as shown below. P ₁ ＜=A ₁ cosθ/4+a ₁ sinθ/4 Q ₁ ＜=a ₁ cosθ/4−A ₁ sinθ/4 ……4th formula Step 5 As shown in Figure 15, data A ₃ from register R2A and the coefficient cos3θ/4 from the coefficient memory CMA are sent to and stored in the multiplier MPYA, and at the same time, multiplication a ₃ ×sin3θ/4 of the previously stored data is performed in this multiplier MPYA, is sent to and stored. On the other hand, data a ₃ from register R2B and coefficient memory
At the same time that the coefficient cos3θ/4 from CMB is sent to the multiplier MPYB and stored, the previously stored data is multiplied A ₃ ×sin3θ/4 in this multiplier MPYB, and this is sent to the adder/subtractor ALUB. be remembered. Further, data A ₂ is sent from the data memory DMA to registers R2A and R3A, and data a ₂ is sent from the data memory DMB to registers R2B and R3B, respectively. Step 6 As shown in FIG. 16, data _a2 from register R3B and coefficient sin2θ/4 from coefficient memory CMA are sent to and stored in adder/subtractor MPYA, and at the same time are stored in this multiplier MPYA first. The data is multiplied by A ₃ × cos3θ/4, and this is sent to the adder/subtractor ALUA.
Addition to previously stored data in ALUA
A ₃ cos3θ/4+a ₃ sinθ3/4 is performed and stored. On the other hand, data _A2 from register R3A and coefficient sin2θ/4 from coefficient memory CMB are sent to and stored in multiplier MPYB, and at the same time, the previously stored data is multiplied _a3 ×cos3θ in this multiplier MPYB. /4 is performed and sent to the adder/subtractor ALUB, where it is added with the previously stored data.
a ₃ cos3θ/4+A ₃ sin3θ/4 is performed and stored. Here, the data stored in the adder/subtractors ALUA and ALUB are defined as shown in the following equations. P ₃ <= A ₃ cos3θ/4+a ₃ sin3θ/4 Q ₃ <=a ₃ cos3θ/4+A ₃ sin3θ/4...5th equation Step 7 As shown in Figure 17, data _A2 and coefficients from register R2A At the same time that the coefficient cos2θ/4 from the memory CMA is sent to and stored in the multiplier MPYA, the previously stored data is multiplied a ₂ ×sin2θ/4 in this multiplier MPYA, and this is sent to the adder/subtractor ALUA. is sent to and stored. on the other hand,
Data a ₂ from register R2B and coefficient memory
At the same time that the coefficient cosθ/4 from CMB is sent to the multiplier MPYB and stored, the previously stored data is multiplied A ₂ ×sin2θ/4 in this multiplier MPYB, and this is sent to the adder/subtractor ALUB. be remembered. Step 8 As shown in Figure 18, the multiplier
Multiplication of previously stored data in MPYA A ₂ ×
cos2θ/4 is performed and sent to the adder/subtractor ALUA, where addition A ₂ cos2θ/4+a ₂ sin2θ/4 is performed and stored with the previously stored data. On the other hand, the data stored in the multiplier MPYB is multiplied by a ₂ ×cos2θ/4, and this is sent to the adder/subtractor ALUB, which subtracts the previously stored data by a ₂ cos2θ/4. −A ₂ sin2θ/4 is performed and stored. Further, data A ₀ is sent from the data memory DMA to the register R2A, and data a ₀ is sent from the data memory DMB to the register R2B. Here, adder/subtractor ALUA and ALUB
The data stored in is defined as follows. P ₂ <=A ₂ cos2θ/4+a ₂ sin2θ/4 Q ₂ <=a ₂ cos2θ/4−A ₂ sin2θ/4...Equation 6 Step 9 As shown in FIG. 19, data A ₀ from register R2A and the coefficient 1/4 from the coefficient memory CMA are sent to the multiplier MPYA and stored, while at the same time the data a ₀ from the register R2B and the coefficient 1/4 from the coefficient memory CMB are sent to the multiplier MPYB and stored. . Also, subtraction P ₁ −P ₃ of the previously stored data is performed in the adder/subtractor ALUA,
At the same time this is sent to register R4B, the previously stored data is subtracted Q ₁ in the adder/subtractor ALUB.
−Q ₃ is performed and this is sent to register R ₄ A. Step 10 As shown in Figure 20, the multiplier
Multiplication of previously stored data in MPYA A ₀ ×
1/4 is performed and sent to the adder/subtractor ALUA, where subtraction 1/4A ₀ -P ₂ is performed and stored with the previously stored data. On the other hand, the multiplication of the previously stored data in the multiplier MPYB is a ₀
×1/4 is performed and sent to the adder/subtractor ALUB, where subtraction 1/4a ₀ −Q ₂ is performed with the previously stored data and stored. Step 11 As shown in FIG. 21, the data Q ₁ -Q ₃ from the register R4A is sent to the adder/subtractor ALUA, where it is added to the previously stored data (A ₀ /4 - P ₂ )+(Q ₁ -Q ₃ ) is performed and sent to register R1A. At the same time, data P ₁ -P ₃ from register R4B is sent to the adder/subtractor ALUB, and subtracted from the previously stored data in this adder/subtracter ALUB (a ₀ /4 - Q ₂ ) - (P ₁ - P ₃ ) is performed and sent to register R1B. Step 12 As shown in FIG. 22, the data Q ₁ -Q ₃ from the register R4A is sent to the adder/subtractor ALUA, where it is subtracted (A ₀ /4 - P ₂ ) with the previously stored data. ) - (Q ₁ - Q ₃ ) is performed and at the same time this is sent to register R1A,
Data (A ₀ /4 - P ₂ ) + (Q ₁ - Q ₃ ) from this register R1A, that is, data X ₁ is stored in the data memory.
Stored in DMA. On the other hand, data P ₁ - _{P 3} from register R4B is sent to the adder/subtractor ALUB, and is added to the previously stored data in this adder/subtracter ALUB (a ₀ /4 - Q ₂ ) + (P ₁ - P ₃ ) is performed and sent to the register R1B, and at the same time the data (a ₀ /4-Q ₂ )-(P ₁ -P ₃ ) or x ₁ from this register R1B is stored in the data memory DMB. Step 13 As shown in FIG. 23, data A ₀ from register R2A and coefficient 1/4 from coefficient memory CMA are input to multiplier MPYA, data a ₀ from register R2B and coefficient 1/4 from coefficient memory CMB are input to multiplier MPYA. are respectively sent to and stored in the multiplier MPYB. Additionally, addition P ₁ + P ₃ of the previously stored data is performed and stored in the adder/subtractor ALUA, and addition Q ₁ + P 3 of the previously stored data is performed in the adder/subtracter ALUB.
Q ₃ is performed and stored. Furthermore, register R1A
The data from (A ₀ /4 - P ₂ ) - (Q ₁ - Q ₃ ) i.e. X ₃ is stored in the data memory DMA and is stored in the register R
The data (a ₀ /4-Q ₂ )+(P ₁ -P ₃ ) or x ₃ from 1B is stored in the data memory DMB. Step 14 As shown in Figure 24, the multiplier
Multiplication of previously stored data in MPYA A ₀ ×
1/4 is performed and sent to the adder/subtracter ALUA, where addition A ₀ /4+P ₂ is performed with the previously stored data and stored. At the same time, the multiplier MPYB multiplies the previously stored data by a ₀ × 1/4, and this is sent to the adder/subtractor ALUB, where it is added with the previously stored data. a ₀ /4+Q ₂ is performed and stored. Step 15 Again, as shown in FIG. 11, the previously stored data is subtracted (A ₀ /4 + P ₂ ) - (P ₁ + P ₃ ) in the adder/subtractor ALUA, and at the same time this is sent to the register R1A. , adder/subtractor ALUB
The data previously stored within is subtracted (a ₀ /4+Q ₂ )−(Q ₁ +Q ₃ ), and this is sent to register R1B. Step 16 Again, as shown in FIG. 12, the previously stored data (A ₀ /4 + P ₂ ) + (P ₁ + P ₃ ) is added in the adder/subtractor ALUA, and this is added to the register R.
1A, the data (A ₀ /4+P ₂ )-(P ₁ +P ₃ ), or X ₂ from this register R1A is stored in the data memory DMA. Also, the data previously stored in the adder/subtractor ALUB is added (a ₀ /4 + Q ₂ ) + (Q ₁ + Q ₃ ), and at the same time this is sent to register R1B, this register R
The data (a ₀ /4+Q ₂ )−(Q ₁ +Q ₃ ) or x ₂ from 1B is stored in the data memory DMB. Step 17 Nothing is done. Step 18 As shown in FIG. 14 again, at the same time that the data (A ₀ /4 + P ₂ ) + (P ₁ + P ₃ ) from register R1A, that is, X ₀ , is stored in the data memory DMA, the data from register R1B is (a ₀ /4 + Q ₂ ) + (Q ₁ + Q ₃ ), that is, x ₀ is the data memory DMB
is memorized. In this way, it seems to take 18 steps to perform one 4-point Fourier transform after the second pass, but once the operation of step 14 is completed,
Since step 1 of the next 4-point Fourier transform can be started, steps 15 to 18 above and the next 4 points can be started.
Steps 1 to 4 of the point Fourier transform can be performed simultaneously and in parallel. Therefore, in reality, one four-point Fourier transform can be performed in 14 steps. Note that step 17 above says "Nothing is done." This means that the data memory
This is because the input and output paths of DMA and DMB are shared, and data cannot be written and read at the same time. Further, when N is an odd number, two-point Fourier transformation is performed only once, but this can be done using an algorithm for normal butterfly calculation. In addition, in the four-point Fourier transform of this embodiment, as shown in the third equation, the real part X _k after the transform
and the imaginary part x _k each contain a common term.
Therefore, in order to utilize this common term, the digital data calculation circuit of this embodiment is provided with mutual exchange paths, that is, registers R4A and R4B between the real number calculation section and the imaginary number calculation section. That is, by performing the operation shown in FIG. 19, the calculation processing time can be significantly shortened. In other words, when using the conventional method of repeating two-point Fourier transform for ^2N data, the number of steps required was N・2N ⁺¹ , but using a digital data calculation circuit like this example, If the four-point Fourier transform is repeated, the number of steps required will be as follows. When N is an even number, 1st pass...8 x 2 ^N /4 = 2 x 2 ^N 2nd to N/2 passes...(N/2-1) x 14 x 2 ^N /4 = (7N-14) 2 ^{N -2} total (7N-6) 2 ^N-2 steps When N is an odd number 1st pass...8 x 2 ^N /4 = 2 x 2 ^N 2nd to N-1/2 passes... (N-1/2- 1) × 14 × 2 ^N / 4 = (7N-21) 2 ^N-2 Nth + 1/2 pass (2-point Fourier transform)...4 × 2 ^N / 2 = 2 ^{N + 1} total (7N-5) 2 ^{N -2} steps Here, for example, N=4, 5, 6, 7, 8,
As 9 and 10, the conventional two-point Fourier transform circuit and 4
Table 1 shows the specific number of steps and their ratios in the digital data arithmetic circuit of this embodiment that performs point Fourier transform.

【table】

〔Effect of the invention〕

As is clear from the description of the embodiments described above, according to the present invention, when performing fast Fourier transform, the calculation processing time can be shortened without increasing the number of calculation units (multipliers, adders/subtractors) or memories. can fully achieve the intended purpose.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital data calculation circuit according to the present invention. Figure 2 is
FIG. 2 is a schematic diagram showing an example of four-point Fourier transform for ^2N data. Figures 3 to 24 are from the above 2nd figure.
The algorithm for actually performing the four-point Fourier transform shown in the figure is shown, and Figures 3 to 10
The figure shows the case of the first pass, and FIGS. 11 to 24 are block diagrams showing the cases of the second pass and subsequent passes, respectively. CMA, CMB...Coefficient memory, MPYA, MPYB
…multiplier, ALUA, ALUB…addition/subtractor, DMA,
DMB...Data memory, R4A, R4B...Register.

Claims (1)

[Scope of Claims] 1. First and second data memories for storing digital data based on digital sample values; at least one coefficient memory for storing coefficients of the digital data; and at least one coefficient memory for storing coefficients of the digital data; first and second multipliers that respectively multiply the digital data supplied from the second data memory; and first and second multipliers that add and subtract the data sequentially supplied from the first and second multipliers, respectively. an adder/subtractor; a first register that stores output data of the first adder/subtractor and supplies it to the second adder/subtracter at a predetermined timing; and a first register that stores output data of the second adder/subtractor; a second register that supplies data to the first adder/subtracter at a predetermined timing, and the first and second data memories are configured to store output data of the first and second adder/subtracters, respectively. A digital data calculation circuit characterized by: