JPH05327047A - Josephson element and manufacture thereof - Google Patents

Josephson element and manufacture thereof

Info

Publication number
JPH05327047A
JPH05327047A JP4123769A JP12376992A JPH05327047A JP H05327047 A JPH05327047 A JP H05327047A JP 4123769 A JP4123769 A JP 4123769A JP 12376992 A JP12376992 A JP 12376992A JP H05327047 A JPH05327047 A JP H05327047A
Authority
JP
Japan
Prior art keywords
layer
substrate
superconductor
superconductor layer
josephson
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4123769A
Other languages
Japanese (ja)
Inventor
Shinichi Shikada
真一 鹿田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP4123769A priority Critical patent/JPH05327047A/en
Publication of JPH05327047A publication Critical patent/JPH05327047A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a Josephson element which can be highly integrated by obtaining a film of high quality even if a crystal growing direction of a superconducting material and a direction of excellent coherence are difference and realizing a planar structure by providing an intermediate layer as a sidewall. CONSTITUTION:A first superconductor layer 2 is formed on a first surface region of a substrate 1. An intermediate layer 3 is formed on a second substrate surface region adjacent to a first substrate surface region, in contact with the layer 2, and brought into contact with a second superconductor layer 4 at a side parallel to its contact surface through a thickness of the layer 3. A second superconductor layer 4 is formed on a third substrate surface region opposed to the first substrate surface region, and a first electrode 5, a second electrode 6 are connected to the layers 2, 4. Thus, a Josephson junction is realized in a horizontal direction with excellent coherence, and a planar structure in which the layers 2, 3, 4 are sequentially aligned in a horizontal direction is realized on the surface of the substrate 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高速デジタル論理素子で
あるジョセフソン素子とこのジョセフソン素子の製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Josephson device which is a high speed digital logic device and a method of manufacturing the Josephson device.

【0002】[0002]

【従来の技術】デジタル論理素子としてSiやGaAs
などの半導体を用いた集積回路が広く普及し、使用され
ている。高速演算に対する需要の高まりに応じて、これ
らの半導体素子とは全く異なる原理によって動作し、飛
躍的にスイッチング時間の短いジョセフソン素子が提案
・試作されてきた。Pb合金系材料を用いて始まったジ
ョセフソン素子の集積は、その材料を、より安定な超電
導特性を示すNb系化合物材料に変更しつつ発展してき
た。近年、既知の超電導物質に比較して高温で超電導状
態となるBi系、Y系酸化物の発見に伴い、Nb系化合
物とともにこれらの超電導材料を使用したジョセフソン
素子、および半導体技術との融合による集積回路化が注
目されている。
2. Description of the Related Art Si and GaAs are used as digital logic elements.
An integrated circuit using a semiconductor such as is widely used and used. In response to the increasing demand for high-speed computation, Josephson devices that operate on a completely different principle from these semiconductor devices and have a dramatically short switching time have been proposed and prototyped. The integration of Josephson devices, which started using Pb alloy-based materials, has evolved while changing the materials to Nb-based compound materials that exhibit more stable superconducting properties. In recent years, with the discovery of Bi-based and Y-based oxides that are in a superconducting state at a higher temperature than known superconducting materials, Josephson devices using these superconducting materials with Nb-based compounds, and fusion with semiconductor technology Attention has been paid to integrated circuits.

【0003】従来、超電導体層(以後、第1超電導体層
と称する)/非超電導体層(以後、中間層と称する)/
超電導体層(以後、第2超電導体層と称する)のサンド
イッチ型構成のジョセフソン素子製造をするにあたり、
基板の垂直方向に、超電導体薄膜、非超電導体薄膜、超
電導体薄膜の順で積み重ねた多層膜を使用する方法が知
られている。例えば、Nb系として、H.Nakagawa et a
l.,1990 Applied Superconductivity Conf.,EPR-1.01
、Y系として、C.T.Rogers et al.,Appl.Phys.Lett.5
5,2032(1989)、およびBi系として、K.Mizuno et al.,
Appl.Phys.Lett.56,1469(1990)、などが報告されている
が、いずれも積層多層膜構造を有している。
Conventionally, a superconductor layer (hereinafter referred to as a first superconductor layer) / a non-superconductor layer (hereinafter referred to as an intermediate layer) /
In manufacturing a Josephson device having a sandwich type structure of a superconductor layer (hereinafter, referred to as a second superconductor layer),
There is known a method of using a multilayer film in which a superconductor thin film, a non-superconductor thin film, and a superconductor thin film are stacked in this order in the vertical direction of a substrate. For example, as an Nb system, H. Nakagawa et a
l., 1990 Applied Superconductivity Conf., EPR-1.01
, Y system, CTRogers et al., Appl.Phys.Lett.5
5,2032 (1989), and as the Bi system, K. Mizuno et al.,
Appl. Phys. Lett. 56, 1469 (1990), etc. have been reported, but all have a laminated multilayer film structure.

【0004】図3はかかるジョセフソン素子の構成図で
ある。図示のとうり、基板1表面と平行に第1超電導体
層2、中間層3、第2超電導体層4が順次積み重なり、
ジョセフソン接合を実現している。第1電極5および第
2電極6は、それぞれ第1超電導体層2、第2超電導体
層4に接続され、二つの超電導体層間の電圧印加および
電流供給に使用される。
FIG. 3 is a block diagram of such a Josephson device. As shown in the figure, the first superconductor layer 2, the intermediate layer 3, and the second superconductor layer 4 are sequentially stacked in parallel with the surface of the substrate 1,
It realizes Josephson junction. The first electrode 5 and the second electrode 6 are connected to the first superconductor layer 2 and the second superconductor layer 4, respectively, and are used for voltage application and current supply between the two superconductor layers.

【0005】このジョセフソン素子は以上のように構成
されるので、エッチング前の多層膜を形成するにあたっ
て、各層の材料物質の結晶成長方向に接合面を設けざる
をえないとともに、ヘテロエピタキシ(ある物質の結晶
材料の上に異なる物質の結晶を成長させる)を、第1超
電導体層2上の非超電導体材料からなる中間層3形成、
および中間層3上の第2超電導体層4形成時に行う必要
がある。
Since this Josephson element is constructed as described above, when forming a multilayer film before etching, it is unavoidable to provide a junction surface in the crystal growth direction of the material of each layer, and heteroepitaxy (existence). Growing a crystal of a different substance on the crystal material of the substance) to form an intermediate layer 3 made of a non-superconductor material on the first superconductor layer 2.
It is necessary to perform it when forming the second superconductor layer 4 on the intermediate layer 3.

【0006】[0006]

【発明が解決しようとする課題】使用する超電導体材料
が、その結晶として、コヒーレンス性が良好な方向と良
質膜の得られる成長方向が異なる場合がある。こうした
場合、従来の製造方法では、前記のように、超電導材料
の結晶成長方向と接合方向が一致するため、良質のジョ
セフソン素子が得にくかった。
As the crystal of the superconductor material used, the direction in which the coherence property is good and the growth direction in which the good quality film is obtained may be different. In such a case, in the conventional manufacturing method, since the crystal growth direction and the junction direction of the superconducting material coincide with each other as described above, it is difficult to obtain a good quality Josephson element.

【0007】ジョセフソン接合をヘテロエピタキシにて
実施するにあたって、二つの材料の結晶相互間で、格子
不整が小さい、密着性、カバレッジが良い必要があるた
め、超電導体層材料と中間層材料では、その結晶構造が
類似している必要があった。例えば、超電導層の材料と
して、Bi系またはY系酸化物を選択すると、その結晶
構造がペロブスカイト構造であることおよび上記の必要
条件から、中間層材料としてY系ではPrBa2 Cu3
y など、Bi系ではBi2 Sr2 CuOx などの格子
定数のミスマッチの比較的小さなペロブスカイト構造を
持つものを選ばなければならなかった。
When the Josephson junction is implemented by heteroepitaxy, it is necessary that the lattice mismatch between the crystals of the two materials is small, the adhesion and the coverage are good. Therefore, in the superconductor layer material and the intermediate layer material, Its crystal structure had to be similar. For example, as the material of the superconducting layer, selecting the Bi based or Y-based oxide, from its crystal structure is a perovskite structure and the requirements, in the Y-based as the intermediate layer material PrBa 2 Cu 3
In the case of Bi system such as O y , one having a perovskite structure with a relatively small lattice constant mismatch such as Bi 2 Sr 2 CuO x had to be selected.

【0008】また、従来のジョセフソン素子は、前記の
ように基板と垂直方向に、第1超電導体層2、中間層
3、第2超電導体層4を順次積み重ねるので、プレーナ
構造とはなりえず、高集積化が困難であった。
Further, the conventional Josephson element has a planar structure because the first superconductor layer 2, the intermediate layer 3, and the second superconductor layer 4 are sequentially stacked in the direction perpendicular to the substrate as described above. It was difficult to achieve high integration.

【0009】本発明は、超電導材料の結晶構造におい
て、コヒーレンス性のよい方向と高品質膜を得られる結
晶成長方向が一致しない場合にも、良質の素子を得られ
るよう構成されるジョセフソン素子およびその製造方法
を提供するとともに、上記のような超電導材料の結晶構
造を基準として、ペロブスカイト構造超電導材料にはペ
ロブスカイト中間層材料といった制約条件を取り除き、
中間層材料の選択範囲を広げることを目的とする。
According to the present invention, a Josephson element and a Josephson element configured so that a high quality element can be obtained even in the crystal structure of a superconducting material when the direction of good coherence does not coincide with the direction of crystal growth capable of obtaining a high quality film. Along with providing a manufacturing method thereof, based on the crystal structure of the superconducting material as described above, a constraint condition such as a perovskite intermediate layer material is removed in the perovskite structure superconducting material,
The purpose is to broaden the selection range of intermediate layer materials.

【0010】また、本発明は、プレーナ構造を実現する
ことにより、高集積化可能なジョセフソン素子および製
造方法を提供することを目的とする。
It is another object of the present invention to provide a Josephson device and a manufacturing method which can be highly integrated by realizing a planar structure.

【0011】[0011]

【課題を解決するための手段】本発明のジョセフソン素
子は、中間層を半導体素子で行われている側壁形成法で
得られる側壁として設けることにより、超電導材料の結
晶成長方向と交差する方向で超電導体層と非超電導材料
からなる中間層との接合を可能とするとともに、プレー
ナ構造を実現することを特徴とする。
In the Josephson element of the present invention, the intermediate layer is provided as a side wall obtained by the side wall forming method which is carried out in the semiconductor element, so that the crystal growth direction of the superconducting material is crossed. The feature is that the superconductor layer and the intermediate layer made of a non-superconducting material can be joined together and a planar structure is realized.

【0012】また、本発明のジョセフソン素子の製造方
法は、基板上に第1の超電導体層、および第1の超電導
体層上にこの層と接続する電極を形成する第1の工程
と、第1の超電導体層の側壁として反応性イオンエッチ
ング法を用いて、中間層を形成する第2の工程と、中間
層をはさんで第1の超電導体層の反対側に、第2の超電
導体層を結晶の選択成長法を使用して形成する第3の工
程と、第2の超電導体層に接続する電極を形成する第4
の工程とを有することを特徴とする。
The method of manufacturing the Josephson element of the present invention further comprises a first step of forming a first superconductor layer on the substrate and an electrode connected to this layer on the first superconductor layer, A second step of forming an intermediate layer by using a reactive ion etching method as a side wall of the first superconductor layer, and a second superconducting layer on the opposite side of the first superconductor layer with the intermediate layer interposed therebetween. Third step of forming a body layer using a selective crystal growth method and fourth step of forming an electrode connected to the second superconductor layer
And the steps of.

【0013】[0013]

【作用】本発明のジョセフソン素子によれば、ジョセフ
ソン接合方向と超電導体層薄膜形成時の結晶成長方向を
交差させることができるので、超電導材料で良質膜の得
られる結晶成長方向とコヒーレンス性の良好な方向が異
なる場合においても、良質膜の得られる結晶方向への成
長で得た超電導体層でコヒーレンス性の良好な方向で接
合が可能であるとともに、プレーナ型構造を実現するの
で高集積化可能である。
According to the Josephson device of the present invention, the Josephson junction direction and the crystal growth direction at the time of forming the superconducting layer thin film can be made to intersect with each other. Even if the good direction is different, the superconductor layer obtained by growing the good quality film in the crystal direction can be bonded in the direction with good coherence and realizes a planar structure, thus achieving high integration. Can be converted.

【0014】本発明のジョセフソン素子の製造方法によ
れば、中間層を側壁形成によって設けるので、従来必要
であった超電導層上の中間層形成および中間層上の超電
導層形成のためのヘテロエキタピシを必要としなくな
る。従って、中間層材料の選択にあって、結晶構造が超
電導体材料と類似の結晶構造を持たねばならないという
制約を除去することが可能である。
According to the method for manufacturing the Josephson device of the present invention, since the intermediate layer is provided by forming the side wall, the heteroexamination for forming the intermediate layer on the superconducting layer and the superconducting layer on the intermediate layer, which have been conventionally required, can be obtained. No longer need it. Therefore, it is possible to remove the constraint that the crystal structure must have a crystal structure similar to that of the superconductor material in selecting the intermediate layer material.

【0015】また、本発明のジョセフソン素子の製造方
法によれば、基板表面と水平方向に、第1の超電導体
層、中間層、第2の超電導体層が順次基板上に形成され
るので、プレーナ構造を有し、かつ、良好に動作する上
記ジョセフソン素子を製作することができる。
Further, according to the method for manufacturing the Josephson device of the present invention, the first superconductor layer, the intermediate layer and the second superconductor layer are sequentially formed on the substrate in the horizontal direction with respect to the substrate surface. It is possible to manufacture the above Josephson device having a planar structure and operating well.

【0016】[0016]

【実施例】本発明の実施例を図面を参照して説明する。
図1には、第1実施例のジョセフソン素子の構造を示し
ている。このジョセフソン素子では、材料として、基板
1にはNdGaO3 (110)を、第1超電導体層2お
よび第2超電導体層4にはYBa2 Cu3 7-x を、中
間層3はSiO2 を、第1電極5および第2電極6には
Alを使用している。第1超電導体層2および第2超電
導体層4の材料であるYBa2 Cu3 7-x は、その結
晶構造がペロブスカイト構造を基本とし、a軸方向にコ
ヒーレンス性が良好である一方、a軸と直交するc軸方
向への結晶成長で高品質の膜を得やすい性質がある。
Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the structure of the Josephson device of the first embodiment. In this Josephson element, the substrate 1 is NdGaO 3 (110), the first superconducting layer 2 and the second superconducting layer 4 are YBa 2 Cu 3 O 7-x , and the intermediate layer 3 is SiO 2. 2 and Al is used for the first electrode 5 and the second electrode 6. YBa 2 Cu 3 O 7-x , which is the material of the first superconductor layer 2 and the second superconductor layer 4, has a crystal structure based on a perovskite structure and has good coherence in the a-axis direction. There is a property that a high quality film can be easily obtained by crystal growth in the c-axis direction orthogonal to the axis.

【0017】このジョセフソン素子の構成要素の幾何学
的な配置は以下のとうりである。第1超電導体層2は、
第1の基板表面領域上に形成され、その結晶構造とし
て、基板1表面の垂直方向にc軸方向、水平方向にa軸
方向を有し、そのa軸方向と直交する側面を有する。中
間層3は、第1の基板表面領域に隣接する第2の基板表
面領域上に形成され、第1超電導体層2のa軸方向と直
交する一つの側面と接し、中間層3の厚みを隔て、その
接触面と平行な側面で第2超電導体層4と接する。第2
超電導体層4は、第2の基板表面領域と接するともに、
この領域を境界として第1の基板表面領域と相対する第
3の基板表面領域上に形成され、その結晶構造として、
基板1表面の垂直方向にc軸方向、水平方向に第1超電
導体層2のa軸方向と平行のa軸方向を有する。第1電
極5、第2電極6は、それぞれ第1超電導体層2、第2
超電導体層4に接続される。
The geometrical arrangement of the constituent elements of this Josephson element is as follows. The first superconductor layer 2 is
The crystal structure is formed on the first substrate surface region and has a c-axis direction in the vertical direction of the substrate 1 surface, an a-axis direction in the horizontal direction, and a side surface orthogonal to the a-axis direction. The intermediate layer 3 is formed on the second substrate surface region adjacent to the first substrate surface region, contacts one side surface of the first superconductor layer 2 orthogonal to the a-axis direction, and reduces the thickness of the intermediate layer 3 The side surface parallel to the contact surface is in contact with the second superconductor layer 4. Second
The superconductor layer 4 is in contact with the second substrate surface region,
It is formed on the third substrate surface region opposite to the first substrate surface region with this region as a boundary, and its crystal structure is:
The c-axis direction is vertical to the surface of the substrate 1 and the a-axis direction parallel to the a-axis direction of the first superconductor layer 2 is horizontal. The first electrode 5 and the second electrode 6 are respectively the first superconductor layer 2 and the second superconductor layer 2.
It is connected to the superconductor layer 4.

【0018】上記のような構造でジョセフソン素子を構
成するので、第1超電導体層2、第2超電導体層4の材
料結晶として、良質膜の得られるc軸方向を結晶成長さ
せる基板1表面の垂直方向とするとともに、コヒーレン
ス性の良好なa軸方向でジョセフソン接合することを実
現している。また、基板1表面上、その水平方向に、第
1超電導体層2、中間層3、第2超電導体層4の順に並
ぶ構造として、プレーナ構造を実現している。
Since the Josephson element is constructed with the above structure, as the material crystals of the first superconductor layer 2 and the second superconductor layer 4, the surface of the substrate 1 on which crystal growth is carried out in the c-axis direction in which a good quality film can be obtained. And the Josephson junction is realized in the a-axis direction with good coherence. Also, a planar structure is realized as a structure in which the first superconductor layer 2, the intermediate layer 3, and the second superconductor layer 4 are arranged in this order on the surface of the substrate 1 in the horizontal direction.

【0019】このジョセフソン素子は、図2に示す工程
で製作される。
This Josephson device is manufactured by the process shown in FIG.

【0020】まず、基板1上にスパッタリング法を用い
て第1超電導体層2をその材料の結晶構造であるペロブ
スカイト系構造のc軸方向に結晶成長させることにより
形成する。この後、第1超電導体層2に接続する第1電
極5を形成する(図2(a))。
First, the first superconductor layer 2 is formed on the substrate 1 by the crystal growth in the c-axis direction of the perovskite structure, which is the crystal structure of the material, by the sputtering method. After that, the first electrode 5 connected to the first superconductor layer 2 is formed (FIG. 2A).

【0021】つぎに、第1超電導体層2として残す部分
をマスク後、エッチングを施し基板1表面を一部露出さ
せる(図2(b))。次いで、減圧CVD法にて中間層
3を図2(b)の工程段階での露出表面全体に形成する
(図2(c))。この後、反応性イオンエッチング(R
IE)による方向性を有したエッチングを施し、第1超
電導体層2の側壁に中間層3を5nm幅で設ける(図2
(d))。このときのRIEでは、反応ガスにはCF4
を用いる。
Next, after masking the portion to be left as the first superconductor layer 2, etching is performed to partially expose the surface of the substrate 1 (FIG. 2B). Next, the intermediate layer 3 is formed on the entire exposed surface in the process step of FIG. 2B by the low pressure CVD method (FIG. 2C). After this, reactive ion etching (R
Directional etching by IE) is performed to provide the intermediate layer 3 with a width of 5 nm on the side wall of the first superconductor layer 2 (FIG. 2).
(D)). In the RIE at this time, CF 4 is used as the reaction gas.
To use.

【0022】引き続き、図2(d)の工程段階で露出し
ている基板1の表面に、第2超電導体層4を結晶の選択
成長によって形成する(図2(e))。この後、第2超
電導体層4と接続する第2電極6を形成する。
Subsequently, the second superconductor layer 4 is formed on the surface of the substrate 1 exposed in the process step of FIG. 2D by selective crystal growth (FIG. 2E). After this, the second electrode 6 connected to the second superconductor layer 4 is formed.

【0023】以上の工程でヘテロエキタピシを用いずに
ジョセフソン素子を作成、12GHzのマイクロ波照射
にてシャピロステップを観測し、良好なジョセフソン素
子を得られることを確認できる。
In the above steps, a Josephson device was produced without using hetero-excitation, and a Shapiro step was observed by microwave irradiation of 12 GHz, and it was confirmed that a good Josephson device could be obtained.

【0024】次いで、第2実施例に関して説明する。第
2実施例のジョセフソン素子の構成図は第1実施例と同
一であり、使用する材料のみが異なる。このジョセフソ
ン素子では、材料として、基板1にMgO(100)
を、第1超電導体層2および第2超電導体層4にBi2
Sr2 Ca2 Cu3 x を、中間層3にBi2 Sr2
uOx を、第1電極5および第2電極6にAgまたはA
uを使用している。第1実施例と同様に、第1超電導体
層2および第2超電導体層4の材料であるBi2Sr2
Ca2 Cu3 x は、その結晶構造がペロブスカイト構
造を基本とし、a軸方向にコヒーレンス性が良好である
一方、a軸と直交するc軸方向への結晶成長で高品質の
膜を得やすい性質がある。
Next, the second embodiment will be described. The configuration diagram of the Josephson element of the second embodiment is the same as that of the first embodiment, and only the materials used are different. In this Josephson element, as a material, MgO (100) was used for the substrate 1.
On the first superconducting layer 2 and the second superconducting layer 4 with Bi 2
Sr 2 Ca 2 Cu 3 O x was added to the intermediate layer 3 as Bi 2 Sr 2 C.
uO x is applied to the first electrode 5 and the second electrode 6 by Ag or A
u are used. As in the first embodiment, the material of the first superconductor layer 2 and the second superconductor layer 4 is Bi 2 Sr 2
The crystal structure of Ca 2 Cu 3 O x is basically a perovskite structure and has good coherence in the a-axis direction, while it is easy to obtain a high-quality film by crystal growth in the c-axis direction orthogonal to the a-axis direction. There is a property.

【0025】以上の材料を用いて、第1実施例と同様に
ジョセフソン素子を構成するので、第1超電導体層2、
第2超電導体層4の材料結晶として、良質膜の得られる
c軸方向を結晶成長させる基板1表面の垂直方向とする
とともに、コヒーレンス性の良好なa軸方向でジョセフ
ソン接合することを実現している。また、基板1表面
上、その水平方向に第1超電導体層2、中間層3、第2
超電導体層4の順に並ぶ構造として、プレーナ構造を実
現している。
Since the Josephson device is formed by using the above materials in the same manner as in the first embodiment, the first superconductor layer 2,
As the material crystal of the second superconductor layer 4, the c-axis direction in which a good quality film is obtained is set to the direction perpendicular to the surface of the substrate 1 for crystal growth, and the Josephson junction is realized in the a-axis direction with good coherence. ing. In addition, on the surface of the substrate 1, the first superconductor layer 2, the intermediate layer 3,
A planar structure is realized as a structure in which the superconductor layers 4 are arranged in order.

【0026】このジョセフソン素子の製造工程は、図2
で示される第1実施例の製造工程と同様であり、中間層
3の形成にあたって使用するRIEの反応ガスの組成が
BCl3 +Cl2 であることと、中間層3の形成幅が6
0nmであることが異なる。
The manufacturing process of this Josephson device is shown in FIG.
The manufacturing process is the same as that of the first embodiment shown in FIG. 3, the composition of the reaction gas of RIE used for forming the intermediate layer 3 is BCl 3 + Cl 2 , and the forming width of the intermediate layer 3 is 6
The difference is 0 nm.

【0027】以上の工程でヘテロエキタピシを用いずに
ジョセフソン素子を作成、18GHzのマイクロ波照射
にてシャピロステップを観測し、良好なジョセフソン素
子を得られることを確認できる。
In the above steps, a Josephson device was prepared without using hetero-excitation, and a Shapiro step was observed by microwave irradiation of 18 GHz, and it was confirmed that a good Josephson device could be obtained.

【0028】本発明は上記実施例に限定されるものでは
なく、様々な変形が可能である。
The present invention is not limited to the above embodiment, but various modifications can be made.

【0029】例えば、第1実施例の中間層材料として
は、SiO2 以外にSiN、SiOxy 、MgO、N
dGeO3 などを使用してもよい。また、第1実施例の
中間層形成にあたっては、減圧CVD法に限らず、中間
層材料に応じて、常圧CVD法、プラズマCVD法、ス
パッタリング法、ECR−CVD法などを用いてもよ
い。
For example, as the intermediate layer material of the first embodiment, in addition to SiO 2 , SiN, SiO x N y , MgO, N
dGeO 3, or the like may be used. Further, in forming the intermediate layer of the first embodiment, not only the low pressure CVD method but also the atmospheric pressure CVD method, the plasma CVD method, the sputtering method, the ECR-CVD method or the like may be used depending on the intermediate layer material.

【0030】[0030]

【発明の効果】以上、詳細に説明したとうり本発明によ
れば、超電導体層として高品質膜の得られる結晶成長方
向と結晶としてコヒーレンス性の良好な方向が異なる場
合においても、高品質膜を得つつコヒーレンス性の良好
な方向で接合を有する、安定した動作を期待でき、かつ
製造上も歩留まりの少ない工程で、高集積化可能なプレ
ーナ型ジョセフソン素子を製造できる。
As described above in detail, according to the present invention, even when the crystal growth direction in which a high quality film is obtained as the superconductor layer and the direction in which the coherence is good as the crystal are different, the high quality film is obtained. It is possible to manufacture a planar type Josephson element which can be highly integrated in a process which has a junction in a direction of good coherence while expecting stable operation, can expect stable operation, and has a small yield in manufacturing.

【図面の簡単な説明】[Brief description of drawings]

【図1】第1実施例のジョセフソン素子の構成図。FIG. 1 is a configuration diagram of a Josephson device according to a first embodiment.

【図2】図1のジョセフソン素子の製造工程図。2A to 2C are manufacturing process diagrams of the Josephson device of FIG.

【図3】従来のジョセフソン素子の構成図FIG. 3 is a block diagram of a conventional Josephson device.

【符号の説明】[Explanation of symbols]

1…基板,2…第1超電導体層,3…中間層,4…第2
超電導体層,5…第1電極,6…第2電極。
1 ... Substrate, 2 ... First superconductor layer, 3 ... Intermediate layer, 4 ... Second
Superconductor layer, 5 ... First electrode, 6 ... Second electrode.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板表面の第1の領域に形成された超電
導材料からなる第1の層と、 この第1の領域と隣接する前記基板表面の第2の領域に
形成された非超電導材料からなる第2の層と、 この第2の領域と隣接し、第2の領域を境界として前記
第1の領域と相対する前記基板表面の第3の領域に形成
された超電導材料からなる第3の層とを備え、 前記第1の層と前記第2の層を接合し、かつ前記第2の
層と前記第3の層を接合した構造を持つことを特徴とす
る、プレーナ型ジョセフソン素子。
1. A first layer of a superconducting material formed on a first region of a substrate surface, and a non-superconducting material formed on a second region of the substrate surface adjacent to the first region. And a third layer made of a superconducting material formed in a third region of the substrate surface which is adjacent to the second region and faces the first region with the second region as a boundary. A planar Josephson device comprising: a layer; and a structure in which the first layer and the second layer are joined and the second layer and the third layer are joined.
【請求項2】 基板表面全体に超電導体層を成長させる
第1の工程と、 前記基板表面の第1の領域以外の前記超電導体層を除去
し、第1の層を形成する第2の工程と、 露出表面全体に非超電導材料を堆積し非超電導体層を形
成する第3の工程と、 前記第1の層の側面以外の前記非超電導体層を反応性イ
オンエッチング法を用いて除去し、前記第1の層の側壁
として前記基板表面の第2の領域に第2の層を形成する
第4の工程と、 前記基板表面を境界として前記第1の領域と相対する第
3の領域に超電導材料の結晶を選択成長させ、第3の層
を形成する第5の工程とを有することを特徴とするジョ
セフソン素子の製造方法。
2. A first step of growing a superconductor layer on the entire surface of the substrate, and a second step of removing the superconductor layer other than the first region of the surface of the substrate to form a first layer. A third step of depositing a non-superconducting material on the entire exposed surface to form a non-superconducting layer, and removing the non-superconducting layer other than the side surface of the first layer using a reactive ion etching method. A fourth step of forming a second layer on a second region of the substrate surface as a sidewall of the first layer, and a third region opposite to the first region with the substrate surface as a boundary. A fifth step of selectively growing a crystal of a superconducting material to form a third layer, the method of manufacturing a Josephson device.
JP4123769A 1992-05-15 1992-05-15 Josephson element and manufacture thereof Pending JPH05327047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4123769A JPH05327047A (en) 1992-05-15 1992-05-15 Josephson element and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4123769A JPH05327047A (en) 1992-05-15 1992-05-15 Josephson element and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05327047A true JPH05327047A (en) 1993-12-10

Family

ID=14868830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4123769A Pending JPH05327047A (en) 1992-05-15 1992-05-15 Josephson element and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05327047A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010192913A (en) * 2010-03-31 2010-09-02 Ntt Docomo Inc Superconducting circuit and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010192913A (en) * 2010-03-31 2010-09-02 Ntt Docomo Inc Superconducting circuit and method of manufacturing the same

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