JPH05326891A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable data to be written in a non-volatile semiconductor memory independent of the influence of a turn-ON phenomenon of an unwritten cell by a method wherein a transistor is provided between the source region of a cell transistor in a flash EEPROM and a ground potential terminal. CONSTITUTION:Memory transistors Qi,j are provided to intersections of word lines Xi and digit lines Yj respectively to constitute a memory cell matrix, where the N<+>-type source regions of the memory transistors are connected in common along a word line direction to a ground potential terminal through the intermediary of the first transistor Pi, and the gate electrode of the first transistor Pi is connected to a word line Xi. A writing high voltage is applied to the digit line Yj and the word line Xi at writing. At this point, even if the other memory cells connected to the same digit, line are lessened enough in threshold voltage to produce a turn-ON phenomenon, a write-operation can be carried out, because transistors which shut off a current path are present.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to an electrically writable / erasable floating gate type semiconductor memory device.

[0002]

2. Description of the Related Art As a non-volatile semiconductor memory device which is electrically writable and erasable, a Fowler-Nordheim (Fowler-Nordhei) has been used for writing and erasing.
The method using the m) type tunnel current was general. However, in this method, since the memory transistor after writing is in the depletion state due to its operating characteristics, it is necessary to provide a selection transistor for each bit in order to enable selective reading. Therefore, a 1-bit memory cell is composed of a selection transistor and a memory transistor, which increases the cell area and hinders the increase in capacity.

As one countermeasure against this, a flash EEPROM has recently been proposed. This cannot be rewritten in byte units like the conventional EEPROM,
Although it is a batch erasing type, it is attracting attention as a method for connecting a large capacity cell such as an ultraviolet erasing type EPROM and "electrical erasing".

FIG. 4 shows such a flash EEPROM.
FIG. 3 is a cross-sectional structure diagram of a memory transistor called a self-aligned gate type which can minimize the cell area among the above. In this example, N ⁺ is formed on the surface of the P-type silicon substrate 1.
A type drain region 7 and an N ⁺ type source region 6 are provided, and the first type drain region 7 and the N ⁺ type source region 6 are provided on a part of the semiconductor substrate 1 between the source region and the drain region.
The floating gate electrode 3 is provided via the gate insulating film 2, and the control gate electrode 25 is formed on the floating gate electrode 3 via the second gate insulating film 4. The floating gate electrode 3 and the control gate electrode 5 are formed in a self-aligned manner in the channel length direction.

The operating principle of this memory transistor will be described. The writing operation is a normal UV erase type EPR
Similar to the OM, a high voltage is applied to the N ⁺ type drain region 7 and the control gate electrode 5, and hot electrons generated in the pinch-off region in the channel are injected into the floating gate electrode 3 so-called hot electron injection. In the erasing operation, a high voltage is applied to the N ⁺ type source region while the control gate electrode 5 is grounded, and electrons are emitted from the floating gate electrode 3 by using a Fowler-Nordheim type tunnel current. At this time, in the memory cell, the conventional EEPROM
It is usual to stop the erase operation in the state where negative charges remain in the select gate electrode such as M.

5 and 6 are a circuit diagram and a plan view showing such a conventional nonvolatile semiconductor memory device. 1
The bit memory cell comprises a two-layer structure of a floating gate electrode 3 and a control gate electrode (X ₁ ), and an N ⁺ type drain region 7 and an N ⁺ type source region 6 on both sides thereof. The control gate electrodes are commonly connected between the memory cells adjacent in the lateral direction to form the word line X ₁ . Further, a contact hole 8 is opened in the N ⁺ type drain region 7 of the memory cell and is connected to the metal wiring forming the digit line Y ₁ . A contact hole 9 is also formed on the N ⁺ type region connecting the N ⁺ type source region 6 to fix the source potential and connected to the metal wiring (Vs). A predetermined erase voltage is applied.

The gate electrodes and drain regions of the memory transistors Q _{i, j} (i = 1, 2, ... M, j = 1, 2, ... N) shown in FIGS. 4 and 6 are word lines X ₁ and X _1, respectively. It is connected to the digit line Y _j . A memory transistor Q _{i, 1} , whose gate electrode is connected to word X _i ,
, Q _{i, n} is applied with the output voltage Vs of the erase voltage applying circuit via the transistor R _i (normal MOS transistor). The transistors R ₁ , ..., R _m are not shown in FIG.

[0008]

In this conventional nonvolatile semiconductor memory device, the controllability of erasure has been a serious problem. As described above, when erasing the information in this memory cell, it is necessary to stop the erasing before the depletion state is reached in principle. It was necessary to stop erasing. At this time, it is the "turn-on phenomenon" at the time of writing that defines the lower limit of erasing. That is, when the threshold voltage after erasing decreases (even in the enhancement state)
The potential of the floating gate electrode may be pulled up and the channel may become conductive just by applying a high voltage to the drain like a non-selected cell on the same digit line at the time of writing. This is called the "turn-on phenomenon". If this phenomenon occurs in the state where the cell matrix is configured, the write-in voltage of the digit line drops due to the turn-on current, and writing cannot be performed sufficiently. There was a problem of disappearing. To avoid this "turn-on phenomenon", the erase level must be stopped at a value high enough for it. However, even if the lower limit of the erase level is high, the upper limit is defined by the read condition, and the existence of the "turn-on phenomenon" consequently narrows the allowable range of the erase level. As memory capacity has increased as in recent years, the number of memory cells connected to a single digit line increases even though the variation in erase level inevitably increases. "Phenomenon" will impose a stricter limit (even if the turn-on current of 1 bit is very small, it will not be neglected due to the large number of them, so the "turn-on phenomenon" will increase as the capacity increases. The lower limit of the erasing level specified by "will increase.)" For this reason, it is difficult to control erasing with the conventional cell matrix, which is a factor that hinders an increase in capacity from the viewpoint of operation.

[0009]

According to the present invention, there are provided a second conductivity type source region and a second conductivity type drain region, a second conductivity type source region and a second conductivity type source region formed on a surface of a first conductivity type semiconductor substrate. A memory comprising a floating gate electrode formed on the semiconductor substrate between conductive type drain regions via a first gate insulating film and a control gate electrode formed on the floating gate electrode via a second gate insulating film. In a nonvolatile semiconductor memory device in which memory cells in which the control gate electrode and the second conductivity type drain region of a transistor are respectively connected to a word line and a digit line are arranged in a matrix, the second conductivity type source region is It is connected to the ground potential terminal via the first transistor having a gate electrode connected to the word line and is erased via the second transistor. Is connected to the output terminal of the voltage application circuit,
The gate electrode of the second transistor is connected to a control signal line different from the word line.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of the first embodiment of the present invention. A memory transistor matrix is formed by arranging memory transistors Q _{i, j} at intersections of word lines X _i and digit lines Y _j , and the N ⁺ -type source regions of the memory transistors are commonly connected in the word line direction. Is connected to the ground potential terminal via the first transistor P _i (normal MOS transistor), and the transistor P _i
Is connected to the word line X _i . Further, the output voltage Vs of the erase voltage applying circuit is applied to the source region of the memory transistor via the second transistor R _i . The erase voltage application circuit supplies a high voltage for erase during the erase operation, and normally has the ground potential during writing and reading. The output voltage Vs of the erase voltage application circuit is also applied to the gate electrode of the transistor R _i .

Next, the operation of this embodiment will be described by taking the memory transistor Q _{i, j} as an example. First, at the time of reading, a reading voltage is applied to the digit line Y _j and the word line X _i . Since the transistor P _i is turned on by the voltage of the word line X _{i ,} the data of the memory transistor Q _{i, j} is judged by whether or not a current flows from the digit line Y _j to the ground potential through Q _{i, j} , P _i. can do.

Next, at the time of writing, a high voltage for writing is applied to the digit line Y _j and the word line X _i . At this time as well, the transistor P _i is turned on, so that the digit line Y _j
From Q _{i, j} , P _i into the ground electrode.
This current causes channel injection inside the memory transistor Q _{i, j} and data is written. At this time _, the threshold voltage of the other memory transistors Q _{i + 2, j} , Q _{i + 3, j,} etc. connected on the same digit line is low and the “turn-on phenomenon” may occur at the write voltage of Y _j. Even in such a state, the turn-on current does not flow because the transistor P _{i + 2} or P _{i + 3} is not conducting. Here, only memory transistors Q _{i + 1, j} on the same digit line and having a common source are involved in "turn-on". Q i _{+ 1, j} and "turn-on phenomenon" occurs at a current flows into the ground potential through from _{Y j Q i + 1, j} , the P _i. However, like this, "turn on"
Therefore, the current flows only in 1 bit sharing the source on the digit line, and the current amount is much smaller than the write current (if it is only 1 bit), it affects the write characteristics of Q _{i + j.} Little to give.

As described above, even if the threshold voltage of the other memory cell is lowered and the "turn-on phenomenon" occurs, the transistor (P _{i + 2)} for interrupting the current path is cut off.
Etc.) enables writing without being influenced by “turn-on”. Note that the transistors R _i and R _{i + 2} are always off at the time of writing and reading, and thus are irrelevant to the operation.

Erasing of the memory cell Q _{i, j} is performed by grounding the gate and applying a high voltage to the source. Here, the high voltage Vs at the source is applied to the source of each memory cell through transistors R _i , R _{i + 2,} etc. At this time, since the word lines X _{i to} X _{i + 3 and the} like are grounded, the transistors P _{i to} P _{i + 3 and the} like are off, and the data in each memory cell is erased collectively.

FIG. 2 shows a part of a plan view of the semiconductor chip represented by the circuit shown in FIG. However, the second transistor R _{i and the} like are not shown. The control gates are commonly connected between the memory cells adjacent in the lateral direction, and the word lines X _i , ...
However, at the same time, transistors P _i , ... Are also formed. The N ⁺ type source region 6 is connected to the metal wiring 1 through the first contact hole 10 via the transistor P _i and is supplied with the ground potential. Further, the N ⁺ type source region 6 is connected to the metal wiring (Vs) through the second contact hole 9 and further connected to the second transistor R _i .

In this embodiment, the second transistor R
The gate electrodes of _i , R _{i + 2} , ... Are connected to the output terminal (Vs) of the erase voltage applying circuit, but at this time, the source of the memory transistor has transistors R _i , R rather than Vs.
A voltage reduced by the threshold voltage of _{i + 2} is supplied. Vs
Is applied to the source region as it is, R _i , R
_A voltage higher than Vs by a threshold voltage or more may be applied to the gate such as _{i + 2} .

Further, the second transistors R _i , R _{i + 2} ,
.. may not be connected to the output terminal of the erase voltage application circuit but may be connected to the output terminal of the erase decoder. Then, for example, when erasing the data of the memory transistor Q _{i, j} , the sector to which Q _{i, j} belongs (a group connected in the source region. Here, Q _{i, 1} ...
Q _{i, n} and Q _{i + 1,1 to} Q _{i + 1, n} belong to the same sector. ) Is applied to the gate electrode of the transistor R _i so as to select the transistor R _i to be connected thereto, only the output signal Z _i of the erasing decoder is set to a high voltage. As a result, the output voltage Vs (high voltage) of the erase voltage applying circuit is applied to the source regions of Q _{i, 1 to} Q _{i, n} and Q _{i + 1,1 to} Q _{i + 1, n} through the transistor R _i . At this time, the word lines X _i , X
_{Since i + 1} is grounded, the transistors P _i and P _{i + 2}
Is off, and the data of the memory transistors on the word lines X _i and X _{i + 1} are erased collectively. The data in the memory transistor of the unselected sector is not erased because the second transistors other than R _i are off.
In this way, block erasing can be performed for every two word lines.

FIG. 3 shows a second embodiment of the present invention. First
In this embodiment, cells adjacent to each other in the digit line direction, for example, Q
_{Since i, j} and Q _{i + 1, j} and Q _{i + 2, j} and Q _{i + 3, j} share the source area, the "turn-on current" at the time of writing is avoided by only one bit. I couldn't do it. In this embodiment, the sharing of the source is stopped and each word line is made independent. As a result, writing that is completely free from the "turn-on phenomenon" has become possible. Also in this embodiment, a voltage higher than the output voltage of the erase voltage application circuit may be applied to the gate electrodes of the second transistors R ₁ , ..., R _i , ... Or the output signal of the erase decoder may be applied. May be. In the latter case,
Depending on the method of decoding, either erasing with one word line or erasing with arbitrary plural word lines is possible.

7 and 8 are a circuit diagram and a plan view of the third embodiment.

In this embodiment, the memory transistor Q _{i, j}
Were ligated N ⁺ type source region 6 and the like in the word line direction N ⁺
The type region is formed through the first metal wiring 12 (aluminum-based alloy film or refractory metal silicide film, that is, the term “metal wiring is used in this specification including an alloy film such as silicide)” and the contact hole 13. There is a feature in the connected point. The first metal wiring 12 is a memory transistor Q _{i, j}
After forming the, an interlayer insulating film is deposited to form a contact hole 13 (N ⁺ reach N ⁺ -type region connecting the source region 6), for example, an aluminum alloy film is patterned deposited form To be done. That is, in this embodiment,
The source line is composed of two layers of the N ⁺ type region and the first metal wiring and has a low resistance. The first metal wiring 12 extends in the word line direction, and one end thereof is connected to one source / drain region 14 (N ⁺ type diffusion layer) of the second transistor through a contact hole 15.

The second transistors R _i , ... Have gate electrodes G _i , .. (a polycrystalline polysilicon film formed in the same step as the floating gate electrode 3) and a pair of source / drain regions 14, 16. And the other source / drain region 16
Is connected through a contact hole 17 to an erase signal line Vs (shown by the same symbol as the output voltage Vs of the erase voltage applying circuit for the sake of simplicity) of the same layer as the first metal wiring 12 and made of, for example, an aluminum alloy film. It

The drain region 7 of the memory transistor Q _{i, n} or the like is provided with a second metal wiring (first
Other interlayer insulation film is provided between the metal wiring of
Connected to the digit line Y _n .

One of the source / drain regions of the first transistor P _i, etc., which is not connected to the source region 6 of the memory transistor, is formed through the first contact hole 10 in the same layer as the digit line Y _n ,. 2nd layer metal film)
Is connected to the ground potential end by the metal wiring 11a.

The gate electrodes G _i , ... Of the second transistors R _i , ... Are respectively connected to the gate wirings 18 _i ,. In the circuit diagram of FIG. 7, the gate wirings 18 _i , ... Are connected to the output terminal Z _i of the erasing decoder. However, the erasing signal line Vs is similar to that described in the first and second embodiments. Or other appropriate control signal lines may be connected.

In this embodiment, only two digit lines are shown between adjacent source lines for the sake of simplicity, but 16 to 32 digit lines are actually provided. A first transistor P _i that interrupts the current path between the source and ground
In the case of using, it is necessary to increase the channel width of this transistor in order to suppress the influence of the source resistance at the time of writing to the EPROM, and to increase the frequency of providing this transistor to one out of 16 to 32 digit lines. As a result, the influence on the chip area cannot be ignored, but as in this embodiment, the source region is connected to the first metal wiring 12 through the source contact hole 13 to line the source region and reduce the source resistance, thereby reducing the current. The first transistor for blocking the path may be provided at both ends of the memory cell matrix in the word line direction, for example. Wherein the first metal wiring 12 and the second metal wires (11a, Y _n) and may be a vertical relationship in its layered structure contrary.

The operation of this embodiment is the same as that of the first embodiment and will not be described in detail. Gate wiring 18 _i ,
.. is connected to the output terminal of the erase voltage applying circuit, the structure is the simplest, but the source of the memory transistor is supplied with a voltage lower than Vs by the threshold voltage of the second transistor R _i ,. .. If you want to apply Vs to the source of the memory transistor as it is, gate wiring 1
A voltage higher than Vs by a threshold voltage or more may be applied to 8 _i , .... Further, by connecting to the output terminal of the erasing decoder, block erasing can be performed for every two word lines.

In the third embodiment, in order to reduce the resistance of the source line of the first embodiment, it is lined with the first metal wiring, but in the second embodiment, the first metal is provided for each word line. It can be lined with wiring and has an advantage that the chip area can be made smaller than that of the second embodiment.

In the plan views of FIGS. 2, 6 and 8 referred to in the above description, the width of the floating gate electrode 3 (corresponding to the channel length)
Is smaller than the width of the word line for convenience of illustration, but in reality, the widths of both are substantially the same. Further, in FIG. 8, the N ⁺ type diffusion layer portion is shaded, but it does not mean the cross section.

[0030]

As described above, the present invention has almost no influence on the "turn-on phenomenon" of an unwritten cell by providing a transistor between the source region of the cell transistor of the flash EEPROM and the ground potential terminal. It becomes possible to write without receiving, and as a result of applying the erase voltage from the erase voltage applying circuit to the source region through the second transistor, it is possible to perform collective erase. As a result of the realization of a cell matrix that is hardly affected by the "turn-on phenomenon",
The lower limit of the allowable range of the erase level of the cell can be expanded from the threshold voltage at which the "turn-on phenomenon" does not occur to "0 V or more".

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a self-aligned gate type memory transistor.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a plan view of a semiconductor chip showing a conventional example.

FIG. 7 is a circuit diagram used to describe a third embodiment of the present invention.

FIG. 8 is a plan view used to describe a third embodiment of the present invention.

[Explanation of symbols]

1 P-type silicon substrate 2 First gate insulating film 3 Floating gate electrode 4 Second gate insulating film 5 Control gate electrode 6 N + type source region 7 N + type drain region 8, 9, 10 Contact hole 11 Metal wiring 11a Second Metal wiring 12 first metal wiring 13 contact hole 14 source / drain region 15 contact hole 16 source / drain region 17 contact hole 18i gate wiring P ₁ , P ₂ , ..., P _i , ..., P _m first transistor Q _{i, 1} , ..., Q _{i, j} , ..., Q _{m, n} memory transistor R ₁ , ..., R _m second transistor X ₁ , ..., X _m word line Y ₁ , ..., Y _n digit line Vs Output voltage of erase voltage generation circuit (or signal line or metal wiring to which output voltage of erase voltage generation circuit is applied)

Claims (8)

[Claims] 1. A semiconductor region between a second conductivity type source region and a second conductivity type drain region formed on the surface of a first conductivity type semiconductor substrate, and the second conductivity type source region and the second conductivity type drain region. The control gate electrode of a memory transistor, which comprises a floating gate electrode formed on a substrate via a first gate insulating film and a control gate electrode formed on the floating gate electrode via a second gate insulating film, and In a non-volatile semiconductor memory device in which memory cells, each having a second conductivity type drain region connected to a word line and a digit line, are arranged in a matrix, the second conductivity type source region has a gate connected to the word line. It is connected to the ground potential terminal via the first transistor having an electrode and is connected to the output terminal of the erase voltage applying circuit via the second transistor. And a gate electrode of the second transistor connected to a control signal line different from a word line. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the control signal line is an output signal line of the erase voltage applying circuit. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a voltage higher than the output voltage of the erase voltage applying circuit is applied to the control signal line. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a decode signal at the time of erasing is applied to the control signal line. 5. A semiconductor region between a second conductivity type source region and a second conductivity type drain region formed on a surface of a first conductivity type semiconductor substrate, and the second conductivity type source region and the second conductivity type drain region. The control gate electrode of a memory transistor, which comprises a floating gate electrode formed on a substrate via a first gate insulating film and a control gate electrode formed on the floating gate electrode via a second gate insulating film, and In a non-volatile semiconductor memory device in which memory cells, each having a second conductivity type drain region connected to a word line and a digit line, are arranged in a matrix, the second conductivity type source region is a metal wiring in the word line direction. A second transistor connected to the ground potential terminal via a first transistor having a gate electrode lined and connected to the word line; A non-volatile semiconductor memory device characterized in that the gate electrode of the second transistor is connected to the output terminal of the erase voltage applying circuit via a transistor and to a control signal line different from the word line. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the control signal line is an output signal line of the erase voltage application circuit. 7. The nonvolatile semiconductor memory device according to claim 5, wherein a voltage higher than the output voltage of the erase voltage applying circuit is applied to the control signal line. 8. The nonvolatile semiconductor memory device according to claim 5, wherein a decode signal at the time of erasing is applied to the control signal line.