JPH05325559A - Memory control circuit - Google Patents

Abstract

PURPOSE:To obtain a memory control circuit which prevents the contents of other memory cells from being rewritten dependent on the contents of a memory cell which are read out when the contents of plural memory cells 2 are successively read out. CONSTITUTION:An address signal variation detecting circuit 8 is used and even if the output signal of an address decoder 1 varies at delicate timing, word lines are so controlled that plural memory cells 2 are not selected at the same time. At this time, an input signal to the address decoder 1 is led out of a delay circuit 30 in the address signal variation detecting circuit 8 for timing adjustment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit of a memory device (RAM) capable of reading and writing the contents of memory cells.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional RA having a built-in gate array.
An outline of the configuration of the M circuit is shown. In the figure, 1 is an address decoder circuit, 2 is a memory cell, 3 is an input control circuit, 4 is an output circuit, 5 is a precharge circuit, 6 and 7 are bit lines, 10 and 11 are inverters in the memory cell 2, and 12 , 13 are n-channel type transistors in the memory cell 2, and in this example, a 64-word 1-bit RAM having 64 memory cells is configured.

The address decoder 1 is connected to six address input terminals AD0 to AD5, and has 64 output signals X.
0 to X63 are connected as word lines to select terminals in 64 memory cells, respectively. The memory cell 2 has a pair of inverters 10, 1 whose input and output are connected to each other.
1 and its pair of inverters, and two n-channel type transistors 12 and 13 connected between the bit lines 6 and 7 for reading and writing data to and from the memory cell, which are in an inverted relationship with each other. .. 3 is the data input signal D
It has a function of transmitting IN to the bit line by inversion and non-inversion, and comprises a three-value output inversion and non-inversion circuit which can inhibit the transmission based on the state of the control terminal WE. Four
Is an output circuit to which the bit line 6 for reading the state of the memory cell is input. 5 is bit lines 6 and 7
Has two p-channel type transistors for precharging the potential of, the source and drain terminals are connected between each bit line and the high potential side power supply (VDD) terminal, and the gate terminal is connected to the WE signal. It is connected. 6
Bit lines 7 and 7 are non-inverted with the data input signal when the WE signal is in the active state (“H”),
The signal level is set to an inversion relation, and when the WE signal is not in the active state and the address decode outputs are all at "L" level, the precharge circuit 5 sets it to "H" level.

AD0-5 are address input signals to the address decoder 1 and select one of 64 memory cells. CE is an enable signal, A
This is a signal for setting all the word lines X0-63 to non-selection ("L") regardless of the state of D0-5. X0
-63 is an output signal of the address decoder 1, which is AD0
Corresponding to the state of -5, one of the signals X0-63 becomes the active state ("H"). WE is a data write signal to the memory cell. DIN is input data for writing data to the memory cell, and DOUT is a data output signal.

Next, data 0 is written in the memory cell of Xi.
The operation will be described by exemplifying a case where data (1) ("H") is written in the memory cell Xj after writing ("L") and then data in the memory cells Xi and Xj are sequentially read. Here, i and j are arbitrary 2 from 0 to 63
It is a value.

FIG. 8 shows a timing chart of the operation. At timing t1, the word line Xi becomes "H" level by the address input signal AD0-5, and a "L" level signal is input to DIN for writing data 0. At timing t2, the write signal WE becomes "H" level and the bit line 6 becomes "L" level and the bit line 7 becomes "H" level. In this state, data 0 is written in the memory cell to which the word line Xi is connected.

Next, at timing t3, the address input signal A
D0-5 changes and the word line Xi becomes "L" level and the word line Xj becomes "H" level. An "H" level signal is input to DIN to write data 1. At timing t4, the write signal WE becomes "H" level and the bit line 6 becomes "H" level and the bit line 7 becomes "L" level. In this state, data 1 is written in the memory cell to which the word line Xj is connected.

Since the data writing is completed, the data is read next. Address input signal A at timing t5
D0-5 changes so that the word line Xi becomes "H" level and the word line Xj becomes "L" level. After that, since the write signal WE maintains the "L" level, the "L" level is read out to the output terminal DOUT.

After that, at timing t6, the address input signals AD0-5 change, the word line Xi goes to "L" level,
The word line Xj becomes "H" level. Since the write signal WE also maintains the "L" level at this time, the "H" level is read out to the output terminal DOUT. In this way, the data in the memory cell is read and written.

Here, the p-channel transistor in the precharge circuit is turned on at the time of reading data, but when each bit line is set to the "L" level, the potential of the bit line becomes an inverter in the memory cell. Also, it is designed in consideration of the sizes of the inverter and the n-channel transistor in the memory cell so that the voltage is not more than the transition voltage of the output circuit.

The conventional RAM memory with a built-in gate array operates as described above, but it may cause a problem, and its contents will be described below. FIG. 9 shows the internal structure of the memory cell along with word lines Xi and Xj and bit lines 6 and 7.

In the figure, 6 and 7 are bit lines, Xi
, Xj are word lines, 10pi, 10ni, 11pi, 1
1ni, 10pj, 10nj, 11pj, and 11nj are transistors forming inverters 10i, 11i, 10j, and 11j, respectively. Ai, Bi, Aj, and Bj are symbols indicating signal positions provided to indicate the potential in the memory cell, and inverters 10i, 11i, and 1 respectively.
Inputs of 0j and 11j and 11i, 10i, 11j and 10
Corresponds to the output of j. 12i, 13i, 12j, 13j
Are n-channel transistors for connecting Ai, 6, Bi and 7, Aj, 6, Bj and 7, respectively.

FIG. 10 shows an operation timing chart for explaining an example of a defect. Data 0 in the memory cell of Xi
("L") is data 1 ("H") in the memory cell of Xj
The operation will be described by taking as an example the case where the data of the memory cells of Xi and Xj are sequentially read in the state where is written.

The potential at each point immediately before the timing t11 is shown in FIG.
0, WE, Xj, Ai, Bj, bit line 6, DOUT is "L" level, CE, Xi, Bi, Aj
, The bit line 7 is at "H" level. At timing t11, the address signals AD0-5 change and Xi is "H".
To "L", and Xj changes from "L" to "H". At this time, focusing on the bit line 6,
Is the memory cell A corresponding to Xi until timing t11.
It is at the "L" level in response to the potential of i, and the timing is t11.
After that, at the time of normal operation, it receives the potential of Aj of the memory cell corresponding to Xj and becomes "H" level.

Extending the time after the timing t11 and looking at the potential change at each point, a period n in which both Xi and Xj are present
Channel transistors 12i, 13i, 12j, 13j
In some cases, the potential at which all are turned on is maintained. That is, for bit line 6, 11ni, 12i, 11
pj and 12j are turned on at the same time, and for bit line 7, 10pi, 13i, 10nj and 13j are turned on at the same time.

Bit line 6 is at "L" level and bit line 7 is at "H" level. From this state, 11pj, 1
2j causes bit line 6 to go to "H" level, 10nj, 1
The bit line 7 is driven by 3j to change to the "L" level, but due to the fact that 12i and 13i are in the ON state and the parasitic capacitance of the bit lines 6 and 7, it is not possible to change the potential sufficiently. In addition, 10nj and 11pj are turned on and off, 10pj and 11nj are turned from off to on, and Aj changes from "H" level to "L" level and Bj changes from "L" level to "H" level. That is, a malfunction occurs in which the contents of the memory cell corresponding to Xj are rewritten from data 1 to data 0.

This state is maintained even after 12i and 13i are completely turned off. As a result, the bit line 6 maintains the "L" level, the bit line 7 maintains the "H" level, and DOUT is "the". It remains at the L "level.

[0018]

As described above, in the conventional memory circuit with a built-in gate array, the change of the address decoder output signal (word line) is subtly related to each other.
There has been a problem that the contents of the memory cell are rewritten and a malfunction occurs.

The present invention has been made in order to prevent a malfunction in the memory circuit having a built-in gate array as described above. The timing is so delicate that the output of the address decoder circuit may malfunction as shown in the conventional example. Even if it changes with
The purpose is to obtain a memory control circuit in which the contents of memory cells are not rewritten.

A second object of the present invention is to obtain a memory control circuit capable of reducing current consumption when a plurality of memories are used and only one of them operates.

[0021]

A memory control circuit according to the present invention has an address decoder circuit which receives an address signal that has passed through a delay circuit in an address signal change detection circuit as an input. The output signal is the precharge control signal of the data line,
The output of the gate circuit, which receives the output of the address decoder circuit and the output of the address signal change detection circuit, is used as a word line. Further, the address signal change detection circuit and the address decoder circuit are controlled by the enable signal.

[0022]

In the present invention, the state of the word line is controlled by the output of the address signal change detection circuit. Therefore, when the contents of a plurality of memory cells are continuously read, there is a delicate time between the output of the address decoder. Even if a difference occurs, multiple memory cells are not selected at the same time,
It is possible to prevent the content of another memory cell from being rewritten by the content of the memory cell read out immediately before.

Further, since the address signal change detection circuit and the address decoder circuit are controlled by the enable signal, even when the address signal is shared by a plurality of memories, the address signal is not enabled in the memory in the disable state. Even if it changes, it consumes almost no power.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a memory control circuit according to an embodiment of the present invention. In the figure, 1 is an address decoder circuit, 2 is a memory cell, 3 is an input control circuit, 4 is an output circuit, 5 is a precharge circuit, and 6 and 7. Is a bit line, and 8 is an address signal change detection circuit. An internal circuit example is shown in FIG. Reference numeral 9 is an AND circuit, 10 and 11 are inverters in the memory cell, 12 and 13 are n-channel transistors in the memory cell, 20 is an OR circuit, 21 and 22 are inverters, 23 is an AND circuit, and 24 is a NOR circuit. ..
Also in this example, as in the conventional example, a 64-word 1-bit RAM having 64 memory cells is configured.

In FIG. 3, the address signal input terminal AD
n is connected to the inverter 31, one terminal of the transmission gate 35, and the delay circuit 30, the output of the inverter 31 is connected to one terminal of the transmission gate 34, and the delay circuit 30 is connected to the gate terminals of the transmission gates 34 and 35. Output of the inverter 32,
It is connected via 33. The An signal connected to the address decoder is output from the delay circuit 30, the other terminals of the transmission gates 34 and 35 are connected and output as the ATDn signal.

The address input signal A0-5 of the address decoder 1 is connected to the input of A0-5 of the address decoder 1, and the address input signal A0-5 is connected to the address signal change detecting circuit 8 via the delay circuit. Six address input terminals AD0-5 for supply are connected.
WE is a data write signal to the memory cell. DIN
Is the data for writing data in the memory cell, and DOUT
Is a data output signal. Address signal change detection circuit 8
The signal change detection outputs ATD0-5 of 1 are connected to the precharge circuit and the other to one input terminal of the AND circuit 9 via the OR circuit 20, the AND circuit 23, and the NOR circuit 24. An enable signal CE is connected to the other input of the NOR circuit 24 via the inverter 21.
The write signal WE is connected to the other input of the AND circuit 23 via the inverter 22.

The 64 output signals of the address decoder 1 are connected to the other input terminal of the AND circuit 9, and the output terminal of the AND circuit 9 is connected as a word line to the select terminal in each of 64 memory cells. There is.

The memory cell 2 includes a pair of inverters 10 and 11 having inputs and outputs connected to each other, and a pair of inverters and bit lines which are in an inverted relationship for reading and writing data from and to the memory cell. It is composed of two n-channel transistors 12 and 13 connected to each other.

Reference numeral 3 is an inverting and non-inverting circuit for ternary output which has a function of transmitting the data input signal DIN to the bit line by inversion and non-inversion, and can inhibit the transmission based on the state of the control terminal WE. There is. An output circuit 4 receives the bit line 6 for reading the state of the memory cell. Reference numeral 5 has two p-channel type transistors for precharging the potentials of the bit lines 6 and 7, the source and drain terminals of which are connected between each bit line and the high potential side power supply (VDD9) terminal. The gate terminal is connected to the output terminal of the NOR circuit 24.

Bits 6 and 7 are bit lines, which are set to signal levels which are in the non-inverted and inverted relation with the data input signal at the time of writing, that is, when the WE signal is in the active state ("H"), and at the time of reading. (CE is “H”, W
When E is "L"), the signal level of the selected memory cell is set, and when CE and WE are both "L" or when the address signal changes during reading, the precharge p
It is set to "H" level by the channel type transistor.

Next, data 0 is stored in the memory cell of Xi.
The operation will be described by exemplifying a case where data (1) ("H") is written in the memory cell Xj after writing ("L") and then data in the memory cells Xi and Xj are sequentially read. Here, i and j are arbitrary 2 from 0 to 63
It is a value.

FIG. 2 shows an operation timing chart. Address input signals AD0-5 are word line X at timing t1.
i is set to a selectable value. At this time, the output of the NOR circuit 24 generates an "L" level pulse signal by the address signal change detection circuit. By this pulse, the bit lines 6 and 7 are precharged to "H" level, the word lines X0-63 are set to "L", and all the memory cells are in the non-selected state.

The NOR circuit 24 becomes "H" at the timing tp1.
Then, the word line Xi becomes "H" level. On the other hand, a signal of "L" level is input to DIN for writing data 0, and the write signal W is output at the timing t2.
When E becomes "H" level, the bit line 6 becomes "L" level and the bit line 7 becomes "H" level. In this state, data 0 is written in the memory cell to which the word line Xi is connected.

Next, at timing t3, the address input signal A
D0-5 changes, the word line Xj is set to a value that can be selected, and the word line Xi becomes "L" level. At this time, similarly to the timing t1, the output of the NOR circuit 24 generates a pulse signal of "L" level by the address signal change detection circuit. By this pulse, the bit lines 6 and 7 are once precharged to the “H” level, and the word line X
0-63 is set to "L", and all memory cells are in the non-selected state.

The NOR circuit 24 becomes "H" at the timing tp2.
Then, the word line Xj becomes "H" level. On the other hand, a signal of "H" level is input to DIN for writing the data 1, and the write signal WE becomes "H" level at timing t4, and the bit line 6 is set to "H" level,
The bit line 7 is set to "L" level. In this state, data 1 is written in the memory cell to which the word line Xj is connected.

Since the data writing is completed, the data is read next. Address input signal A at timing t5
D0-5 changes to a value capable of setting the word line Xi to "H", and the word line Xj becomes "L" level. At this time, similarly to the timings t1 and t3, the output of the NOR circuit 24 generates a pulse signal of "L" level by the address signal change detection circuit. This pulse causes bit line 6,
7 is once precharged to "H" level, the word lines X0-63 are set to "L", and all the memory cells are in the non-selected state.

The NOR circuit 24 is "H" at the timing tp3.
When returning to the level, the word line Xi becomes the "H" level. After that, since the write signal WE maintains the "L" level, the "L" level is read out to the output terminal DOUT as the data of the memory cell to which the word line Xi is connected.

Address input signal AD0 at timing t6
-5 changes to a value that can set the word line Xj to "H", and the word line Xi becomes "L" level. At this time, similarly to the timings t1, t3, and t5, the output of the NOR circuit 24 generates a pulse signal of "L" level by the address signal change detection circuit. By this pulse, the bit lines 6 and 7 are once precharged to "H" level, the word lines X0-63 are set to "L", and all the memory cells are in the non-selected state.

The NOR circuit 24 becomes "H" at the timing tp4.
Then, the word line Xj becomes "H" level. After that, since the write signal WE maintains the "L" level, the "H" level is read out to the output terminal DOUT as the data of the memory cell to which the word line Xj is connected.
At timing t7, the address signals AD0-5 change and the word line Xj changes to "L". In this way, the data in the memory cell is read and written.

Here, the timing of the signal applied to the two input terminals of the AND circuit 9 will be described. As shown in FIG. 6, the timing t30 or t31 at which the output of the address decoder circuit 1 changes from "L" to "H" or "H" to "L" is the period when the output of the NOR circuit 24 is "L". If it is outside, the same problem as in the conventional example occurs. In order to avoid this, in order to adjust the timing of An which is an input signal to the address decoder, the An signal is taken out from the delay circuit 30 in the address signal change detection circuit 8. The original purpose of the delay circuit 30 is to determine the pulse width of the ATDn signal when the address signal changes.

Example 2. FIG. 4 shows a second embodiment of the present invention, in which 1 is an address decoder circuit, 2 is a memory cell, 3 is an input control circuit, 4 is an output circuit,
Reference numeral 5 is a precharge circuit, 6 and 7 are bit lines, and 8 is an address signal change detection circuit. An example of an internal circuit is shown in FIG. Reference numeral 9 is an AND circuit, 10 and 11 are inverters in the memory cell, 12 and 13 are n-channel transistors in the memory cell, 20 is an OR circuit, 22 is an inverter, and 25 is a NAND circuit. Also in this example, as in the conventional example, a 64-word 1-bit RAM having 64 memory cells is configured.

In the second embodiment, the CE signal connection point and the supply signal generator for the precharge circuit 5 and the AND circuit 9 are different from those in the first embodiment, and the description of the same parts will be omitted. .. The signal change detection outputs ATD0-5 of the address signal change detection circuit 8a are connected to the precharge circuit 5 via the OR circuit 20 and the NAND circuit 25, and the other to one input terminal of the AND circuit 9. .. The write signal WE is connected to the other input of the NAND circuit 25 via the inverter 22.

In FIG. 5, address signal input terminal AD
n is connected to the inverter 40, the enable terminal CE is connected to one terminal of the inverter 41 and the NAND circuit 43, and the output of the inverter 40 is one input terminal of the NOR circuit 42, the other input terminal of the NAND circuit 43, and The output of the NOR circuit 42 is connected to the delay circuit 30, the output of the NAND circuit 43 is connected to one terminal of the transmission gate 35, and the gate terminals of the transmission gates 34 and 35 are connected to one terminal of the transmission gate 34. The output of the delay circuit 30 is the inverter 32, 3
It is connected to each of them via 3. The An signal connected to the address decoder is output from the delay circuit 30, and the other terminals of the transmission gates 34 and 35 are connected and output as the ATDn signal.

Next, the operation will be described. If the output signal of the NAND circuit 25 is replaced with the output signal of the NOR circuit 24, the operation when the enable terminal CE is "H" operates similarly to the timing chart of the first embodiment shown in FIG.

When CE is "L", the output of the NOR circuit 42 is "L", the transmission circuit 35 is on, and the output of the NAND circuit 43 is "H".
ATDn becomes "H", the output of the NAND circuit 25 becomes "L", and the selection of the memory cell is also prohibited (WE becomes "L" when disabled). That is, the circuit that operates even when the address input signal ADn changes is limited to the inverter 40 and does not consume unnecessary current.

[0046]

As described above, according to the present invention, the bit line is precharged by the output signal of the address signal change detection circuit, and the input signal for the address decoder is supplied from the delay circuit in the address signal change detection circuit. Since the memory cell selection signal (word line) is controlled by taking out the above, there is an effect that a malfunction does not occur even if the signal in the memory cell is continuously read.

Since the address signal change detection circuit is controlled directly by the enable signal CE, a plurality of memory cell blocks are controlled by using the same address signal,
When one of a plurality of memory cell blocks is selected by the CE signal, there is an effect that the operation is performed with a minimum required current consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory control circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of a memory control circuit according to an exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration in an address signal change detection circuit according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a memory control circuit according to another embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a configuration in an address signal change detection circuit according to another embodiment of the present invention.

FIG. 6 is a timing chart for explaining a relationship between an address decoder output and a word line.

FIG. 7 is a circuit diagram of a conventional memory control circuit.

FIG. 8 is a timing chart for explaining the operation of the conventional memory control circuit.

FIG. 9 is a circuit configuration diagram inside a memory cell for explaining a malfunction of a conventional memory control circuit.

FIG. 10 is a timing chart for explaining a malfunction of the conventional memory control circuit.

[Explanation of symbols]

 1 Address Decoder Circuit 2 Memory Cell 3 Input Control Circuit 4 Output Circuit 5 Precharge Circuit 6 Bit Line 7 Bit Line 8 Address Signal Change Detection Circuit 9 AND Circuit 10 Inverter 10i Inverter 10pi p-Channel Transistor 10ni n-Channel Transistor 10j Inverter 10pj p-channel type transistor 10nj n-channel type transistor 11 inverter 11i inverter 11pi p-channel type transistor 11ni n-channel type transistor 11j inverter 11pj p-channel type transistor 11nj n-channel type transistor 12 n-channel type transistor 12i n-channel type transistor 12j n-channel type transistor 13 n-channel transistor 13i n-channel transistor 13j n-channel Transistor 20 the OR circuit 21 inverter 22 inverter 23 AND circuit 24 NOR circuit 25 NAND circuit 30 a delay circuit 31 inverter 32 inverter 33 inverter 34 transmission gate 35 transmission gate 40 inverter 41 inverter 42 NOR circuit 43 NAND circuit

Claims (2)

[Claims] 1. A memory control having a memory cell, a data line for reading and writing data in the memory cell, a word line for selecting the memory cell, and an address signal change detection circuit for detecting a change in an address signal. In the circuit, the address signal passing through the delay circuit in the address signal change detection circuit is used as an input to the address decoder circuit, and the output signal of the address signal change detection circuit is used as the precharge control signal for the data line. A memory control circuit, wherein an output of a gate circuit which receives an output of the circuit and an output of the address signal change detection circuit is the word line. 2. A memory control having a memory cell, a data line for reading and writing data in the memory cell, a word line for selecting the memory cell, and an address signal change detection circuit for detecting a change in an address signal. A memory control circuit, characterized in that a change of an output signal of the address signal change detection circuit and a change of an input signal to the address decoder circuit is prohibited by a chip enable signal.