JPH05324868A - Microcomputer - Google Patents

Abstract

PURPOSE:To obtain the microcomputer which can synchronize an internal and an external system clock with each other when characteristics of a device change. CONSTITUTION:A ceramic oscillator, a crystal vibrator, an external oscillator, etc., are connected to input terminals 71 and 72, and the oscillator 4 inputs an OSCOUT signal 113 to a phase synchronizing circuit 2 and a clock generating circuit 3. The clock generating circuit 3 generates system clock signals 102 and 103 on the basis of the OSCOUT signal 113 and inputs them to a CPU 1 and the phase synchronizing circuit 2. A PLLOUT signal 114 is outputted from the phase synchronizing circuit 2 as a reference signal CLKOUT signal 101 through an output buffer 5 and then fed back to an external output and the phase synchronizing circuit 2 through a CLKOUT terminal 73. A PWRON signal 112 and signals 101-103, and 113 are inputted to the phase synchronizing circuit 2 and the delay time of the PLLOUT signal 114 is controlled so that a C2 signal and the CLKOUT signal 101 rise at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer.

[0002]

2. Description of the Related Art Generally, in a microcomputer, in order to control an input timing of a signal input from the outside of the microcomputer, a latch timing of a signal output from the microcomputer to the outside, and the like,
Many reference signals used externally have a function of outputting a clock having the same frequency as the internal system clock to the outside. Hereinafter, the clock output to the outside will be referred to as a CLKOUT signal.
Then, it is assumed here that the internal system clock has two phases. The first phase of this internal clock is called the C ₁ signal and the second phase is called the C ₂ signal. In such a microcomputer, the circuit inside the microcomputer is controlled by the C ₁ signal and the C ₂ signal, and the circuit outside the microcomputer is CL.
Since it is controlled by the KOUT signal, the interface portion of the input signal inside the microcomputer needs to be designed in consideration of the phase difference between these clocks.

FIG. 6 is a block diagram showing an outline of a conventional microcomputer, which includes an interface circuit 58, a CPU 59, and a clock generation circuit 60.
And an oscillator 61 and an output buffer 62. The CLKOUT terminal 77 has an external load capacitance 63
Has been added.

In FIG. 6, a ceramic oscillator, a crystal oscillator, and an external oscillator (these are not shown) are connected to the X ₁ terminal 75 and the X ₂ terminal 76, which are input terminals to the oscillator 61. The OSCOUT signal 113 is generated and output by the CSC as the CLKOUT signal 101 via the output buffer 62.
The signal is output from the LKOUT terminal 77 to the outside and is also input to the clock generation circuit 60. Clock generation circuit 6
At 0, the system clocks C ₁ signal 102 and C ₂ signal 103 are generated and output based on the CLKOUT signal 101, and are input to the CPU 59 and also to the interface circuit 58. The interface circuit 58 is arranged so as to be inserted between the CPU 59 and the terminal group 78, and when receiving an input signal, a signal synchronized with the CLKOUT signal 101 is
The signal is converted into a signal synchronized with the C ₁ signal 102 or the C ₂ signal 103 and input to the CPU 59. When an output signal is output, conversely, the C ₁ signal 102 or C ₁ signal
_{2 The} signal synchronized with the signal 103 is the CLKOUT signal 10
It is converted to a signal synchronized with 1 and output to the outside.

7 (a), (b), (c), (d),
(E), (f), (g), (h), (i), (j),
Shown in (k) and (l) are timing charts of clocks and input / output signals in FIG. 7 (d) and 7 (f) are input signals 115 and 117 showing a part of the signals input to the interface circuit 58 from the terminal group 78, and FIGS. 7 (h) and 7 (k) are Output signals 119 and 12 showing a part of signals output from the interface circuit 58 to the terminal group 78.
It is 1. 7 (e) and 7 (g) are input signals 118 and 120 showing a part of signals input to the CPU 59 from the interface circuit 58, and FIG.
And (l) is the interface circuit 5 from the CPU 59.
8 are output signals 120 and 122 showing a part of the signals output to FIG.

As described above, the C ₁ signal 102 and the C ₂ signal 103 of the internal two-phase system clock are generated based on the CLKOUT signal 101 which is the reference clock, so that FIG. As shown in (c), delay times of T _DC1 and T _DC2 occur, respectively. In order to prevent the delay time from being influenced by the external load capacitance 63 and to prevent the delay times T _DC1 and T _{DC2 from} being negative values, the system clock C _{1 is} once based on the CLKOUT signal 101 output to the outside. Signal 102
And the C ₂ signal 103 has been generated. 7 (c)-
As shown in (l), the input / output signal 1
It is a timing chart of 15 to 122, input signal 1
Reference numeral 15 (see FIG. 7D) is a signal input from the outside in synchronization with the rising edge of the CLKOUT signal 101. C
_{Since the} falling edge of the ₂ signal 103 is later than the falling edge of the CLKOUT signal 101, if this input signal 115 is used by being latched internally, there is a possibility that the signal may be lost, so that the interface circuit 5
8, it is necessary to once synchronize with the C ₁ signal 102 and output as the input signal 116 (see FIG. 7E). Similarly, a signal 117 externally input in synchronization with the rising edge of the CLKOUT signal 101 (see FIG. 7 (f)).
Again, in the interface circuit 58, once C
_{The two} signals 103 are synchronized and the input signal 118 (see FIG.
(See (g)). Also, CLK
When outputting a signal to the outside in synchronization with the rising of the OUT signal 101, the output signal 120 synchronized with the internal C ₁ signal 102 is CL in the interface circuit 58.
It is necessary to output as the output signal 119 (see FIG. 7 (h)) via the rising edge synchronization of the KOUT signal 101. Similarly, when outputting a signal to the outside in synchronization with the falling edge of the CLKOUT signal 101, the internal C ₂ signal 1
In the interface circuit 58, it is necessary to output the output signal 122 synchronized with the signal 03 as the output signal 121 (see FIG. 7 (k)) through the falling edge synchronization of the CLKOUT signal 101.

[0007]

In the above-described conventional microcomputer, since the circuit inside the microcomputer and the circuit outside the microcomputer are controlled by different clocks, they correspond to the input / output signals. It is necessary to provide an interface circuit, and the interface circuit increases the chip occupying area, which in turn increases the manufacturing cost.

Also, as seen in the input signals 115 and 117 shown in FIGS. 7 (d) and (f) and the output signals 120 and 122 shown in FIGS. 7 (j) and (l), a microcomputer From outside of
When the rising / falling synchronization signal of the UT signal 101 is input, C in the microcomputer is input.
A setup time for the rise of the ₂ signal 103 and the C ₁ signal 102 and a setup time for outputting a signal synchronized with the C ₁ signal 102 and the C ₂ signal 103 from the microcomputer in synchronization with the rise / fall of the CLKOUT signal 101. , FIG. 7 (d),
As shown in (f), (h) and (k), they are T _S1 , T _S2 , T _S3 and T _{S4 respectively,} and CLKOUT
When the cycle of the signal 101 is T _C , the following equation holds.

T _S1 = T _C / 2 + T _DC2 …………………… (1) T _S2 = T _C / 2 + T _DC1 ……………… (2) T _S3 = T _C / 2 + T _DC1 ………………………… (3) T _S4 = T _C / 2 + T _DC2 …………………… (4) As is clear from the above equation, T _DC1 or T _DC2 has a large value. Then, the setup time required to generate the output signals 119 and 121 becomes a small value. In the conventional microcomputer, the external load capacitance 63 at the CLKOUT terminal 77 has no influence, but the delay times T _DC1 and T _DC2 of the system clock with respect to the CLKOUT signal 101 change depending on the external temperature and manufacturing conditions. Therefore, these delay times T _DC1 and T
_When the value of _DC2 becomes large, it becomes difficult to guarantee the operation. Since the delay times T _DC1 and T _DC2 are constant irrespective of the clock frequency, they are easily affected by this, especially when the operating frequency is high.

That is, in the conventional microcomputer, the chip area occupied by the interface circuit increases, the manufacturing cost increases, and the delay time of the system clock fluctuates due to external temperature, manufacturing conditions, etc. It has the drawback that it tends to be stable.

[0011]

The microcomputer of the present invention comprises means for outputting a reference clock signal to the outside.
In a microcomputer comprising means for generating an internal multi-phase system clock signal based on the reference clock signal, a rising edge of any one of the internal multi-phase system clock signals and the rising edge of the clock signal, A rising edge of the reference clock signal output to the outside is detected and a rising edge detecting means for outputting a pair of rising edges and a phase comparing means for comparing and collating the phases of the pair of rising edges output from the rising edge detecting means. And a delay time of the reference clock signal output to the outside with respect to the reference clock signal used to generate the internal system clock signal, with reference to the phase comparison result output from the phase comparison means. A delay time control means, and a phase synchronization means including at least
It is characterized in that the phases of the internal multi-phase system clock and the reference clock signal output to the outside are synchronized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the outline of the first embodiment of the present invention. As shown in FIG. 1, this embodiment includes a CPU 1, a phase synchronization circuit 2, a clock generation circuit 3, an oscillator 4, and an output buffer 5, and the CLKOUT terminal 73 is connected to the CLKOUT terminal 73. , External load capacity 6
Has been added.

In FIG. 1, a ceramic oscillator, a crystal oscillator, and an external oscillator (these are not shown) are connected to the X ₁ terminal 71 and the X ₂ terminal 72 which are input terminals to the oscillator 4, and the oscillator 4 By O
The SOUT signal 113 is generated, output, and input to the phase synchronization circuit 2 and the clock generation circuit 3. In the clock generation circuit 3, this CLKOUT signal 113
Based on the above, the system clocks C ₁ signal 102 and C ₂ signal 103 are generated and output, and are input to the CPU 1 and also to the phase synchronization circuit 2.
The PLLOUT signal 114 is output from the phase synchronization circuit 2, and the reference signal CLKO is output via the output buffer 5.
Output as UT signal 101, CLKOUT terminal 73
Output to the outside via the phase synchronization circuit 2
Is fed back to. In this case, the phase synchronization circuit 2
PWRON signal 112 indicating power-on, C ₁ signal 10
2, C ₂ signal 103, OSCOUT signal 113 and C
The LKOUT signal 101 is input, and the C ₂ signal 10
The delay time of the PLLOUT signal 114 is controlled and adjusted so that the rising timings of 3 and CLKOUT signal 101 are equal. The operation of the phase synchronization circuit 2 will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a circuit diagram showing an example of the phase synchronization circuit 2. The rising detection circuits 7 and 8 formed by an inverter and an AND circuit, an RS flip-flop 9 and an edge trigger type D flip-flop, respectively. Group 10, inverter 11, composite gates 12, 15, 1
8 and 21 and D flip-flops 13, 14, 1
6, 17, 19, 20, 22, and 23 and the delay element 2
4 to 27, transfer elements 28 to 32, and a buffer 33.

Further, FIGS. 3 (a), (b), (c),
Shown in (d), (e), (f), (g) and (h) are timing charts of clocks and input / output signals in FIG.

1 and 2 (a) to 2 (h),
In rising edge detection circuits 7 and 8, C ₂ signal 103 (see FIG. 3C) and CLKOU are respectively generated.
Rising edge 10 of T signal 101 (see FIG. 3A)
5 (see FIG. 3 (e)) and 104 (see FIG. 3 (d))
Are detected and input to the S terminal and the R terminal of the RS flip-flop 9, respectively, and the RS flip-flop 9 is set / reset. The Q output 106 (see FIG. 3F) of the RS flip-flop 9 is input to the edge trigger type D flip-flop 10. The C ₁ signal 102 is also separately input to the edge-triggered D flip-flop 10, and the output FW signal 107 is output.
(See FIG. 3 (g)) shows the composite gates 12, 15, 18,
.., 21 and is also inverted via the inverter 11, and is similarly output as the BW signal 108 (see FIG. 3 (h)) to the composite gates 12, 15, 18 ,.
Entered in.

Composite gates 12, 15, 18, ..., 2
1 is formed by two AND circuits and one OR circuit, and each output signal has a corresponding D
It is input to the flip-flops 13, 16, 19, ... These D flip flips 13, 16, 1
9, ........., for 22, respectively C ₂ signal 103
Is also input, and each output signal is the corresponding D
It is input to the flip-flops 14, 17, 20, ... Here, the D flip-flops 13, 1
One of the D flip-flops 6, 19, ..., 22 is set to be initialized to "1" level by the PWRON signal 112, and the other D flip-flops are set to be initialized to "0". It Delay elements 24, 25, 26,
.., 27 are composed of, for example, two-stage inverters, which are connected in cascade to form the delay element 24 in the first stage.
The OSCOUT signal 113 is input to. OSCOU
T signal 113 and each delay element 24, 25, 26, ...
The output signals of 27 are input to the corresponding transfer elements 28, 29, 30, 31 ,. These transfer elements 28, 29, 30, 3
For 1, ..., 32, the signal input to the gate is "1"
It acts so as to be turned on at the level, and each gate has D flip-flops 14, 17, 20, ...
, 23 are connected, and all the outputs are output as the PLLOUT signal 114 via the buffer 33.

Next, the operation of this embodiment will be described with reference to the timing charts shown in FIGS. The timing chart is CLKOUT
It shows a state in which the system clock C ₁ signal 102 and the C ₂ signal 103 are delayed with respect to the signal 101 until the system is gradually synchronized and transits to a stable steady state. In rising edge detection circuits 7 and 8, C ₂ signal 103 and CLKOUT signal 1 are generated, respectively.
Since the rising edge of 01 is detected, the waveform of the output signal 105 of the rising edge detection circuit 7 becomes as shown in FIG. Since the RS flip-flop 9 is reset by the output signal 104 and set by the output signal 105, the Q output signal 1 of the RS flip-flop 9 is set.
06 is as shown in FIG. However, RS
In the flip-flop 9, when these set signals and reset signals compete with each other, the Q output signal 106
It is uncertain whether it will be a "1" level or a "0" level, but there is no great difference in either operation, and here, the description will be continued assuming that it is a "0" level. The above-mentioned FW signal 107 is transferred to the Q ₁ via the C ₁ signal 102 in the edge trigger type D flip-flop 10.
B is a signal output by latching the output signal 106.
The W signal 108 is a signal output by logically inverting the FW signal 107. Compound gates 12, 15, 18,
..., 21, and the D flip-flops 13, 14,
The circuits formed by 16, 17, 19, 20, ..., 22, 23 are D flip-flops 14, 17, 20, ..., 2 when the FW signal 107 becomes “1” level.
3 is a circuit for shifting the data to the left, and as described above, one of the D flip-flops 14, 17, 20, ... By initializing it to the 1 "level and other D flip-flops to the" 0 "level, the data" 1 "is shifted to the left or right by the FW signal 107 and the BW signal 108.
The position of the data “1” in the D flip-flops 14, 17, 20, ..., 23 is the OSCOUT signal 113.
, And the delay elements 24, 25, 26, ..., 27 to determine which output to select, and the PLLOUT signal 114 becomes closer to the right when the position of the data "1" is located.
Delay time for the OSCOUT signal 113 of
Further, the delay time of the PLLOUT signal 114 with respect to the OSCOUT signal 113 is shortened as the position of the data “1” is located on the left side.

As shown in FIGS. 3A and 3C, FW = “1”, BW = when the C ₂ signal 103 is delayed with respect to the CLKOUT signal 101.
Since it becomes “0”, the D flip-flops 14, 17,
The position of the data "1" in 20, ..., 23 is shifted to the right, and the delay time of the PLLOUT signal 114 with respect to the OSCOUT signal 113 increases. The increase in the delay time of the PLLOUT signal 114 corresponds to the increase in the delay time of the CLKOUT signal 101 as it is.
The delay time of the C ₂ signal 103 with respect to the UT signal 101 is relatively reduced. As a result, the C ₂ signal 103 becomes C
In the state of being delayed with respect to the LKOUT signal 101, FW = “1” and BW = “0” again, so that the delay time of the PLLOUT signal 114 with respect to the OSCOUT signal 113 increases again, and C with respect to the CLKOUT signal 101 increases. The delay time of the _two signals 103 is further reduced. This operation causes the C ₂ signal 103 to be CLKOUT.
When the process is repeated until the signal 101 goes ahead of the signal 101, FW = “0” and BW = “1”, and CLKOU
On the contrary, the delay time of the C ₂ signal 103 with respect to the T signal 101 increases. Therefore, the CLKOUT signal 101
And C ₂ signal 103 are synchronized, F
An operation is performed in which the W signal 107 and the BW signal 108 are mutually "1".

As described above, in the phase synchronizing circuit 2, the rising edges of the CLKOUT signal 101 and the C ₂ signal 103 are synchronized. And at the same time, CLK
The falling edge of OUT signal 101 and the rising edge of C ₁ signal 102 are also synchronized. Even when the CLKOUT signal 101 is synchronized with the C ₁ signal 102 and the C ₂ signal 103, the phase of the CLKOUT signal 101 is 1 of delay elements 24, 25, 26 ,.
Since the delay time for the stage is present, the delay elements 24, 2
The delay time for one step of 5, 26, ..., 27 is
It is necessary to set the delay time to such an extent that it does not affect the operation of the system, and to take this into consideration to determine the number of stages of delay elements.

Next, a second embodiment of the present invention will be described. The difference between this embodiment and the first embodiment is that the phase synchronization circuit 2 is configured by the circuit shown in FIG. 4, and other circuit configurations are the same as those in the first embodiment. It is exactly the same. Therefore, the block diagram of the entire microcomputer is the same as that of FIG.

FIG. 4 is a circuit diagram showing another example of the phase synchronization circuit 2, which includes rise detection circuits 34 and 35 formed by an inverter and an AND circuit, and R, respectively.
S flip-flop 36 and D flip-flop 37
, Transfer elements 38 to 41, capacitors 42, 44,
48, 51, 54 and 56, an operational amplifier 43, inverters 46, 49, 52 and 57, and MOS transistors 47, 50, 53 and 55, and transfer elements 38 to 41 and capacitors. 42 and 44 and the operational amplifier 43 form a switched capacitor differential integrator (hereinafter, referred to as SC differential integrator) 45. In addition, FIG. 5 (a), (b), (c),
(D), (e), (f), (g), (h) and (i)
Shown in FIG. 4 is a timing chart of clocks and input / output signals in FIG.

In FIGS. 4 and 5 (a)-(i),
In the rising edge detection circuits 34 and 35, the C ₂ signal 103 (see FIG. 5 (c)) and CLK are respectively generated.
The rising edges 105 (see FIG. 5E) and 104 (see FIG. 5D) of the OUT signal 101 (see FIG. 5A) are detected and input to the S and R terminals of the RS flip-flop 36, respectively. Then, the RS flip-flop 36 is set / reset. Q output 106 of RS flip-flop 36 (see FIG. 5 (f))
Is input to the D flip-flop 37. For the D flip-flop 37, a C ₂ signal 103 (see FIG.
(See (c)) is also input, and the V ₂ signal 110 (see FIG. 5 (h)) output from the Q terminal thereof is input to the transfer element 39 included in the SC differential integrator 45. The V ₁ signal 109 (see FIG. 5 (g)), which is the other output of the D flip-flop 37, is also SC
It is input to the transfer element 38 included in the differential integrator 45. The SC differential integrator 45 receives the V ₁ signal 109 and the V ₂ signal 110,
The V _G signal 111 (see FIG. 5 (h)) is output, and the NMO
Input to each gate of the S transistors 47, 50, 53, ...

Between the input signal OSCOUT signal 113 and the output signal PLLOUT signal 114, inverters 46, 49, 52, ... 57 and NMOS transistors 47, 50, 53 ,. , Are alternately connected, and capacitors 48, 51, 54, ..., 56 are connected between the inverters 49, 52 ,.

The operation of this embodiment will be described with reference to the timing charts shown in FIGS. Rising edge detection circuits 34 and 35
The operation of the RS flip-flop 36 is similar to that of the first embodiment described above. The output waveforms of the rising edge 105 of the C ₂ signal 103 and the rising edge 104 of the CLKOUT signal 101 output from the rising edge detection circuits 34 and 35, and the output waveform of the Q output signal 106 of the RS flip-flop 36 are shown in FIG. This is the case as shown in e), (d) and (f). Q inverted output signal 10 of the RS flip-flop 36
9 is V ₁ , the output signal 1 of the D flip-flop 37 is
Assuming that the voltage of 10 is V ₂ , the voltage V ₁ is an inversion voltage of the voltage of the Q signal 106, and the voltage V ₂ is C _{2 of the} Q signal 106.
This is the voltage synchronized by the signal 103. The capacitance 42 of the SC differential integrator 45 receives V ₁ and G by the C ₂ signal 103.
It is charged between ND, and is charged between V ₂ and the negative phase input terminal of the operational amplifier 43 by the C ₁ signal 102. Since the voltage of the negative phase input terminal of the operational amplifier 43 is tentatively set to the ground potential, if the capacitance values of the capacitors 42 and 44 are C _S1 and C _S2 , respectively, the difference voltage C due to the electric charge at the rise of the C ₁ signal 102 will be described. _S1 (V ₂ -V ₁₎
Is transferred to the capacitor 44, and the voltage V _G of the output signal 111 of the SC differential amplifier 43 is (C _S1 / C _S2 ).
It changes by (V ₁ −V ₂ ). If the power supply voltage is V _DD and the rising edge 104 of the CLKOUT signal 101 is earlier than the rising edge of the C ₂ signal 102, V ₁ =
0, V ₂ = V _DD , and in the opposite case, V ₁ = V
_DD and V ₂ = 0. Therefore, the voltage V _G of the output signal 111 of the SC differential amplifier 43 is the rising edge 104 of the CLKOUT signal 101 as shown in FIG.
However, if it is earlier than the rising edge 105 of the C ₂ signal 103, it drops by (C _S1 / C _S2 ) V _DD , and in the opposite case, it rises by (C _S1 / C _S2 ) V _DD . Note that FIG.
In the waveform of V _G shown in (i), in order to make the waveform easy to see, the voltage range is displayed differently from the voltage ranges of other signals.

The output voltage V _G is the NMOS transistor 4
55 are input to the gates of 7, 50, 53, ..., 55, and if the voltage V _G rises, the channel resistance values of these NMOS transistors 47, 50, 53 ,. _{If G} decreases, the channel resistance value of the NMOS transistors 47, 50, 53, ..., 55 increases. Corresponding to the input of the OSCOUT signal 113, via the respective inverters 46, 49, 52, ..., 57, the corresponding capacitors 48, 51, via these channel resistors,
54, ..., 55 are charged and discharged, whereby the NMOS transistors 47, 50, 53 ,.
If the channel resistance value of 5 increases, PLLOUT signal 1
If the amount of delay time for the OSCOUT signal 113 of 14 increases, and the channel resistance value of each NMOS transistor decreases, the OSCOU of the PLLOUT signal 114 increases.
The amount of delay time for the T signal 113 becomes small. That is,
When the rising edge of the CLKOUT signal 101 is earlier than the rising edge of the C ₂ signal 102, the voltage level of V _G decreases, the delay time of the PLLOUT signal 114 increases, and the CLKOUT signal 101 is delayed. Conversely, C
When the rising edge of the LKOUT signal 101 is later than the rising edge of the C ₂ signal 103, the voltage level of V _G increases, and accordingly, the delay time of the PLLOUT signal 114 decreases and becomes faster. In this way, the CLKOUT signal 101
Rising edge 104 of C ₂ and rising edge 105 of C ₂ signal 103 are synchronized.

The capacitance 44 of the SC differential amplifier 43 (capacitance value C
_S1 ) and the capacitance 42 (capacitance value C _S2 ) are set so that the value of C _S2 is sufficiently larger than the value of C _S1 , the change in V _{G in} the steady state becomes a small value. It becomes possible to output the stable CLKOUT signal 101. The inverters 47, 50, 53, ...
..., 55 stages, and capacities 47, 51, 54, ...
The value of 56 needs to be set in consideration of the output level range of the output voltage V _G of the operational amplifier 43 so as to operate stably within the level range.

[0029]

As described above, according to the present invention, even when the characteristics of the device change due to the load capacitance of the external terminal, the external temperature, the manufacturing conditions, etc., the internal system clock and the reference output to the outside are provided. Since the clock phases are synchronized, there is an effect that signals can be delivered inside and outside the microcomputer in a stable manner regardless of the usage conditions and manufacturing conditions. This effect is especially noticeable when the operating frequency is high. Is remarkable.

Further, an interface circuit for input / output, which has been conventionally required, is not required, and a phase synchronization circuit is required on the contrary, the scale of the interface circuit depends on the number of terminals of the microcomputer. Therefore, especially when the number of terminals of the microcomputer is large, there is an effect that the chip area is reduced and the cost is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a phase synchronization circuit in the first embodiment.

FIG. 3 is a timing diagram of operation signals in the phase synchronization circuit of the first embodiment.

FIG. 4 is a circuit diagram showing a phase synchronization circuit according to a second embodiment.

FIG. 5 is a timing diagram of operation signals in the phase synchronization circuit of the second embodiment.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a timing chart of operation signals in a conventional example.

[Explanation of symbols]

1, 59 CPU 2 Phase synchronization circuit 3, 60 Clock generation circuit 4, 61 Oscillator 5, 62 Output buffer 6, 63 External load capacity 7, 8, 34, 35 Rise detection circuit 9, 36 RS flip-flop 10 Edge trigger type D flip-flop 11, 46, 49, 52, 57 Inverter 12, 15, 18, 21 Composite gate 13, 14, 16, 17, 19, 20, 22, 23, 3
7 D flip-flop 24-27 Delay element 28-32, 38-41 Transfer element 33 Buffer 42, 44, 48, 51, 54, 56 Capacitance 43 Operational amplifier 45 SC differential amplifier 47, 50, 53, 55 NMOS transistor 58 Interface circuit

Claims (1)

[Claims] 1. A microcomputer comprising: a means for outputting a reference clock signal to the outside; and a means for generating an internal polyphase system clock signal based on the reference clock signal. A rising edge detecting means for detecting a rising edge of any one phase of the clock signal and a rising edge of the reference clock signal output to the outside and outputting a pair of rising edges; and the rising edge detecting means. Phase comparison means for comparing and collating the phases of a pair of rising edges output, and a phase comparison result output from the phase comparison means, with respect to a reference clock signal used for generating the internal system clock signal Delay time control means for controlling and adjusting the delay time of the reference clock signal output to the outside, Microcomputer, characterized in that a phase synchronization means including at least a synchronizing phase of the reference clock signal outputted to the inside of the multi-phase system clock and the external.