JPH05324594A - Processor - Google Patents

Abstract

PURPOSE:To avoid an overall operation stop of the processor, in the case a processor element is abnormal by providing a specific self-diagnosing means, a diagnostic flag and a deciding means, respectively. CONSTITUTION:First of all, in each processor element(PE) 9i, a self-diagnosing means 11 actuated by turning on a power source, etc., executes a self-diagnosis, and as a result, outputs a result of diagnosis being effective and ineffective in the case of being normal, and negative, respectively and sets it to a diagnostic flag 12. Subsequently, when the result of diagnosis set to the flag 12 is ineffective, that is, when the PE 9i is abnormal, it is decided by a deciding circuit 13, and unconditionally, an input/output circuit 6 outputs directly input data from an input data bus 21 to an output data bus 22. That is, in the case a certain PE 9i is abnormal, the input data comes to pass through its PE 9i, and it does not occur that an operation of the whole processor is stopped die to abnormality of the PE 9i.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, and more particularly to a distributed processor in which a plurality of processor elements are connected in a ring shape to execute processing.

[0002]

2. Description of the Related Art In a conventional processor of this type, an identifier is given to each processor element (hereinafter referred to as PE), and the processing is distributed to each PE and executed by this identifier.
However, since these identifiers are fixed by hardware, there is a problem in that the performance of the entire processor is deteriorated due to variations in the data transfer amount between PEs.

As a solution to this, for example, Japanese Patent Laid-Open No. 63-
As described in Japanese Patent Publication No. 240663, a register for storing an identifier and an identifier flag indicating whether or not this register is valid are provided, and the identifier setting which is input to the PE from the control circuit is provided by this identifier flag. It is determined whether or not the data is set in the register, and if it is not set, the identifier setting data is sent to the PE after the PE. Further, when setting, the identifier is set in the register based on the identifier setting data and the identifier flag is changed, so that the PEs can be dealt with in response to the variation in the data transfer amount between PEs. The identifier setting can be changed arbitrarily.

Referring to FIG. 2 (A), a conventional processor comprises a control circuit 1, a data bus 2, and n PEs 31 to 3n which are connected in a ring and constitute a processor. ..

Each PE 3i (1 ≦ i ≦ n) is shown in FIG.
As shown in, register 4 for storing the identifier of PE3i
An identifier flag 5 indicating whether the above-mentioned identifier of the register 4 is confirmed and valid, an input / output control circuit 6, a determination circuit 7 which is a part of the input / output control circuit 6, and an internal data bus 8.
And the input and output data buses 21 and 22.

Next, the operation of the conventional processor will be described.

First, the case where the input data is other than the identifier setting data will be described. In a certain PE3i,
When the identifier flag 5 of the PE 3i is valid, that is, when the identifier is set in the register 4, the data input from the input data bus 21 is transferred to the input data by the input / output control circuit 6 and the determination circuit 7. The inside identifier and the register 4 and the identification flag 5 are compared and determined. If the determination result of the identifier in the input data is the data given to the PE 3i, the data is sent to the internal data bus 8, and otherwise, it is sent to the output data bus 22.

Next, a case where the input data is identifier setting data will be described. When the identifier flag 5 is valid, the input / output control circuit 6 sends the input data directly to the output data bus 22 and does not affect the PE 3i. On the other hand, when the identifier flag 5 is invalid, that is, when the identifier is not set in the register 4, the identifier setting data input by the input / output control circuit 6 sets the identifier in the register 4 and the identification flag 5 is set. Was effective.

[0009]

The above-mentioned conventional processor has a drawback that it cannot operate at all if any PE constituting the processor fails.

[0010]

The processor of the present invention comprises:
An identifier corresponding to each process to be executed is given,
A register storing the identifier, an identifier flag indicating whether the identifier stored in the register is valid, and determining whether to set the identifier setting data input by the identifier flag in the register In the case of no, in a distributed processor for connecting a plurality of processor elements having an input / output control means for directly outputting the identifier setting data as output data and executing a plurality of processes, each of the processors If the element is normal, the self-diagnosis means that outputs an invalid diagnosis result if the element is valid, a diagnostic flag that holds the diagnostic result, and input data of the processor element when the held value of the diagnostic flag is invalid. It is configured to include a determination unit that determines to directly output as output data.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows an embodiment of a processor of the present invention, (A) is an overall block diagram, and (B) is a block diagram of a processor element (hereinafter PE).

As shown in FIG. 1A, the processor of this embodiment comprises a control circuit 1, a data bus 2, and n PEs 91 to 9n which are connected in a ring and constitute a processor. Has been done.

Each PE 9i (1 ≦ i ≦ n) is shown in FIG.
As shown in FIG. 3, a register 4 for storing the same identifier as that of the conventional PE 9i, an identifier flag 5, an input / output control circuit 6
An internal data bus 8 and an input and output data bus 2
1 and 22, a self-diagnosis means 11 for diagnosing whether the PE 9i is normal, a diagnosis flag 12 for holding a diagnosis result of the self-diagnosis means, and an identifier which is a part of the input / output control circuit 6 In addition to the flag 5, a determination circuit 13 that determines whether the diagnostic flag 12 is valid or invalid is provided.

Next, the operation of this embodiment will be described.

First, in each PE 9i, the self-diagnosis means 11 activated by turning on the power performs self-diagnosis, and if the result is normal, it outputs an invalid diagnosis result if it is valid, and the diagnosis flag 12 Set to. Next, the diagnosis result set in the diagnosis flag 12 is invalid, that is, P
If E9i is abnormal, the judgment circuit 13 judges this,
Unconditionally, the input / output circuit 6 outputs the input data from the input data bus 21 directly to the output data bus 22. That is, when a certain PE 9i is abnormal, the input data passes through the PE 9i, and the abnormality of the PE 9i does not stop the operation of the entire processor. If the diagnosis flag 12 is valid, that is, if the PE 9i is normal, the same operation as that shown in the example of the conventional art described above is performed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made.

For example, counting means is provided in the control circuit, the counting means is cleared at the start of identifier setting, and 1 is added each time the identifier setting data is output to the PE, and the identifiers are set in all PEs other than the abnormal PE. If so, the above identifier setting data is looped back without being set any further, so
Of course, knowing the number of normal PEs from the count value at this time can also be applied without departing from the gist of the present invention.

[0019]

As described above, according to the processor of the present invention, if each processor element is normal, the self-diagnostic means for outputting the invalid diagnostic result if the processor element is valid, and the diagnostic flag holding the diagnostic result. And a determination means for determining that the input value is directly output as the output data when the holding value of the diagnostic flag is invalid, when the processor element is abnormal, the identifier is not added and the input data is not changed. Because it only passes
The effect is that it is possible to avoid the entire stoppage of the operation of the processor.

[Brief description of drawings]

FIG. 1 is a block diagram of an overall processor element showing an embodiment of a processor of the present invention.

FIG. 2 is a block diagram of an entire processor element and an example of a conventional processor.

[Explanation of symbols]

 1 Control Circuit 2 Data Bus 3,9 PE 4 Register 5 Identifier Flag 6 Input / Output Control Circuit 7, 13 Judgment Circuit 8 Internal Data Bus 11 Self Diagnostic Means 12 Diagnostic Flag 21 Input Data Bus 22 Output Data Bus

Claims (1)

[Claims] 1. A register which is provided with an identifier corresponding to each process to be executed, stores the identifier, an identifier flag indicating whether the identifier stored in the register is valid, and an identifier flag A plurality of processor elements are connected in a ring shape with an input / output control unit that directly outputs the identifier setting data as output data when determining whether to input the identifier setting data to the register or not. In a distributed processor that executes a plurality of processes, a self-diagnosis unit that outputs an invalid diagnostic result if each of the processor elements is normal and is invalid, and a diagnostic flag that holds the diagnostic result. , When the value held by the diagnostic flag is invalid, the input data of the processor element is directly converted to output data. And a determination unit that determines to output the output.